Innovations in computational lithography for 20nm

By Gandharv Bhatara, product marketing manager for OPC technologies, Mentor Graphics.

For nearly three decades, semiconductor density scaling has been supported by optical lithography. The ability of the exposure tools to provide shorter exposure wavelengths or higher numerical apertures have allowed optical lithography to play such an important role over such an extended time frame. However, due to technical and cost limitations, conventional optical lithography has reached a plateau with a numerical aperture of 1.35 and an exposure wavelength of 193nm.  Although intended for the 32nm technology node, it has been pushed into use for the 20nm technology node.

The continued use of 193nm optical lithography at the 20nm technology node brings with it significant lithography challenges – one of the primary challenges being the ability to provide sufficient process window to pattern the extremely tight pitches. Several innovations in computational lithography have been developed in order to squeeze every possible process margin out of the lithography/patterning process.  In this blog, I will talk about two specific advances that are currently in deployment at 20nm.

The first such innovation is in the area of double patterning. As the pitch shrinks to below 80nm, double patterning becomes a necessary processing/patterning technique. One of the impacts of double patterning on the manufacturing flow is that foundries now have to perform optical proximity correction (OPC) on two separate masks after the layout has been decomposed. There are two approaches available to do this. In the first approach, each mask undergoes a separate OPC process, independent of each other. In the second approach—developed, deployed, and recommended by Mentor Graphics—the two masks are corrected simultaneously. This approach allows critical information, like edge placement error and critical dimension, to be dynamically shared across the two masks. This concurrent double patterning approach (Figure 1) ensures the best quality optimal correction, good stitching across the two masks, and significantly reduces the risk of intra-mask bridging.



Caption: Concurrent double patterning OPC corrects the two decomposed masks at the same time, sharing information between them.

The second innovation is in the area of technical advances in OPC techniques. As the process margin gets tighter, traditional or conventional OPC may not be sufficient to process difficult-to-print layouts. These layouts are design rule compliant but require a more sophisticated approach in order to make them manufacturable. We developed two approaches to deal with this situation. The first is to perform a localized in-situ optimization. This is a computationally expensive approach, which precludes it from being a full chip technique that improves printing by enhancing the process margin for extremely difficult-to-print patterns (Figure 2).

Caption: Hotspot improvement with in-situ optimization. The simulated contour lines show an improvement in line width after optimization.

In-situ optimization is integrated within the OPC framework so it’s seamless from an integration standpoint.  The second approach is a technique for post-OPC localized printability enhancement. OPC at 20nm typically uses conventional OPC and simple SRAFs. We developed an inverse lithography technique in which the OPC and the SRAFs have greater degrees of freedom and can employ non-intuitive but manufacturable shapes. This is also a computationally expensive approach, but it allows for significant process window improvement for certain critical patterns and allows for the maximum possible lithography entitlement. In this approach, you first run OPC and identify lithography hotspots (difficult-to-print patterns), then apply the localized printability enhancement techniques on the hotspots. All the necessary tooling and the infrastructure to enable this approach for all major foundries are available.

Both these advances in computational lithography are critical enablers for the 20nm technology node. In my next blog, I will talk about extension of these techniques to the 14nm technology node.

Author biography

Gandharv Bhatara is the product marketing manager for OPC technologies at Mentor Graphics.




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