STMicroelectronics and CMP announced today that ST’s H9A CMOS process (at 130nm lithography node), which offers a large panel of analog and digital devices, is now available for prototyping to universities, research labs and design companies through the silicon brokerage services provided by CMP. The diffusion of the silicon wafers will take place at the ST plant in Rousset, near Aix-en-Provence (France). ST is releasing this process technology to third parties as a foundry service for a well-established analog platform and for new developments in the More than Moore applications such as energy harvesting, autonomous intelligence, and home-automation integrated systems.
The introduction in CMP’s catalogue of ST’s H9A (and its derivative H9A_EH) process builds on the successful collaboration that has allowed universities and design firms to access leading-edge and previous CMOS generations including 28nm CMOS, 45nm (introduced in 2008), 65nm (introduced in 2006), 90nm (introduced in 2004), and 130nm (introduced in 2003) through the ST Site of Crolles. CMP’s clients also have access to 28nm FD-SOI, 65nm SOI and 130nm SOI (Silicon-On-Insulator), as well as 130nm SiGe processes from STMicroelectronics. More than 200 universities and companies have received the design rules and design kits for the ST 65nm bulk and SOI CMOS processes. Since CMP started offering the ST 28nm CMOS bulk technology in 2011, over 100 universities and microelectronics companies have received the design rules and design kits, and over 30 integrated circuits (ICs) have already been manufactured. Since CMP introduced the 28nm FD-SOI, over 30 universities and microelectronics companies have received the design rules and design kits.
“There has been a great interest in designing ICs using these processes, with about 300 projects having been designed in 90nm, which was phased out in 2009, and more than 350 already in bulk 65nm,” said Bernard Courtois, director of CMP. “In addition, more than 60 projects have already been designed in 65nm SOI and many top universities in Europe, USA/Canada and Asia have already taken advantage of the collaboration between CMP and ST.”
The CMP multi-project wafer service allows organizations to obtain small quantities–typically from a few dozens to a few thousand units–of advanced ICs. H9A design rules and design kits are now available for universities and microelectronics companies and the first requests are already being answered. A run is forecast for September 2013 to carry the first contributions.
ST will propose ULP/ULQC devices (Ultra Low Power, Ultra Low Quiescent Current) in the next Design Kit (DK) generations as this is a requirement for harvesting low-energy sources and for long-life autonomous intelligent systems.Semiconductor technology leaders ST and CMP help universities, research labs and companies prototype next generation of Systems-on-Chip.