Ed Korczynski, Senior Technical Editor, Solid State Technology/SemiMD
The most functionality at the least cost is the promise of wafer-level packaging (WLP) when dealing with complex integrated circuits (IC) with a high number of input/output connections to the outside world. Integration of heterogeneous circuit functions—such as micro- and graphics-processing, field-programmable gate array (FPGA) logic, dynamic and static memory, radio-frequency (RF) and analog, and sensing and actuating—may also be needed at the package-level to be able to deliver complete systems (Figure 1).
FIGURE 1: Heterogeneous System-in-Package (SiP) as an extension of proven flip-chip (FC) packaging technology. (Source: Amkor)
In particular, electronic systems for high-growth mobile applications require low-power and low-volume per element which dis-allows circuit integration at the printed-circuit board (PCB) level. Instead, heterogeneous integration must occur as either a system-in-package (SIP) or a system on-chip (SOC). Dr. Eric Mounier of Yole Développement, presented at the recent European 3D TSV Summit 2014 held in Grenoble, and showed Yole forecasts that total world-wide semiconductor IC wafers packaged at the wafer-scale will be 19% this year, raising to 20% in 2015.
One way of looking at the history of the IC industry is to examine the dynamic between SIP and SOC approaches. New functionalities tend to be first integrated into hardware as dedicated additional chips, to be connected in to the rest of the system as part of a PCB or SIP. Since different functionalities often require different fab processes, it is generally less expensive at the chip-level to divide functionalities into different chips, but then the packaging costs tend to be higher. Relatively low-volume parts may be most economically delivered as SIP, while higher-volume parts can often justify the additional design and test expenses of delivering the same functionality as a single SOC.
The other major reason to go with an SIP is to improve the yield of large area chips at the leading edge of fab processing. Since defects/area tend to be relatively high with a new fab process, very large chip designs will have relatively low yield at first but then will improve as the fab learns how to reduce both random and systematic yield limiters. The recent excellent example of this trend is the Xilinx Vertex-7 FPGA which splits the chip into four sub-chips and then uses a silicon interposer for SIP re-integration. We may expect that a next-generation of the product would be build in a single SOC after the yield improves, at which point Xilinx would be expected to extend the product line with additional functionality added in using multi-chip SIP.
Fan-Out WLP
Steffen Kroehnert, director of technology for Nanium S.A., gave a recent presentation at SEMICON/Singapore 2014 entitled “Wafer Level Fan-Out as Fine-Pitch Interposer.” Fan-In WLP uses layout package connections within the chip area, and when the scale and count of on-chip bond pads does not match with standard packaging scales, a Re-Distribution Layer (RDL) of metal interconnect can be used to Fan-In to ball-grid or pillar-grid arrays (BGA/PGA) within the chip-area. However, when the needed number of connections cannot be made within the chip area, packaging filler materials can be used to provide physical area adjacent to an original chip such that package connections can be arranged to Fan-Out WLP solutions use “Fan-Out” out from the chip center when seen from above.
Chip-Package-Board simultaneous co-design and co-development are becoming import instead of serial work according to Kroehnert. The penalty for re-design costs and losing strategic time-to-market for a new SiP is too high for allow for iterative R&D, such that products must be co-designed properly the first time.
FO-WLP Leveraging PV Fab Tricks
Deca Technologies, the electronic interconnect solutions provider to the semiconductor industry owned by Cypress Semiconductor, recently announced that it has shipped its 100-millionth component. The company attributes this milestone to strong demand from portable electronics manufacturers for wafer-level chip scale packages (WLCSP) manufactured using Deca’s unique, integrated Autoline production platform, which is designed to achieve faster time-to-market at lower cost.
Leveraging volume production technologies from leading silicon PV manufacturer SunPower Corp., Deca quickly achieved this milestone by addressing cycle time and capital cost challenges that semiconductor device manufacturers have struggled with using conventional approaches to WLCSP manufacturing. Deca claims that other FO-WLP technologies suffer from inherent manufacturing and reliability issues due to discontinuity at the silicon:mold-compound interface, which are avoided by the company’s use of copper-pillars and an over-mold approach (Figure 2).
FIGURE 2: Cross-section of edge of FO-WLP using Cu-pillars and over-mold approach. (Source: Deca Technologies)
Demand for WLCSP is being driven by manufacturers of wireless connectivity, audio, and power management components for mobile markets. Demand fluctuations in these markets can lead to challenges in managing inventories. “Congratulations to the Deca team on achieving this significant milestone,” said Brent Wilson, senior vice president of the Global Supply Chain Organization at ON Semiconductor. “Deca’s innovative technologies and focus on customer service have made the company a valuable part of our supply chain.”
“Reaching 100 million units is an important milestone for Deca because it validates our unique approach to WLCSP manufacturing,” said Chris Seams, CEO of Deca Technologies. “Based on the demand forecasted by our customers, we anticipate passing the half-billion mark in unit shipments this year.”
FO-WLP for the future
As thoroughly covered in our sister blog Insights From The Leading Edge, STATSChipPAC (SCP) recently announced FlexLine™ FO-WLP. The FlexLine flow dices and reconstitutes incoming wafers of various sizes to a standard size, which results in wafer level packaging equipment becoming independent of incoming silicon wafer size. The SCP FlexLine process flow is based on the SCP commercial eWLB FO-WLP process (Figure 3). Single and multi die fan-out package solutions have been in high-volume manufacturing since 2009 with more than a half-billion units shipped.
FIGURE 3: Schematic cross-sections of various Fan-Out WLP packages. (Source: STATSChipPAC)
Earlier this month, Digitimes provided a brief English translation of some Chinese-language Economic Daily News (EDN) saying that Taiwan Semiconductor Manufacturing Company (TSMC) plans to increase IC packaging revenues to US$1 billion in 2015 and to US$2 billion in 2016. TSMC co-CEO CC Wei reportedly acknowledged that the production cost for silicon-substrate SIP (TSMC’s variant termed “chip-on-wafer-on-substrate” or “CoWoS”) packages is relatively high, and so the world’s leading IC foundry intends to invest in FO-WLP technologies to be able to offer advanced packaging at a reduced price.
Wafer-level packaging continues to gain slow IC market share, and novel fan-out redistribution drives the need for improvements in existing packaging materials within tight cost and reliability constraints. With silicon-interposers and copper-interconnects part of WLP technology, the lines between chip and package have never been less clear. Managing all of this complexity is business as usual when designing mobile systems of the future.
‒E.K.