Monthly Archives: June 2013

Ongoing weakness in notebook personal computers will be offset by stronger unit growth of touch-screen tablets—especially smaller “mini” systems with 7- and 8-inch displays—resulting in a four percent increase in integrated circuit sales for all types of personal computing products this year, says a new update of IC Insights’ 2013 edition of IC Market Drivers—A Study of Emerging and Major End-Use Applications Fueling Demand for Integrated Circuits.  Combined IC sales for standard PCs, tablets, and new cloud-computing portables are forecast to reach $77.6 billion in 2013 compared to $74.9 billion in 2012, when the total fell six percent from $79.6 billion in 2011, according to the 2Q13 update to the IC Market Drivers report.

IC Insights is now forecasting a two percent decline in integrated circuit sales for keyboard-equipped standard PCs (desktops and notebooks) to $62.5 billion in 2013, following drops of 12 percent in 2012 and seven percent in 2011.  IC sales for standard PCs are slumping primarily due to slowing shipments of notebook computers, which are being superseded by tablets in consumer computing markets worldwide.  IC sales for tablet computers are forecast to rise 37 percent to $14.7 billion in 2013 after climbing 77 percent in 2012 and 190 percent in 2011.

In the new update to the IC Market Drivers report, IC Insights is raising its forecast for tablet unit shipments to 190 million systems worldwide in 2013, which would be a 62 percent increase from 117 million in 2012.  The forecast for standard PC shipments has been lowered to 347 million units in 2013, which is slightly less than a 1 percent increase from 344 million units in 2012.  IC Insights’ new forecast continues to show tablet unit shipments surpassing desktop PCs in 2013 (190 million tablets versus 150 million desktop PCs).  The updated forecast also continues to show tablet shipments exceeding notebook unit volumes in 2014, but the gap has been increased—253 million tablets versus 210 million notebook PCs next year.

IC Insights believes it now takes the sale of nearly 2.3 tablets to roughly equal the IC dollar value of one notebook PC.  The average IC content of a tablet computer is estimated at $77.50.  Nearly all tablets today are made with 32-bit microprocessors, which are often similar to application processors found in smartphones.  The vast majority of tablet processors are built with RISC cores licensed from ARM in the U.K. instead of the x86 MPU architecture used in microprocessors sold by Intel and Advanced Micro Devices for standard PCs.  ARM-based tablet microprocessors have much lower average selling prices (ASPs) than x86 MPUs—often 20 percent or less than the ASPs of PC processors.  Most tablet processors are also system-on-chip (SoC) designs with integrated graphics and many system-level functions, which reduce the need for a number of ICs and chipsets that have populated notebook PC motherboards.  Tablets also contain less DRAM memory than standard PCs, but they use NAND flash for internal storage instead of hard-disk drives.

The outlook for tablet IC sales has been increased with revenues projected to rise by a compound annual growth rate (CAGR) of about 25 percent between 2012 and 2016, reaching $26.6 billion in the final forecast year.  IC sales for standard PCs are now expected to grow by a CAGR of nearly 2 percent in the four-year period to $68.5 billion in 2016.  IC sales for new cloud-computing portable systems—such as Google’s Chromebook platform—are forecast to increase by a CAGR of 41 percent percent from about $500 million in 2012 to $1.8 billion in 2016.  These Internet-centric portables must be connected online to the web to fully function.   Low-cost cloud-computing portables are expected to be a small-but-fast growing market niche, reaching 27 million systems in 2016 compared to 5 million in 2012, according to IC Insights’ new market update report.

Challenges of EUVL HVM


June 18, 2013

By Vivek Bakshi, EUV Litho, Inc.

Most of the papers at this year’s EUVL Conference during SPIE’s 2014 Advanced Lithography program focused on topics relating to EUVL’s entrance into high volume manufacturing (HVM).

In their paper, GLOBALFOUNDRIES compared EUVL and ArF immersion scanners for 20/14nm metal lines and found equal yields for both lithog- raphy techniques. They did note an additional issue of EUV mask backside contamination, which I believe can be addressed. For 10/7nm metal lines, they believe they need to address issues of overlay, mask defects, integration and line width roughness (LWR) through focus, in order to bring EUVL into production.

Imec presented a preliminary cost of ownership (COO) study that concluded that at the 7 nm node, 75 wafers per hour (WPH) throughput will be needed for EUVL to show better COO than ArF immersion (ArFi) multiple patterning (MP). This throughput corresponds to 100 W of source power at the intermediate focus.

HVM-related metrics such as yield and availability (mean time to failure [MTTF], mean time to repair [MTTR], etc.) are now the focus. It was evident from the talk by TSMC, which reported ~10 W of power instead of the expected 30 W for their planned insertion of EUVL into the 10 nm node. A laser misalignment caused a source breakdown and a two-week unexpected downtime for the tool. Although some saw this as a setback, a brand new tool’s first installation in the field can be expected to have glitches and downtime. TSMC reconfirmed their commitment to bring EUVL into HVM at the 10nm node.

Mark Philips of Intel, in his talk, outlined the 1-D grating and cuts approach of Yan Semiconductors Borodovsky. EUVL is the preferred choice for cuts as EUVL offers advantages in terms of number of masks and edge placement error (EPE). Intel still plans to insert EUVL at the 7nm node in 2017, but needs a mature COO for EUVL. It will be either mix and match with ArFi MP or EUVL alone, depending upon the cost drivers.

As the mix and match approach faces the issue of overlay, he presented a detailed model, developed with Mike Hanna of ASML, that identifies the root cause of machine to machine overlay values and will help minimize it. Current machine to machine overlay (EUVL and ArFi) is 5 nm but needs to be 3.5 nmat10nmnodesand3.0nmat7nmnode.My perception is that with the amount of effort going into it, those goals can be achieved.

Hynix, in their paper on EUVL development efforts, made a comment that self-aligned quadruple patterning (SAQP) has 5x more steps than EUVL and that many multiple patterning steps take away any benefit that one can expect from it, and hence are not beneficial.

ASML currently has three NXE 3300B, HVM level scanners being installed in the field, including one at TSMC. They reported 30 W power (down from 50 W reported in the lab last year) with 100 W planned for this year and 250 W for next year. We know that TSMC had only 10 W at the time of conference. With ASML acquiring Cymer, I expected a change in how data is presented, with more realistic roadmaps. I understand that to predict the readiness of source is very hard, as there are many new technologies that may do well in the lab with a dozen PhDs fine-tuning them, but aren’t necessarily ready for the field where they have to perform 24 x 7 while being operated by technicians.

My personal opinion is that if we can get 50 W with decent availability in the field this year for 3300 B, it will be a great achievement. 100 W will follow over the coming years and I cannot predict yet when 250 W sources will be ready. With the data that I currently have seen, I will stick with my predictions.

Global sales of handsets featuring Near Field Communication (NFC) grew 300 percent in 2012 to reach 140 million units, according to a new research report by Berg Insight. Growing at a compound annual growth rate (CAGR) of 48.2 percent, annual shipments are forecasted to reach 1 billion units by 2017. Wider adoption of NFC in mobile phones began in 2011 and accelerated in 2012 when the top-ten handset vendors released nearly 100 NFC-enabled models. NFC technology enables numerous applications such as information exchange, device pairing for establishing Bluetooth or WLAN connections, access control, electronic ticketing and secure contactless payments. However, Berg Insight anticipates that it will take some time before the stakeholders agree on business models for payment networks and access to secure elements that store the sensitive user information in NFC-enabled handsets. Once developers gain experience with NFC and get access to a larger installed base of compatible handsets, we can also expect to see entirely new use cases not yet imagined.

“It is the sum of many possible use cases for NFC rather than one single killer application that make the technology compelling for smartphone vendors already today. Once developers gain experience with NFC and get access to a larger installed base of compatible handsets, we can also expect to see entirely new use cases not yet imagined,” concluded Andre Malm, senior analyst at Berg Insight.

Connectivity technologies such as Bluetooth, WLAN and GPS are already standard features in most smartphones. Shipments of WLAN-enabled handsets increased to 700 million units in 2012 and the attach rate reached 44 percent. Several new WLAN standards and certification programs are now being adopted to enable new use cases and improve the user experience when using WLAN in handsets. Wi-Fi Direct facilitates making device-to-device connections to enable content sharing and wireless connection to peripherals. Wi-Fi Miracast enables peer-to-peer HD video and audio streaming without cables, for instance between a smartphone and a TV. Wi-Fi Passpoint enables mobile devices to discover and connect to WLAN networks automatically without user intervention.

“Mobile operators that were initially sceptical about WLAN are now adopting a range of strategies for using WLAN as a cost-effective data offloading solution to handle the rise in data traffic from smartphones,” said Malm. He adds that WLAN is also a central component in hybrid location solutions that can enable reliable indoor navigation services. Hybrid location solutions fuse signal measurements from global navigation satellite systems (GNSS), cellular and WLAN network signals, together with data from sensors such as accelerometers, gyroscopes, compasses and altimeters.

SEMATECH, the global consortium of semiconductor manufacturers, today announced that William R. Rozich has assumed the role of chairman of the board of directors. Rozich, who previously was a member of the company’s board, succeeds Michael R. Polcari, who served as chairman since November 2009.

“The strength and commitment of our board is a great advantage for SEMATECH and we welcome Bill to his role as chairman. His extensive industry experience, familiarity with the progressive developments of our industry in Albany, NY and his leadership and insights are valuable to SEMATECH and our members,” said Dan Armbrust, SEMATECH’s president and CEO.

“I am honored to serve as chairman of SEMATECH’s board,” said Rozich. “SEMATECH has been setting global direction through the facilitation of precompetitive collaboration among its members for over 25 years, and I look forward to building on that history and collaborating with our board to address the complex, ever-changing technology landscape and the unique needs of our members.”

Rozich, who begins his new role July 1, most recently served as the director of semiconductor operations of IBM Corporation at the College of Nanoscale Science and Engineering in Albany, New York. He has more than 30 years of semiconductor fabrication operations experience and extensive interactions with equipment and materials suppliers, as well as leading complex alliances.

Rozich began his career at IBM in 1974 and progressed through a variety of assignments in equipment engineering, manufacturing technology and alliance management. He previously served on SEMATECH’s Executive Technical Advisory Board from 1994 through July 2006, the I300I Executive Steering Committee from 1995 until December 2000, and as a SEMATECH board member from 2006 to 2010.

Rozich received his bachelor’s degree in biology and chemistry from Fordham University and Marist College, as well as a Master of Arts degree in chemistry from State University of New York at New Paltz.

Samsung announced today that it has begun mass producing the industry’s first PCI-Express (PCIe) solid state drive (SSD) for next-generation ultra-slim notebook PCs.

“With the Samsung XP941, we have become the first to provide the highest performance PCIe SSD to global PC makers so that they can launch leading-edge ultra-slim notebook PCs this year,” said Young-Hyun Jun, executive vice president, memory sales and marketing, Samsung Electronics. “Samsung plans to continue timely delivery of the most advanced PCIe SSD solutions with higher density and performance, and support global IT companies providing an extremely robust computing environment to consumers.”

Samsung started providing the new SSD to major notebook PC makers earlier this quarter. The XP941 lineup consists of 512, 256 and 128GB SSDs.

The new Samsung XP941 delivers a level of performance that easily surpasses the speed limit of a SATA 6Gb/s interface. Samsung XP941 enables a sequential read performance of 1,400MB/s (megabytes per second), which is the highest performance available with a PCIe 2.0 interface. This allows the drive to read 500GB of data or 100 HD movies as large as 5GB in only six minutes, or ten HD movies at 5GB in 36 seconds. That is approximately seven times faster than a hard disk drive (which would need over 40 minutes for the same task), and more than 2.5 times faster than the fastest SATA SSD.

By mass producing the new PCIe SSD, Samsung has established the groundwork for a significant transition into the new paradigm in the global SSD market which enables increasing the performance and the memory storage capacity of SSDs at the same time.

The XP941 comes in the new M.2 form factor (80mm x 22mm), weighing approximately six grams – about a ninth of the 54 grams of a SATA-based 2.5 inch SSD. Also, the XP941’s volume is about a seventh of that of a 2.5 inch SSD, freeing up more space for the notebook’s battery and therein providing the opportunity for increased mobility that will enhance user convenience.

Samsung intends to continuously expand its production volumes of high-performance 10nm class NAND flash memory, in helping the company to maintain its lead in PCIe SSDs for ultra-slim PCs and notebook PCs. Furthermore, Samsung plans to introduce next-generation enterprise NVMe SSDs in a timely manner to also take the lead in that high-density SSD market, adding to its competitive edge.

Through a series of lectures and workshops, SEMATECH will address R&D challenges and closing key infrastructure technology gaps from July 8–12 at SEMICON West in San Francisco, CA.

SEMATECH experts will discuss the challenges which are affecting progress in next-generation lithography techniques, new materials and processes for sub-20nm manufacturing as well as present a variety of advances in new materials and device structures and lithography.

“In order to prepare for major industry transitions that will stress the industry’s resources over the next decade, we must evolve our infrastructure collaborations to address rapidly evolving technical and business model challenges,” said Dan Armbrust, president and CEO of SEMATECH.

On July 10, Armbrust will be participating in SEMI’s executive R&D panel, “A Conversation on the Future of Semiconductor Technology.” Collaborative research experts will address the technological and financial challenges in semiconductor design, process technology and manufacturing, and share how technical contributions and synergies from all sectors of the industry are required to achieve industry-wide goals.

SEMATECH experts who are scheduled to speak on the SEMICON West TechXPOT stage, in the North and South Halls of the Moscone Center include:

  • Paul Kirsch, SEMATECH’s director of Front End Processes, “Non-Silicon R&D Challenges and Opportunities,” July 9 at 11:30 a.m., South Hall
  • Stefan Wurm, SEMATECH’s director of Lithography, “EUV Lithography: Status and Outlook,” July 10 at 10:55 a.m., South Hall
  • Abbas Rastegar, SEMATECH Fellow “Challenges of Nanodefectivity,” July 10 at 11:50 a.m., North Hall
  • Mark Neisser, SEMATECH research manager, “ITRS Front End of Line Technologies: Lithography,” July 11 at 1 p.m., South Hall

Additionally, SEMATECH will host several public workshops at the San Francisco Marriott Marquis during SEMICON West:

  • Participants will address the challenges associated with infrastructure gaps, particle metrology and filtration for the reduction and prevention of nanoparticles in solutions at the SEMATECH Workshop on Nanoparticle Defectivity Issues in Solutions on July 9 at 8 a.m.
  • Equipment suppliers, semiconductor researchers and device manufacturers will discuss how they are applying new inspection and metrology technologies as well as modified or enhanced existing techniques to improve 3D interconnect processes at the SEMATECH Workshop on 3D Interconnect metrology on July 10 at 8 a.m.
  • Co-sponsored by SEMI and SEMATECH, the Enabling Supply Chain R&D through Collaboration Workshop will identify the most significant affordability challenges for semiconductor R&D and explore new collaborative opportunities that address these challenges on July 10 at 1:30 p.m.
  • A half-day preview of this year’s International Technology Roadmap for Semiconductors will be offered at the Summer ITRS Public Conference on July 11.

Some of SEMATECH’s most prominent technologists in the nanoelectronics industry will be attending SEMICON West. To arrange for meeting attendance or interviews with executives and technical experts, please contact [email protected].

 

EV Group and Dynaloy, LLC today introduced CoatsClean—an single-wafer photoresist and residue removal technology designed to address thick films and difficult-to-remove material layers for the 3D-ICs/through-silicon vias (TSVs), advanced packaging, MEMS and compound semiconductor markets.  In its official press release, EVG said CoatsClean provides a complete wafer cleaning solution that offers significant efficiency, performance and cost-of-ownership (CoO) advantages compared to traditional resist stripping and post-etch residue removal methods.

"Increasing wafer processing challenges associated with the adoption of new materials, device architectures and packaging schemes requires a new, holistic view of wafer cleaning, where the chemistry, process and equipment are all critically important and must be addressed in combination," stated Steven Dwyer, business director at Dynaloy.  "We’re pleased to be working with EV Group on developing and commercializing CoatsClean technology to meet the needs of our customers for a more cost-effective, flexible approach to thick-film resist removal."

The CoatsClean process and chemical formulation are engineered to perform at higher temperatures, resulting in faster stripping rates and cycle times.  This enables CoatsClean to operate as a single-wafer process for thick resist films and difficult-to-remove resists—resulting in improved performance, consistency, reproducibility and repeatability.  The engineered formulation also enables selective stripping of the resist.

CoatsClean is also unique in its ability to dispense a small amount of material on the top of the wafer, and then activate the material with direct heat.  This direct utilization of the material and heat dramatically reduces the strip material used.  CoatsClean uses fresh solution for each processed wafer compared to competing techniques that use an immersion bath—resulting in greater process efficiency and eliminating cross contamination.  The highly selective application of resist strip material eliminates damage to the wafer backside.  The entire CoatsClean process is performed in a single bowl, which reduces tool footprint.

"CoatsClean applies the right chemistry at the right process conditions to provide optimal cleaning results," stated Paul Lindner, EV Group’s executive technology director.  

EV Group will be responsible for selling the CoatsClean systems and providing customer support, while Dynaloy will be responsible for selling the CoatsClean resist stripping materials.  CoatsClean systems have already been installed for customer demonstrations, and EVG and Dynaloy are now accepting orders for the systems and resist stripping materials.

Dr. Deepak Sekar is a senior principal engineer at Rambus Labs. He is the author or co-author of a book, two invited book chapters, 30 publications and 100 issued or pending patents (50 issued). He is a program committee chair at the International Interconnect Technology Conference, has received two best paper awards and serves on the committee of the International Technology Roadmap for Semiconductors. 

 In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult. The solution, he said, is to supplement VLSI with what he called a Wafer Level System Integration (WLSI) paradigm. Advances in wafer level packaging and through-silicon via technology could allow systems to scale and reduce the dependence on transistor/chip scaling, according to Yu.

Figure 1: Douglas Yu of TSMC talked about WLSI

Techniques for WLSI

Yu then described TSMC’s efforts towards WLSI.

Fan-in wafer level packages, where the package is the same size as the chip, were shown with sizes as high as 52 sq. mm (see Figure 2(a)). These could be used for low pin count applications such as WiFi.

Fan-out wafer level packages, where individual die are embedded in a molding compound, could be used for higher pin count applications, said Yu. These allow placing one or more die within the same package. TSMC has qualified large 225 sq. mm fan-out wafer level packages with tight 20um pitch redistribution layer wiring (see Figure 2(b)). These fan-out wafer level packages could be used for medium to high pin count applications and also for multi-chip packages.

Figure 2: (a) A 52 sq. mm fan-in wafer level package (b) A 225 sq. mm fan-out wafer level package where the die is surrounded by a molding compound

Yu then showed TSMC’s silicon interposer and 3D-TSV technology, called CoWoS (chip-on-wafer-on-substrate). Figure 3 depicts the process flow for CoWoS and finished systems built with the technology. It is just a matter of time before TSV technologies are prevalent, he said.

Figure 3: Chip-on-Wafer-on-Substrate technology used for interposer and 3D systems

How WLSI could allow system scaling despite the increasing challenges with Moore’s Law

Significant reductions in system size are possible with wafer level packaging, interposer and 3D stacking technologies, said Yu. This is particularly beneficial to mobile applications, which show the fastest growth in the industry today. This would allow packing more and more functionality within the same form factor, something Moore’s Law is finding increasingly difficult to do.

Smart system partitioning with WLSI can benefit electronic products quite a bit, said Yu. He gave an example of partitioning digital and analog components. With finFETs moving to production, designing analog components on the same chip as logic becomes difficult due to high parasitic capacitance. Analog blocks take up more and more percentage of the chip area since they don’t scale well. In this scenario, placing analog components on a separate chip and using fan-out wafer level packaging or TSV technology to build competitive systems is beneficial, he said. This allows systems to combine analog at a trailing edge node (eg. 65nm) and logic at a leading edge node (eg. 14nm). IP blocks can be reused, time-to-market can be accelerated with smart system partitioning and yields can be improved due to the lower die size, said Yu.

System performance per watt improvement, one of the benefits of Moore’s Law scaling, can also be obtained with WLSI, according to Yu. Memory (access) power is now a key component of total system power and this is increasing with every generation. By using fan-out wafer level packaging or TSV technology, memory power can be significantly reduced due to the shorter wire lengths (Figure 4).

Figure 4: WLSI could reduce logic to DRAM wire lengths from 20mm to 0.03mm.

During the question and answer session, Yu mentioned that all of the technologies he described used pure wafer-based processes, which allowed larger packages and lower cost. Audience members, when asked about the keynote, mentioned that cost will determine how prevalent the technologies presented in Yu’s talk will become. 3D chip technologies are still considered a few years away from mass adoption.

The International Interconnect Technology Conference, held in Kyoto this year, is IEEE’s flagship conference in the interconnect field.

Imec and Renesas Electronics Corporation, a supplier of advanced semiconductor solutions, unveiled the world’s first multi-standard radio frequency (RF) receiver in 28nm CMOS technology, and a 28nm analog-to-digital converter (ADC) targeting wide-bandwidth standards such as LTE-advanced and next-generation WiFi. The companies released this new development at this week’s VLSI circuits Symposium in Kyoto, Japan.

Imec specializes in developing reconfigurable RF solutions, high-speed/low-power ADCs and new approaches to digitize future RF architectures and minimize antenna interface requirements. The company combines innovative design with advanced chip technology (28nm and beyond) to develop small, low-cost, energy-efficient RF solutions with competitive performance. Imec aims at developing solutions that cover all key broadband communication standards including emerging cellular and connectivity standards such as LTE advanced and next-generation WiFi.

The 28nm receiver is a linear software-defined radio (SDR) operating from 400MHz up to 6GHz and supporting reconfigurable RF channel bandwidths up to 100MHz. Through novel design and architecture techniques, the receiver operates at a low standard supply of 0.9V, while maintaining +5dBm of out-of-band IIP3 and tolerating 0dBm blockers.  It achieves noise figures down to 1.8dB, occupies an active area of 0.6mm2, and consumes less than 40mW.

The ADC is a 410MS/s dynamic 11bit pipelined SAR ADC in 28nm CMOS. It achieves a peak Signal-to-Noise Distortion Ratio (SNDR) of 59.8dB at 410MS/s with a power consumption of 2 mW. By combining novel digital calibration techniques with a new ADC architecture, an excellent energy efficiency was achieved. The ADC, including an on-chip calibration engine, occupies an active area of 0.11mm2.

“High-volume consumer devices require advanced chip technology that is cost-effective,” stated Joris Van Driessche, program manager of reconfigurable radios at imec. “Along with our partner, Renesas, we are thrilled to continue to offer innovative solutions to the market. Our 28nm wireless receiver brings the electronics industry closer to the development and adoption of next-generation wireless devices.”

“High level integration and low power are strongly required for recent wireless transceivers. There is every possibility of creating epoch-making architecture for RF and analog cores by using fine CMOS technology,” said Hisayasu Sato, senior manager of 2nd Analog Core Development Department, Core Technology Business Division, 1st Solution Business Unit, Renesas Electronics Corporation. “Through the collaboration with imec, we have been developing cutting-edge technologies. We continue to supply competitive IP cores and solutions to our customers.”

28nm CMOS technology

At this week’s VLSI 2013 Symposium in Kyoto, Japan, imec highlighted new insights into 3D fin shaped field effect transistors (finFETs) and high mobility channels scaling for the 7nm and 5nm technology node.         

At the VLSI 2013 symposium, imec presented the first strained Germanium devices based on a Si-replacement process, where a Ge/SiGe quantum-well heterostructure is grown by epitaxially replacing a conventional Si-based shallow trench isolation (STI). The technique allows for highly-versatile means of heterogeneous material integration with Si, ultimately leading the way to future heterogeneous finFET/nanowire devices.  The device shows dramatically superior gate reliability (NBTI) over Si channel devices due to a unique energy band structure of the compressively-strained Ge channel.

 “We are facing significant challenges  to scale the MOSFET architecture towards 7nm and 5nm. Besides dimension scaling, enhancing the device performance, in the face of rising parasitics and power, is a major focus of the logic device research at imec,” said Aaron Thean, logic devices program director at imec. “Among the key activities are R&D efforts investigating both high-mobility channel material and new methods of enhancing Si-based finFET.” 

With options to introduce heterostructure into next-generation finFET, quantum-well channels based on a combination of materials that enhance both mobility and electrostatics, can be engineered. At VLSI 2013, imec also presented comprehensive simulation work that investigated material combinations of Si, SiGe, Ge and III-V channels to enhance device electrostatics, providing important process guidance to extend finFET scalability.

Moreover, imec presented novel highly scalable engineering approaches to tune gate workfunction and improve mobility, noise and reliability in Si nMOS finFETs. The impact on the performance of layout-induced stress effects in scaled finFETs and the impact of random telegraph noise (RTN) fluctuation in lowly doped devices was shown.

Imec’s research into next-generation finFETs is performed in cooperation with imec’s key partners in its core CMOS programs including GLOBALFOUNDRIES, INTEL, Micron, Panasonic, Samsung, TSMC, Elpida, SK hynix, Fujitsu and Sony.