Precision is key to scaling below 14nm

by Debra Vogler, SEMI

In advance of the 2013 SEMICON West TechXPOTs on lithography and nonplanar transistors beyond 20nm, SEMI asked some of the speakers and industry experts to comment on the challenges they wanted to highlight. Many of the inputs focused on the need for precision in the processes used to form transistors, as well as how EDA can contribute to mitigating variability.

Likely enhancements on the logic roadmap below 20nm are a move to FinFET, improved FinFET implementation, high mobility channel, and gate all around (GAA) structures, noted Adam Brand, senior director, Transistor Technology Group at Applied Materials. He told SEMI that, “The increased complexity of the FinFET, high mobility channel, and GAA devices in combination with continued scaling requires more precision in structure formation and improved materials to address structure formation and parasitic effects.”

The key steps for maintaining the structural integrity of the fin are precision etch, void-free STI fill, recess, and precisely tailored corner rounding through dummy gate oxidation. Dummy gate oxidation addresses the challenge of ensuring that electric fields can be avoided in the corner explained Brand, who will present at SEMICON West 2013 ( “The dummy gate serves two purposes,” said Brand. “It’s a structural element and it’s there when you do the transistor formation so it can serve roles such as being the etch stop for the gate etch. It’s also able to play a role in shaping the fin.” The fin can be shaped by changing the oxidation rate depending on the amount of oxidation needed for the side vs. for the corner.

Precision again comes into play when forming the gate — precision CMP is required to control the dummy gate and replacement metal gate height. The dummy gate material must also be easily removed. “Advanced CVD materials offer more choices in materials for differentiating selective removal,” said Brand. “Implant-based precision material modification (PMM) has been effective in changing selectivity to obtain better structure control.” He noted that in the past, CMP had not played a role in directly affecting the geometry of the transistor, but now, it is playing a much more direct role in determining the size of the transistor features. For example, in the replacement metal gate step, CMP is used to polish the metals used for the replacement gate structure and it’s also used for the self-aligned contact polish. “So now, you’re polishing the gate at least three times in order to form it, and you need very precise gate height control because it affects the overall stack height and contact height.”

Further complicating transistor scaling is that the 3-D structure adds complexity in strain-related mobility enhancement. “Source/drain stressor shaping is needed to optimize strain and control unwanted increase in the Miller capacitance,” said Brand.  “Lower k dielectrics are also needed to manage the Miller capacitance.” He further explained that when strain is implemented in a FinFET, each source/drain area is a separate fin — as opposed to when strain is being implemented on planar devices. “When you grow the source/drain [in a FinFET], it grows both horizontally and vertically, so when you scale the pitch of the fins, there’s the challenge that eventually those source/drain stressors come very close to each other and they might merge.” The solution, therefore, has to allow the stressors to grow without having them merge between the transistors and still obtain the amount of strain that is wanted. The solution must also address the Miller capacitance. 

The SOI value proposition changes below 20nm

Gary Patton, VP at IBM’s Semiconductor Research and Development Center, told SEMI that in order for the full benefit of the FinFET to be realized below 20nm, a dielectric isolation scheme is necessary to counter the uniformity and variability challenges. “The arrival of the FinFET era has brought about a fundamental paradigm shift in the SOI value proposition such that the advantages of SOI-based innovation now extend well beyond just device performance as in the planar case,” said Patton.  Indeed, Soitec, and others, such as STMicroelectronics, are betting that SOI-based technology will be used as a bridge enabling the industry to get the performance benefits of a fully-depleted transistor while staying with a planar transistor all the way from 28nm down to 14nm, or perhaps even sub-14nm.

To those who question the added cost of going with an SOI-based platform, Patton said that the cost of dealing with the isolation challenge offsets the cost of using SOI substrates. “Offset costs are due to both additional process steps required for bulk, and increases to die area,” said Patton. “An STI isolation module must be added for bulk FinFETs, as well as a series of masking steps and implants for isolation-leakage control and latch-up avoidance. Estimated additional processing costs of bulk isolation offsets the cost advantage of bulk substrates over SOI.” He also pointed out that die area increases are driven by the need for well contacts, and I/O guard-rings (latch-up avoidance). “We also anticipate the overall die yield to be challenging for the bulk FinFET process due to variability and the need for matching performance of critical circuit paths in a chip.”

Another consideration for proponents of SOI-based technology is the issue of process variability. “A buried oxide layer (BOX) in SOI fins is responsible for three areas of improvement in variability over bulk-isolated FinFETs,” Patton told SEMI. “First, the top silicon layer is terminated by the buried oxide, is proven to be extremely uniform in thickness, and defines the height of the fin both physically and electrically, since any fin over etch does not contribute to the fin height.” He further explained that the source and drain are completely separated by the gated channel, unlike in a bulk FinFET, where there is a continuous path for leakage, requiring a highly doped punch-through stop.

“The non-abrupt nature of doping introduces a non-uniform doping profile, and hence, turn-on current, between the top and bottom of the fin, further eroding the FinFET advantage.” Patton noted that a more practical consideration is the slope or taper of the fin itself. “From an electrical point of view, the ideal fin would be perfectly vertical and of uniform thickness from top to bottom. In a bulk fin process, a degree of taper must allow for the subsequent oxide fill and etch-back, and also to accommodate a reduced spacer over-etch budget (vs. an SOI fin). The fin taper introduces further non-uniformity to the FinFET, which reduces switching speed.”

EDA tackles variability

Reducing/mitigating process variability is ever more critical to yield as the industry scales transistors below 20nm, and much can be done in the design arena to help. For example, EDA considerations can mitigate “noise” in the optical system [lithography] that is a source of variability.

Mike Rieger, group director, R&D, Silicon Engineering Group at Synopsys, uses communication theory to analyze certain aspects of a lithographic system. He told SEMI that when there are optical systems [lithography] without tuning, i.e., a “plain vanilla” system — all the spatial frequencies in the visible limit are present. Conversely, when the design is friendly to specific spatial frequencies and you then try to print that design with an optical system that is friendly to all spatial frequencies, there are other frequencies that leak through. This “leakage” causes a lowering of the contrast in the optical image. “With the lower contrast, the image is more susceptible to other sources of variation like defocused variation, or dose variation, and that translates into your printed features having more variation in their dimensions,” said Rieger, another speaker at the upcoming SEMICON West (

Rieger added that, if you can prevent the unwanted frequencies from even being passed through the optical system, the net result is that the contrast is improved. Additionally, by tuning these frequencies, the diffraction orders in the stepper (the rays of light used to form the image) are manipulated. “You can eliminate the zero order ray. This zero order ray reduces contrast and it also limits the maximum frequency that you can image.” The tuning process – also known as source mask optimization (SMO) – really isn’t the end game, noted Rieger. “It’s source design optimization that is the end game. You tune the configuration of your design to be consistent with the optimization of the source.”

Regarding the parallel paths the industry is taking – extending optical lithography while developing EUVL — Rieger is realistic in his assessment of what EDA can bring to the table. “We’re going to be using 193i for the foreseeable future — it will be years before 193i is replaced,” said Rieger. But, “Optical lithography on a single exposure is maxed out in terms of the density it can print, so if you want to get more transistors per chip or more details per chip, you must do a couple of things.” Those are: tuning the optics, which comes at a cost, and using multiple exposures. “To get an effective result, the whole process of the tuned optics and the multiple exposures must be comprehended in the physical layout software, and some of the things that need to be done go beyond what you can accomplish with the traditional rule-based constraint that you put on the layout.”

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