Dr. Deepak Sekar is a senior principal engineer at Rambus Labs. He is the author or co-author of a book, two invited book chapters, 30 publications and 100 issued or pending patents (50 issued). He is a program committee chair at the International Interconnect Technology Conference, has received two best paper awards and serves on the committee of the International Technology Roadmap for Semiconductors. 

 In a keynote at the IEEE International Interconnect Technology Conference (IITC), Douglas Yu from TSMC talked about Moore’s Law scaling becoming increasingly difficult. The solution, he said, is to supplement VLSI with what he called a Wafer Level System Integration (WLSI) paradigm. Advances in wafer level packaging and through-silicon via technology could allow systems to scale and reduce the dependence on transistor/chip scaling, according to Yu.

Figure 1: Douglas Yu of TSMC talked about WLSI

Techniques for WLSI

Yu then described TSMC’s efforts towards WLSI.

Fan-in wafer level packages, where the package is the same size as the chip, were shown with sizes as high as 52 sq. mm (see Figure 2(a)). These could be used for low pin count applications such as WiFi.

Fan-out wafer level packages, where individual die are embedded in a molding compound, could be used for higher pin count applications, said Yu. These allow placing one or more die within the same package. TSMC has qualified large 225 sq. mm fan-out wafer level packages with tight 20um pitch redistribution layer wiring (see Figure 2(b)). These fan-out wafer level packages could be used for medium to high pin count applications and also for multi-chip packages.

Figure 2: (a) A 52 sq. mm fan-in wafer level package (b) A 225 sq. mm fan-out wafer level package where the die is surrounded by a molding compound

Yu then showed TSMC’s silicon interposer and 3D-TSV technology, called CoWoS (chip-on-wafer-on-substrate). Figure 3 depicts the process flow for CoWoS and finished systems built with the technology. It is just a matter of time before TSV technologies are prevalent, he said.

Figure 3: Chip-on-Wafer-on-Substrate technology used for interposer and 3D systems

How WLSI could allow system scaling despite the increasing challenges with Moore’s Law

Significant reductions in system size are possible with wafer level packaging, interposer and 3D stacking technologies, said Yu. This is particularly beneficial to mobile applications, which show the fastest growth in the industry today. This would allow packing more and more functionality within the same form factor, something Moore’s Law is finding increasingly difficult to do.

Smart system partitioning with WLSI can benefit electronic products quite a bit, said Yu. He gave an example of partitioning digital and analog components. With finFETs moving to production, designing analog components on the same chip as logic becomes difficult due to high parasitic capacitance. Analog blocks take up more and more percentage of the chip area since they don’t scale well. In this scenario, placing analog components on a separate chip and using fan-out wafer level packaging or TSV technology to build competitive systems is beneficial, he said. This allows systems to combine analog at a trailing edge node (eg. 65nm) and logic at a leading edge node (eg. 14nm). IP blocks can be reused, time-to-market can be accelerated with smart system partitioning and yields can be improved due to the lower die size, said Yu.

System performance per watt improvement, one of the benefits of Moore’s Law scaling, can also be obtained with WLSI, according to Yu. Memory (access) power is now a key component of total system power and this is increasing with every generation. By using fan-out wafer level packaging or TSV technology, memory power can be significantly reduced due to the shorter wire lengths (Figure 4).

Figure 4: WLSI could reduce logic to DRAM wire lengths from 20mm to 0.03mm.

During the question and answer session, Yu mentioned that all of the technologies he described used pure wafer-based processes, which allowed larger packages and lower cost. Audience members, when asked about the keynote, mentioned that cost will determine how prevalent the technologies presented in Yu’s talk will become. 3D chip technologies are still considered a few years away from mass adoption.

The International Interconnect Technology Conference, held in Kyoto this year, is IEEE’s flagship conference in the interconnect field.