Zvi Or-Bach, President & CEO of MonolithIC 3D Inc. blogs about an ASML presentation from Semicon West. This is a follow up to a previous post: "Dimensional Scaling and the SRAM Bit-Cell."

I just downloaded the ASML presentation from Semicon West2013 site – ASML’s NXE Platform Performance and Volume Introduction. Slide #5  – IC manufacture’s road maps – says it all.

Embedded SRAM will scale from 0.09µm² at 22-20nm node to 0.06µm² at 11-10nm node. In other words only 30% reduction instead of the 4x reduction expected of historical dimension scaling, to roughly 0.02µm² !!!

In our previous blog that followed ISSCC 2013 we saw some early indication of this slowdown.  Yet we were still surprised to realize how bad it really is. This might explain why after resisting IBM and other pushes for embedded DRAM, Intel announced few month ago that its Haswell processor will incorporate embedded DRAM after all.

Another point from this ASML slide is the adaption of monolithic 3D by the NAND Flash vendors. We believe this is a start of a trend, and that logic vendors has now one more reason to follow it.