In 3D integration, wafers are thinned, stacked and connected to one another with through silicon vias (TSVs). The process of wafer thinning and TSV formation typically involves the use of a wafer bonding/debonding technology, where the wafers are bonded onto a carrier substrate – either silicon or glass – processed, and then debonded. The bonding/debonding step can be tricky because the bond has to be strong enough to withstand relatively high temperature processes and polishing steps, but not so strong as to make debonding difficult. It’s also critical that minimal stress be introduced to the device wafer during the debonding step (which can involve sliding or peeling), and that no residue remain. Room temperature debonding is also desirable.
A variety of techniques and materials have been developed to successfully achieve bonding/debonding, but Tony Flaim, chief technology officer of Brewer Science (Rolla, MO) says they are still too complicated. Brewer Science introduced the ZoneBOND technology in the 2008/2009 timeframe, and it has been implemented by tool suppliers such as EVG and SUSS. In an interview at The ConFab in June, Flaim said: “This is one of the industry’s first methods for separating the carrier from the bonded pair under low stress, low temperature conditions. It can be done at room temperature. We’ve had customers adopt that technology and are using it for some low volume production.”
High volume manufacturing of 3D integration with TSVs might not occur for another two years. To date, TSVs have been primarily used in limited applications such as image sensors where back-to-front contact is required. The first true stacked, 3D integrated device to go into production will likely be the Hybrid Memory Cube sometime next year.
“The industry is at best in low volume production with things like high density interposers and a few stacked devices, but for the most part we really haven’t seen anyone going into high volume manufacturing with the technology,” Flaim said. “What we’re trying to do, until that time arrives, is move on to a third generation of technology that will basically involve all the steps in the process and simplifying more than they are now.” He said that with ZoneBond and competing technologies, they have six basic process steps, but at a more detailed level, you can see as many as 20-25 steps. “Some of those steps are lengthy, they can be minutes or even up to hours in some cases to perform. We believe that for temporary wafer bonding technology and in fact for 2.5D and 3D integration to occur, we’re going to have to have a much simpler, more reliable, more cost-effective process. That’s really our goal for the next two years,” Flaim said.
In terms of ideal process temperature, Flaim said the bulk of their customers are working in the range of 250-260°C, but it’s clear that they want to go higher. Dielectric cure processes and deposition processes, for example, would yield better material properties when performed at a higher temperature. “We’re trying to move our whole materials set to have thermal stability at 280, 300°C or maybe even beyond. But the trick is still getting them back apart. That’s where ZoneBond and some of the other release technologies that we’re working on now will really provide the advantage. You decouple the thermal stability from how you separate from the stack. You can still be operating under a low stress, low temperature condition when you take the bonded structure apart, but the materials within the structure are surviving the high temperature.”