Semiconductor roadmapping update: Front-end technologies Part 1

In the afternoon of the last day of SEMICON/West 2013, a session was devoted to updates from the International Technology Roadmap for Semiconductors (ITRS) Front End of Line Technologies. Representatives from the different International Technology Working Groups (ITWG) provided highlights from the work now happening on the 2013 update.

Andrew Kahng of U.C. San Diego provided two presentations on challenges associated with future ICs:  System Drivers and the Design. Systems today are clearly driven by System-on-Chip (SoC) and mobile. The size of a typical mobile phone SoC is expected to double from ~50 mm2 to ~100 mm2 due to increased  integration of new functionalities such as Graphics Processing Units (GPU), memory controllers, and input/output (I/O) interfaces. Overall power for such a chip in the distant future would consume >200W of power compared to today’s ~8W unless new technologies are employed. Some future drivers such as medical and defense are now in question; will these segments develop unique devices and processes or will they simply ride on the progress of mainstream commercial IC development.

“The latter scenario is looking more likely now,” said Kahng.

Constant area-factors allowed prior node scaling to be 2x, however since 2009 the real scaling has been 2E(2/3)x or ~1.6x due to an “IC Design Gap.” This gap is due to overheads from non-core blocks and additional overheads from PIDS effects on the area needed for cores. Design cost for a SoC consumer portable chip in 2011 were $40M, helped by commercial EDA software advances over the last decades. Today only at most 2.4 percent of the logic in an SoC is turned on at any time, which is how the power can be kept to ~8W.

Modeling and Process Simulation challenges were covered by Lothar Pfitzner of Fraunhofer IISB, with understanding that the overarching goal of this ITWG is to use virtual cycle-of-learning to lower R&D costs. To do so there are different models needed in different conceptual domains, “based on quantitative physical understanding of processes, devices, circuits, and systems,” explained Pfitzner. “Both short-term and long-term challenges remain in modeling of chemical, thermo-chemical and electrical properties of new materials.”

PIDS updates on logic, DRAM, and Non-Volatile Memory (NVM) were provided by Mustafa Badaroglu of Qualcomm. PIDS mission is to forecast device technologies likely to be used 15 years in the future of main-stream manufacturing. With Denard-scaling now part of history, the specifications for future transistors using either FD-SOI or multi-gate (such as finFET) technologies require TCAD simulations of source-to-drain tunneling, band structure effects due to strong confinement, as well as crystallographic orientation and strain. The current target is an overall eight percent power reduction per year in logic, but parasitics dramatically limit device performance, and gate-length scaling is endangered by increased tunneling.

A 2013 survey recently done by the Japan PIDS regional group provides a consensus on when new devices are expected to reach volume manufacturing. For DRAM cells there has been a slight relaxation of the planned half-pitch, and  the cell size transition from 6F2 to 4F2 planned for 2016 (delayed by two years from the last ITRS update), and vertical transistors are likewise planned for 2016. RRAM is now planned as mainstream technology in 2018, and is projected to catch-up with the bit density of 3D Flash in 2021; however, development of a selector diode in a 3D architecture remains a challenge. The Purdue University TCAD tools (NanoHub) will continue to be developed to better project device characteristics, and new websites within NanoHub will be created to allow free public access to the tools.

Part 2 of this blog will cover ITRS updates on Lithography, Front-End Processing, and Emerging Research Materials/Devices.

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