Dr. Zhihong Liu, Executive Chairman, ProPlus Design Solutions, blogs about the challenges of designing for yield using SPICE models.
The ubiquitous SPICE circuit simulator, initially released 40 years ago, made a recent list of the top 10 most significant developments in the history of EDA, as it should. Its widespread use and importance among circuit designers cannot be understated.
However, the third-generation of SPICE (Simulation Program with Integrated Circuit Emphasis) simulation is showing its age. Circuit designers are doing giga-scale simulations because of complex designs, increasingly simulated post-layout and the large number of simulations required to design for variation effects.
Giga-scale designs range from post-layout analog circuits, high-speed I/Os, memory and CMOS image sensor arrays to full-chip power ICs, and clock trees and critical path nets. They require a parallel SPICE simulator with high capacity in the order of tens of millions of elements for analog designs and hundreds of million elements for memory designs. A SPICE simulator needs to deliver high performance with pure SPICE accuracy and offer support for the latest process technologies such as FinFETs.
Three dimensional FinFETs bring additional challenges to device modeling and circuit simulations. Modeling and simulation tools must be able to handle increased layout dependencies in device characteristics and more complex parasitics, including internal parasitics and interactions between the device and surrounding components.
Current SPICE simulators can offer few of these must haves. Traditional SPICE simulators lack capacity even with parallelization capabilities. FastSPICE simulators deliver capacity at the cost of accuracy and are losing steam as an increasing number of designs require post-layout verification that weakens circuit hierarchy. The FastSPICE table model approach and approximated matrix solutions can offer unreliable results and poor usability for complicated giga-scale designs with multiple operating modes and supply voltages.
The key is to maintain simulation accuracy as traditional SPICE simulators do, and simultaneously, be able to handle large circuit simulation capacity that typically only FastSPICE simulators can do with reasonable simulation time. In today’s bleeding-edge designs, designers often can’t settle for performance or capacity by sacrificing accuracy as FastSPICE simulators can.
EDA vendors are aware of these trends and the increasingly urgent market needs. Almost all existing SPICE and FastSPICE simulators have been working hard to utilize parallel technologies on multicore and/or multi-CPU computing environments to improve simulation performance. However, patched-on parallelization offers short-term improvement, and can’t fully meet the need for simulation accuracy, performance and memory consumption for giga-scale circuit designs.
New simulation technology is essential for deep-nanometer technology designs where process variations impact circuit yield and performance. In addition to capacity challenges related to increasing circuit size, designers need to run large numbers of repeated simulations to tackle the impact of process variations. Process-Voltage-Temperature (PVT) analysis and statistical Monte Carlo analysis create another challenge dimension for giga-scale simulations.
In a circuit designer’s ideal world, the next-generation SPICE circuit simulator would be highly accurate with full SPICE analysis features and support for industry-standard inputs and outputs. It would be much, much faster than traditional SPICE simulators and able to handle all circuit types. The ability to simulate giga-scale circuits and challenging post-layout designs is mandatory. Building parallelization in a SPICE simulator from the ground up instead of patched-on solutions is the key to handling giga-scale simulations with good performance and memory consumption, while still offering SPICE accuracy. Most aging circuit simulators will soon show their limitations.
Ideally, the new SPICE simulator also will have native capabilities to handle process variations from 3-sigma to high-sigma Monte Carlo simulations, where hundreds or even thousands of simulations are needed. Circuit designers have begun to search for Design-for-Yield (DFY) solutions and not just cobbled-together point tools. A total DFY solution starts with a high-capacity, high-performance SPICE simulator as its engine. A simulator designed for DFY with built-in statistical simulation capabilities can provide incomparable simulation performance when compared to ad-hoc variation analysis with external circuit simulators.
And, of course, the SPICE simulation engine should be tightly integrated with statistical transistor model extraction and yield prediction/improvement software. Those components make a total DFY solution, and enable the efficiency and consistency of yield-analysis results.
Giga-scale simulation isn’t the future, it’s here today and needs viable solutions to meet the challenges it has created. SPICE simulators have served the circuit design industry for 40 years, and it’s time for the next generation, essential for deep nanometer technology designs.