At the International Electron Devices Meeting (IEDM) in December, IBM researchers will describe a silicon nanowire (SiNW)-based MOSFET fabrication process that produced gate-all-around (GAA) SiNW devices at sizes compatible with the scaling needs of 10nm CMOS technology. They built a range of GAA SiNW MOSFETs, some of which featured a 30nm SiNW pitch with a gate pitch of 60 nm.
Devices with a 90nm gate pitch demonstrated the highest performance ever reported for a SiNW device at a gate pitch below 100 nm— peak/saturation current of 400/976 µA/µm, respectively, at 1 V. Although this work focused on NFETs, the researchers say the same fabrication techniques can be used to produce PFETs as well, opening the door to a potential ultra-dense, high-performance CMOS technology.
The integration scheme allows for a reduced, more uniform diffusion distance, affording a more abrupt junction.
A new two-step anneal process shows that the nanowires can be smoothened with no loss of density compared to planar processes.
The TEM electron microscope images above show: a) a cross section of a completed device through a gate, illustrating the spacer, epitaxial source/drain and contacts; (b) the cross section of a silicon nanowire (SiNW) decorated with a high-Z film to better show the nanowire’s boundary. The effective SiNW diameter shown is 12.8 nm; (c) a close up of the region of interest indicated in a), showing that the source/drain is epitaxially regrown from the cut face of the nanowire. The lattice planes in the epi region are registered to that of the original SiNW channel (parallel red dashed lines).