Nanoelectronics research center imec and Excico have successfully demonstrated the application of laser thermal anneal (LTA) to boost the current in vertical polysilicon channel devices for 3D memory. Due to the larger grain size of the laser recrystallized polycrystalline channel material, up to 10 times higher read current and 2.5 times steeper sub-threshold slope could be obtained as compared to conventional polysilicon channel. This technique provides a way to higher stacking and therefore higher bit density in 3D memory.

Three-dimensional vertical poly-Si channel devices are considered prominent alternatives for many technologies and in particular for new generation nonvolatile memory applications. In such solutions, vertical poly-Si channel transistors are used both as memory cells and as string select transistors. Because devices are typically fabricated with a gate-first, channel-last approach, the formation of single-crystal silicon channel is complicated or even prohibitive. As a result, electron conduction is dominated by scattering at grain boundaries and interface defects of the polycrystalline channel material, significantly decreasing the drive current needed for the read operation.

As a result, grain size engineering is required to obtain larger grains and hence less grain boundaries. Imec and Excico researchers have accomplished this by channel formation with amorphous Si deposition followed by pulsed laser annealing (Excico LTA series, wavelength λ=308 nm, pulse duration < 200 ns). LTA dose needs proper adjustment in order to optimally crystallize the channel (too low doses are not effective whereas too high doses compromise device integrity). Grain structure was inferred from TEM analysis, showing increasingly larger grains from as-deposited, to furnace, to laser recrystallized polysilicon.

In LTA recrystallized polycrystalline channel material, up to 10 times higher read current and 2.5 times steeper sub-threshold slope, could be obtained as compared to other polysilicon channel. Larger grains are obtained that result in less grain boundaries which in turn leads to higher effective mobility, less temperature activation of the conduction mechanism.

Also memory operation was evaluated in cells with ONO (oxide-nitride-oxide) memory stack as well as in macaroni-type cells with a dielectric filler in the center (not shown). Main memory characteristics such as program/erase characteristics, endurance and room temperature retention on fresh and program/erase cycled devices were independent of crystallization thermal treatment, proving that optimized LTA does not impact memory operation. This observation is crucial for the successful fabrication of advanced vertical memory stacks using LTA.

These results were achieved in the framework of imec’s Industrial Affiliation Program on Advanced Memory Devices, with imec’s memory core partners including Intel, Micron, Samsung, SK Hynix, GLOBALFOUNDRIES, Panasonic, as well as Toshiba and SanDisk.