Model-based hints: GPS for LFD success

By Joe Kwan, Mentor Graphics

For several technology nodes now, designers have been required to run lithography-friendly design (LFD) checks prior to tape out and acceptance by the foundry. Due to resolution enhancement technology (RET) limitations at advanced nodes, we are seeing significantly more manufacturing issues [1] [2], even in DRC-clean designs. Regions in a design layout that have poor manufacturability characteristics, even with the application of RET techniques, are called lithographic (litho) hotspots, and they can only be corrected by modifying the layout polygons in the design verification flow.

A litho hotspot fix should satisfy two conditions:

  • First, implementing a fix cannot cause an internal or external DRC violation (i.e., applying a fix should not result in completely removing a polygon, making its width less than the minimum DRC width, merging two polygons, or making the distance between them less than the minimum DRC space).
  • Second, the fix must be LFD-clean, which means it should not only fix the hotspot under consideration, but also make sure that it does not produce new hotspots.

However, layout edges that should be moved to fix a litho hotspot are not necessarily the edges directly touching it. Determining which layout edges to move to fix a litho hotspot can be pretty complicated, because getting from a design layout to a printed contour involves a bunch of complex non-linear steps (such as RET) that alter the original layout shapes, and optical effects that take into account the effect of the layout features context. Since any layout modifications needed to fix litho hotspots must be made by the designer, who is generally not familiar with these post-tapeout processes, it’s pretty obvious that EDA tools need to provide the designer with some help during the fix process.

At Mentor Graphics, we call this help model-based hints (MBH). MBH can evaluate the hotspot, determine what fix options are available, run simulations to determine which fixes also comply with the required conditions, then provide the designer with appropriate fix hints (Figure 1). A fix can include single-edge movements or group-edge movement, and a litho hotspot may have more than one viable fix. Also, post-generation verification can detect any new minimum DRC width or space violations, but it will not be able to detect deleting or merging polygons, so the MBH system must incorporate this knowledge into hint generation. Being able to see all the viable fix options in one hint gives the designer both the information needed to correct the hotspot and the flexibility to implement the fix most suitable to that design.

Figure 1. Litho hotspot analysis with model-based hinting (adapted from “Model Based Hint for Litho Hotspot Fixing Beyond 20nm node,” SPIE 2013)

Figure 1. Litho hotspot analysis with model-based hinting (adapted from “Model Based Hint for Litho Hotspot Fixing Beyond 20nm node,” SPIE 2013)

Another cool thing about MBH systems—they can be expanded to support hints for litho hotspots found in layers manufactured using double or triple patterning, by using the decomposed layers along with the original target layers as an input. This enables designers to continue resolving litho hotspots at 20 nm and below. In fact, we’ve had multiple customers tape out 20 nm chips using litho simulation and MBH on a variety of designs to eliminate litho hotspots

Of course, it goes without saying that any software solutions generating such hints also need to be accurate and fast. But we said it anyway.

As designers must take on more and more responsibility for ensuring designs can be manufactured with increasingly complex production processes, EDA software must evolve to fill the knowledge gap. LFD tools with MBH capability are one example of how EDA systems can be the bridge between design and manufacturing.


Joe Kwan is the Product Marketing Manager for Calibre LFD and Calibre DFM Services at Mentor Graphics. He previously worked at VLSI Technology, COMPASS Design Automation, and Virtual Silicon. Joe received a BA in Computer Science from the University of California, Berkeley, and an MS in Electrical Engineering from Stanford University. He can be reached at [email protected].


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