3) Porous Silicon for Integrated On-Chip Energy Storage

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Capacitors are favored over batteries for some energy storage applications because they can capture energy at high rates and lower voltages, as well as provide higher power (albeit at lower energy densities). They also don’t degrade significantly over thousands of charging cycles. These properties come about because capacitors are electrostatic devices and don’t rely on chemical reactions to store energy, as batteries do.  Intel researchers built and studied electrochemical (EC) capacitors based on porous-silicon (P-Si) nanostructures coated with various atomic layer deposited (ALD) films. Measurements of the coated P-Si capacitors showed that a high capacitance can be achieved (3 milliFarads/cm2 was shown), which is contrary to studies of uncoated porous-silicon capacitors. The devices were fabricated with conventional silicon technology, opening up the potential to integrate them on a single die with silicon CMOS circuits, sensors or energy-harvesting systems like silicon solar cells. This can be done either by forming the pores in localized regions on the front side of the die, or by utilizing the backside bulk silicon. The researchers will detail how they optimized the porous-silicon nanostructure (i.e. surface area, pore morphology, etc.) and the surface-coating processes. Some of the porous-silicon electrochemical capacitors they built that had a TiN coating, exhibited stable capacitance even after 1,000 cycles at 50 mV/sec.

In the illustrations above, (a) is a series of scanning electron microscope (SEM) images which demonstrate that by controlling various etch conditions such as current density (shown), it is possible to vary the porous-silicon structure. The two colored images at the bottom show the image-analysis code that was used to quantify the porous-silicon structures; (b) shows a tapered porous-silicon nanostructure created by changing the current density during etching; (c) cross-sectional images of carbonized porous-silicon deposited at 500ºC (left), then at 720ºC with acetylene gas (right); and (d) SEM images of the top of the porous-silicon region before (left) and after (right) stop-flow ALD TiN deposition. The pore walls get thicker but the overall pore structure doesn’t change.

(Paper #8.2, “Integrated On-Chip Energy Storage Using Porous-Silicon Electrochemical Capacitors,” D.S. Gardner et al, Intel)

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