ANDREW HO, Global Industry Director, Advanced Semiconductor Materials, Dow Corning, Hong Kong.

New technology eliminates the need for specialized equipment for wafer pre- or post-treatment.

Advances in three-dimensional (3D) through-silicon via (TSV) semiconductor technology promise to significantly improve the form factor, bandwidth and functionality of microelectronic devices by enabling once-horizontal chip structures to be fabricated as vertical architectures. The challenges to implementing 3D-IC TSV integration are not trivial, and the search for a solution has prompted exploration of several schemes. These are frequently labeled as via-first, via-middle or via-last depending on the position where the 3D TSV fabrication takes place.

Figure 1: A thing silicon wafer on diving frame after successful debonding from a silicon carrier wafer at imec, using Dow Corning’s silicon-based temporary bonding solution. Image courtesy of and copyright owned by imec

In via-first integration, TSVs are formed before processing the front-end-of the line (FEOL) layers, which enables high thermal budget processing for TSV insulation and filling. In via-middle schemes, TSVs are added between FEOL and back-end-of-the-line (BEOL) stacking to allow several copper-based interconnections. In a via-last approach, fabrication of TSVs occurs after completion of FEOL and BEOL processing, either from a wafer’s front or back side. This approach generally addresses applications in which low density 3D interconnections are adequate.

In all these approaches, however, TSV fabrication is problematic without thinning the active silicon wafer down to 50µm or less (FIGURE 1) – about half the thickness of a standard piece of printer paper – and therein lies the challenge. In order to handle such ultra-thin wafers, the industry requires solutions that can easily, cost-effectively and temporarily bond and debond active wafers to carrier wafer systems for subsequent wafer thinning and TSV fabrication.

Temporary bonding solutions: A primer

Wafer thinning is already widely applied for IC manufacturing, as well as the manufacture of power devices and image sensors. Depending on process requirements and applications, wafer bonding can be divided into several techniques including direct bonding, anodic bonding and thermo-compression adhesive bonding and others. For 3D-IC integration, however, the most commonly explored approach is attaching device wafers to a carrier wafer for support with the use of polymer-based temporary adhesives. As shown in FIGURE 2 A typical process flow for the use of such temporary bonding solutions first applies a release and an adhesive layer, either on the device or the carrier wafer. After this the device and carrier wafers are bonded together. Subsequent steps, in sequence, involve wafer thinning, TSV reveal or fabrication, formation of redistribution layers and wafer interconnect fabrication, debonding and cleaning of the processed ultra-thin device wafer and, lastly, 3D stacking of the thinned device wafers.

Figure 2: A typical process flow for temporary bonding and debonding solutions.

Central to the success of this approach is the polymer adhesive, which must protect the ultra-thin wafer while withstanding the harsh chemicals and thermal stresses imposed by wafer thinning and 3D-IC TSV integration processes. Specifically, temporary bonding/debonding (TB/D) solutions must demonstrate excellent thermal and chemical stability to withstand the plasma processes as well as the solvents, bases and acids used by 3D-IC TSV processes. In addition to delivering excellent adhesive properties to withstand the mechanical stress of the wafer thinning process, temporary adhesives must also be able to maintain global high uniformity of the adhesive layer as characterized by a low total thickness variation (TTV) across the device wafer through all processing steps to reach a typical target of 2 µm TTV on the thin device wafer (FIGURE 3). In addition, these materials must enable low-temperature debonding compatible with different interconnect technologies using solder bumps or copper pillars, and offer a simple wafer cleaning process that will damage neither the underlying layers of the processed device wafer nor the tape on which the thinned wafer stands after debonding.

Figure 3: Measurements of a temporarily bonded active water (post-thinning) show total thickness variation to be approximately 4µm.

The potential of polymer-based TB/D solutions has prompted exploration of several material technologies coupled with various equipment platforms and wafer treatments. As development of these and other TB/D solutions advance, 3D-IC TSV integration has yet to become a mainstream technology due to its additional costs and challenges on thin wafer handling. These costs derive not only from the sophisticated materials used, but also the multiple pre-treatment steps that temporary bonding and debonding processes have traditionally required. While these painstaking steps help to ensure high yields and protect the high value of fully functional device wafers, they also hinder 3D-IC TSV integration from moving to volume production and, ultimately, they contribute to a higher total cost of ownership.

Figure 4: Wafers spin-coated with the temporary adhesive and then cured tested the materials chemical resistance by soaking it in phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. The temporary bonding material showed negligible weight loss or gain for all chosen chemicals.

Minimizing total cost of ownership is essential for all semiconductor manufacturing applications. But it is a critical enabler for next-generation technologies, such as 3D-IC TSV integration. Recent innovations by Dow Corning and industry collaborators have shown promising development of a simpler, more cost-effective temporary bonding solution based on silicone adhesive and release layers. Importantly, this new solution enables room-temperature bonding and room-temperature mechanical debonding of active and carrier wafers using conventional, high-volume manufacturing methods.

A new bilayer temporary bonding/debonding concept

At the center of this new approach is a simple bilayer concept based on two silicone materials that serve as the temporary bonding materials during the fabrication of thin wafers for 3D-IC TSV integration. It applies a process flow that greatly simplifies the temporary bonding/debonding process, and reduces costs associated with special equipment for pre- or post-process treatments of the device wafer such as plasma, ultra-violet, preferential zone treatment and others.

The first step in the process flow is the spin coat of the temporary bonding materials. This step is critical to minimizing delays in process time, as the total thickness variation (TTV) of the spin coated material can contribute to the TTV of the bonded pair and, later, transfer to the thin wafer during the wafer thinning and post processing of bonded wafer pairs. Thus it is important to start with a low TTV for spin coated films. Notably, the process described here targets TTV for coatings on the device wafer to a range of within 1 percent.

The spin coat step first applies a continuous release layer onto the front side of the device wafer, ensuring the layer entirely covers any micro-structures present. Next, comes spin coat application of a silicone-based adhesive layer of a few tens of microns in thickness – depending on the device wafer’s topography – on top of the release layer. The adhesive layer developed for this process is designed to obtain excellent uniformity and planarization over high bump topographies. It allows single-layer thicknesses between 10 and 110 µm to provide process simplicity.

After application of both layers, the device and carrier wafer are bonded. The carrier wafer can be either silicon or glass, and it does not require any particular pre-processing. Prior to the bonding step, application of vacuum assures no air bubbles are trapped in the adhesive, which is viscous. After degassing, the carrier is dropped onto the device wafer.

Importantly, bonding occurs at room temperature, which greatly improves the opportunity for increased throughput. Also, the silicone-based adhesive is still in its wet state at this point. So, no force is required to bond the pair. Thus, this technology offers the potential to accommodate fragile ultra-low dielectric constant materials used within advanced copper interconnects that are very sensitive to the application of force. The total time for this step takes a couple of minutes, followed by a post-bonding bake on a hotplate – typically at 150° C for a few more minutes – to cure the adhesive layer.

Wafer processing now proceeds with backgrinding and associated process control. Following post-bonding, the bonded pair is mechanically debonded at room temperature along the release to adhesive layer interface. The thinned device wafer remains on a tape on a frame, available for release layer cleaning followed by dicing, pick-and-place and stacking steps. The carrier wafer, still covered with adhesive, is processed for chemical recycling.

Able to withstand real-world processes

Candidate TB/D materials must deliver excellent thermal stability to ensure that the bond remains strong during the various processing steps involved in the copper nail reveal step and formation of redistribution layers on the device wafer. It is also critical that candidate materials do not outgas during post-bond processing, as this can lead to voids or delamination that, ultimately, can contribute to device failures.

Thermal analysis of both the release and adhesive materials used in this new approach heated the thinned bonded pair to 200° C on a hot plate in air for 20 minutes; and then to 200° C in air for three hours, where it passed solder bump reflow conditions at 260° C for 10 minutes; and finally to 200° C for three hours under vacuum. Scanning acoustic microscopy analysis after each test showed no voids or delamination.

These results underscore that both TB/D materials developed for the approach described above can not only hold up under the rigors of conventional backgrinding processes, they can also deliver the thermal stability necessary to withstand the plasma processes applied to the wafer pair during the fabrication of 3D-IC TSV architectures.

Strong chemical resistance is also critical for candidate TB/D materials to ensure they can perform reliably without delaminating or swelling when exposed to the several wet processes that thinned wafers undergo. Testing of the release and adhesive layer materials began by spin coating a wafer with the temporary adhesive, curing it using described protocols and then soaking it in phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. The temporary bonding material showed negligible weight loss or gain for all chosen chemicals (FIGURE 4).

One of the most important enablers of broader adoption of TB/D solutions is the ability to debond thinned device wafers from carrier wafers, and clean any residues from the device wafer without adversely affecting device yields. The new bilayer TB/D concept described above leverages a room-¬temperature peel debond, and has been demonstrated on several conventional, commercially available debonding platforms from leading equipment providers.

The process begins by first mounting the thinned wafer pair onto a dicing tape and holding it in place on a vacuum chuck while peeling off the thick carrier wafer. Because the solvent dissolvable release layer is applied to the thin device wafer with dicing tape exposed, no harsh silicone removers or other strong acids need be applied. The entire debond process takes less than five minutes, including clean-up of the device wafer.

Conclusion

While TB/D materials and equipment continue to evolve in sophistication, broader adoption of this technology and the 3D-IC TSV integration that it enables cannot advance at the expense of simple processing, device yields or total cost of ownership. The emergence of Dow Corning’s simple, bilayer TB/D bonding solution achieves all these goals by eliminating the need for specialized equipment for wafer pre- or post-treatment.

Comprising an adhesive and release layer, the technology has demonstrated excellent spin coating and room temperature bonding performance with low TTV, even for very thick layers up to 110 µm. Proven on commercially available high-volume production equipment, it has shown excellent chemical stability when exposed to phosphoric acid, nitric acid, organic solvents and other chemicals familiar to TSV fabrication. In addition, the bonding solution and paired wafers showed good thermal stability when exposed to the 300° C temperatures common to post-bonding 3D TSV processes. •

ANDREW HO is the Global Industry Director, Advanced Semiconductor Materials, Dow Corning. E-mail: [email protected].