COURTNEY HAZELTON, JOSH ROBERGE and ALLEN PAGE, Texas Instruments, Dallas, TX.
ROBERT NEWCOMB, BILL USRY and JOEL HICKSON, Qcept Technologies, Atlanta, GA.

Improving economic competitiveness through cost reduction, cycle time improvement and more eco-friendly processing.

Leading-edge semiconductor device manufacturers utilize advanced inspection technologies to detect and reduce the impact of yield-critical defectivity issues. This is especially true during the development of a new technology node and the subsequent ramp to high-volume manufacturing. Traditionally, the defect inspection focus was on physical defects, but the proliferation of new materials, new processes and new device structures has resulted in the need to detect yield-critical non-visual defects (NVDs), including sub-monolayer residues and process-induced charging of dielectric films. Leading-edge fabs are utilizing a scanning probe system that detects changes in surface work function or charge build-up of a dielectric film to detect and reduce the impact of yield-critical NVDs [1-5].

There are numerous mainstream semiconductor fabs, including 200mm and trailing edge 300mm fabs that have established high yielding processes. Applying a leading-edge technology for NVD inspection to a mainstream fab would typically face a significant barrier to entry given their end of line (EOL) yields and the challenge of justifying higher cost new equipment from a return on investment perspective. Mainstream fabs must therefore focus engineering resources on more than just yields in order to maintain the economic competitiveness of their products. They must also focus their efforts on cost reduction through lower materials usage, higher tool utilization through more optimized processes and fab capacity management through mix and match of equipment from different vendors. Additionally, the fabs look for more eco-friendly processes that reduce overall use and disposal of chemicals, deionized water and other effluents.

In this paper, we present data on how a 200mm mainstream analog fab achieved significant economic benefit from using an advanced ChemetriQ NVD inspection system manufactured by Qcept Technologies [6-7]. The highlighted case studies provided an annual savings of US $3.0M per year – and a further US $3.5M one-time savings in capital expenditures for a new wet process tool due to higher capacity with their existing tools.

Reduced packaging costs

For certain devices, the analog process flow required the insertion of an additional back end of line (BEOL) process loop in order to deliver the requisite device capabilities. Based on EOL yield data and failure analysis, it was determined that this additional loop was leaving a thin edge residue that was not detectable by existing optical inspection tools. This residue affected 15% of lots in the production line. In addition to the sunk cost of assembling these defective die, the failure rate for the bad lots resulted in delayed revenue from the good die and higher incurred costs to perform extensive failure analysis to prove the yield loss was attributed to the edge residues and not a different reliability risk.

Fab engineers determined that the ChemetriQ NVD inspection tool was the only system capable of detecting the thin edge residue in the fab. An inline NVD inspection was subsequently implemented on 100% of production wafers after the plasma etch and clean process. FIGURE 1A provides an example of a bad wafer where the edge residue is detected in the outer region of die. It was determined that this residue failure mode was isolated to die near the edge and so the inspection recipe was optimized for this specific NVD. In FIGURE 1b, threshold analysis was used to automatically flag wafers as bad if they had the edge residue, and the data enabled the fab to determine how far the residue encroaches into the wafer interior.

The inline inspection data from the NVD inspection tool was then used to feed forward the region with known bad die so that these die can be ink marked post fab and no longer packaged. Eliminating the packaging of known bad die has resulted in a recurring US $900,000 per year savings. Additionally, the customer reject rate was reduced from 15% to 0% after implementing this new inline inspection protocol – resulting in an additional recurring savings of US $900,000 by eliminating the need for failure analysis.

Reduced Chemical Costs

The second use case involves a BEOL solvent clean process where the process of record used back-to-back isopropyl (IPA) baths where the IPA chemicals are changed after every ten production lots. Fab engineers had previously proposed a process change that would reduce IPA chemical usage by 50%, but the change was not approved because the fab lacked a method to detect non-visual residues that could have a negative impact on yield or even worse, result in reliability failures in the field.

The proposed process change was re-evaluated with the ChemetriQ NVD inspection tool to demonstrate the process robustness and latitude. The new process reused IPA chemicals from the second (clean) bath to the first (dirty) bath resulting in each batch of IPA to be used for twenty production lots for a 50% reduction in chemical usage. FIGURE 2 shows two residue free NVD inspection results for a wafer from the 1st production lot and 10th production lot while implementing the IPA reuse approach from the second bath to first bath.

The new process was implemented after this second study because the fab was confident that the new process would be robust based on the combination of the NVD inspection results, which showed that the wafers were residue free, with data such as particle checks and electrical split lot qualification. The 50% reduction in IPA usage for this back end of line solvent clean process resulted in US $720,000 per year savings for this one process step.

Higher throughput and more eco-friendly process

The final use case involves optimizing the process throughput for a FEOL RCA clean process by reducing the total deionized water (DIW) rinse time. The RCA process used a two-step final rinse with a Quick Dump Rinse (QDR) technique. The goal was to reduce the total rinse time by 50% from the process of record while ensuring that the shorter rinse was thorough enough to remove the clean chemistries without leaving residues.

The design of experiments for the proposed process change used multiple inspection tools and electrical qualifications, including NVD inspection, optical inspection, electrical gate oxide integrity (GOI) and electrical EOL probe results. For the NVD inspection portion, wafers were processed through the two-step QDR tanks ranging from 10% to 100% of the standard rinse time using increments of 10%. The goal was to determine at which point the rinse time was no longer effectively removing the cleaning chemistry.

FIGURE 3 shows the NVD inspection results for three wafers from this study including the 100%, 50% and 10% splits. The results indicate that the efficacy of the 10% QDR split is very poor as a significant level of surface residues are detected on the wafer in FIGURE 3c. The 50% QDR split provided effective rinsing of the wafer, which was verified with numerous confirmation runs. Electrical qualification lots were run comparing the 100% QDR process to the 50% QDR process and both the GOI data and final probe data as shown in Figure 4 showed good electrical performance for the proposed process.

The new 50% QDR rinse time process was approved, which resulted in numerous benefits for the fab, including (a) a 14,000,000 liter reduction in DIW usage for this one RCA clean process; (b) a 25% increase in the wafers per day throughput of the wet bench system; which in turn resulted in (c) the fab cancelling a planned $3.5M expenditure for a new wet bench system because the existing tools could now meet the higher wafer start levels without the need of more tools.

Table 1.

Summary

Table 1 summarizes the economic benefits achieved from the three case studies covered in this article as well as three other examples. These include (a) resolving a charge induced yield issue on a “new” used tool where the fab had to mix-and-match different tools from different vendors for the same process; (b) implementing an inline NVD inspection step to detect yield excursions due to ozone generator reliability issues and high water content in the process bath; and (c) optimizing a litho rework process to eliminate non-visual BARC residues that resulted in lower yields for lots that were reworked as compared to lots that were not reworked.

In summary, both 200mm and trailing edge 300mm mainstream fabs face many challenges, including how to improve their economic competitiveness. In this article we have presented use cases from a 200mm mainstream analog fab that utilized advanced NVD inspection technology to reduce costs, provide higher throughput for process tools and deliver more eco-friendly processing. The economic benefit of the use cases shown in Table 1 exceeds US $3.0M per year of recurring savings plus a one time savings of US $3.5M in capital.

Acknowledgements

This article is based on an oral presentation given at the 2013 SEMICON West TechXPOT Productivity Innovation track focused on reducing cost and improving performance at 200/300mm wafer fabs. •

Bibliography

W. Kang, et al; SEMATECH Surface Preparation and Cleans Conference / Solid State Technology (June 2013); Detection and Elimination of a Yield Critical Non-Visual Residue Defect at a Gate Module Etch and Clean Process (2013)

D. Scranton, et al; SEMATECH Surface Preparation and Cleans Conference / Solid State Technology (April 2008); Optimization of a Post Via Wet Clean Process using a Novel, Full Wafer Inspection Technique for Non-Visual Defects (2008).

J. Park, et al; SEMATECH Surface Preparation and Cleans Conference / Solid State Technology (July 2012); Impact of Charge at Gate Oxide Patterning on Yield for an Advanced Technology Node (2012).

Y. Yamada, et al; SEMATECH Surface Preparation and Cleans Conference; Charge-Induced Attraction of Particles in Post CMP and Megasonic Clean Processes (2010).

J. Hallady, et al; SEMATECH Surface Preparation and Cleans Conference; Elimination of Electro-Static Discharge (ESD) Defects Using DICO2 (2008).

J. Raine, et al; SEMICON West Productivity Innovation TechXPOT; Applying Non-Visual Defect Inspection to an Existing Mainstream Fab to Reduce Costs, Increase Tool Utilization, and Deliver Eco-Friendly Processing (2013).

J. Hawthorne, et al; MICRO Magazine; Inspecting Wafers Using a Potential Difference Imaging Sensor Method (Feb 2005).

COURTNEY HAZELTON is a senior surface preparation engineer, JOSH ROBERGE is a senior product engineer, and ALLEN PAGE is a senior BEOL cleans and plasma etch engineer at Texas Instruments, email: [email protected] ROBERT NEWCOMB is an executive vice president, BILL USRY is a senior applications engineer, and JOEL HICKSON is product marketing manager at Qcept Technologies, Atlanta, GA, email: [email protected]