The need for high sigma yield

By Dr. Bruce McGaughy, Chief Technology Officer and Senior Vice President of Engineering, ProPlus Design Solutions, Inc.

In the mid-1990s, the former head of General Electric Jack Welch and Six Sigma were all but synonymous. Many a corporation implemented Six Sigma to improve process quality, based on Welch’s outspoken endorsement of the program.

Today, the semiconductor industry is using similar terminology to refer to high sigma yield prediction, a means to statistically determine the impact of process variations on parametric yield for integrated circuits such as SRAM that require extremely low failure rate.

No one needs to be Jack Welch to know why. In fact, it’s a huge challenge for the industry and it has been getting the attention it deserves of late –– the move to state-of-the-art 28nm/20nm planar CMOS and 16nm FinFET technologies present greater challenges to yield than any previous generation.

The key challenge is high sigma yield analysis that covers yield from roughly the 4 to 7+ σ range –– the range where traditional Monte Carlo simulation methods break down due to the requirement of high-sample numbers with associated long run times. For 3 σ designs, Monte Carlo continues to be a viable solution.

Foundries now require SRAM memory verification to 7 σ in 16nm FinFET technology, a technical impossibility without deploying a special high sigma yield prediction tool. The reason memory bit cell yield targets are being set so high is due to large process variations and shrinking design margins at advanced nodes and larger memory sizes. Most commercially available tools are unable to address 7+σ reliably or accurately.

Multiple methods are available to tackle the high sigma challenge, discussed at length in a recent ProPlus whitepaper. The key is an accurate and reliable estimate of yield out to very high sigma values with a reasonable number of simulations.

High Sigma methods that utilize Monte Carlo as the foundation are able to take advantage of its robustness but overcome its inability to scale to high sigma analysis. Designers are further pushing the high sigma boundary running the analysis on larger and larger blocks, such as an SRAM array. The requirement to analyze large designs with tens of thousands of variables creates a compounding effect on the high sigma problem.

This gives a glimpse into the scope of the high sigma challenge. On the one hand, there is a need to validate yield out to 7+ σ ranges. On the other, there is pressure to run high sigma analysis on large designs.

Yes, challenges abound. More than one industry expert is calling for an integrated design for yield (DFY) flow to answer the challenge. That’s because the conventional design flow is outmoded and struggling under the weight of these weighty requirements. An integrated DFY flow, advise the experts, needs accurate statistical device modeling and a powerful SPICE simulator. Most important, the new flow needs yield prediction, analysis and fixing capabilities that can cover requirements from 3 to 7+ σ yield.

Few tool providers today offer all three in an integrated DFY flow. In fact, most electronic design automation (EDA) tool providers in this space offer one product that may or may not be “best in class.” While “best in class” may suggest a company focused on its core competence, it’s a mistake to think that not providing an integrated DFY flow is an acceptable practice in the era of FinFET.

Anyone in charge of developing or managing a complete DFY flow should employ the principals of Six Sigma consistently through all three stages of the whole flow. The checklist should start with an integrated DFY methodology that neatly packages statistical device modeling and a powerful SPICE simulator with yield prediction, analysis and fixing capabilities up to and beyond 7 σ.  A designer should be able to tick off on the checklist the key points of accuracy, productivity improvement, scalability, high s yield, high σ optimization, and cost effectiveness.  That’s the recommendation for EDA teams and designers in the FinFET era. And, one that Jack Welch would endorse.


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