By Zvi Or-Bach, President & CEO of MonolithIC
While many have recently predicted the imminent demise of Moore’s Law, we need to recognize that this actually has happened at 28nm. From this point on we will still be able to double the amount of transistors in a single device but not at lower cost. And, for most applications, the cost will actually go up.
Let’s go back to 1965 and Moore’s paper in “Electronics, Volume 38, Number 8, April 19, 1965 The future of integrated electronics”. The following figure represented Dr. Moore’s observation with regard to three consecutive technology nodes. Quoting: …”the cost advantage continues to increase as the technology evolves toward the production of larger and larger circuit functions on a single semiconductor substrate. For simple circuits, the cost per component is nearly inversely proportional to the number of components, the result of the equivalent piece of semiconductor in the equivalent package containing more components. But as components are added, decreased yields more than compensate for the increased complexity, tending to raise the cost per component. Thus there is a minimum cost at any given time in the evolution of the technology.”
“The complexity for minimum component costs has in-creased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years”
The public information we now have indicates that:
a. The 28nm node is quite mature and we cannot expect that optimum integration vs. yield will double for it.
b. All that we know about the more advanced nodes (22/20nm, 16/14nm, …) indicates that the cost per transistor is not going to be reduced significantly vs. that of 28nm.
c. What we now know about embedded SRAM (“eSRAM”), I/O and other analog functions, indicates that most SoCs will end up at a higher cost as compared to 28nm.
Let’s recap using a few public charts to help tell the story of how we have reached that conclusion.
It starts with the escalating cost of lithography as illustrated in this 2013 chart from GlobalFoundries:
We should mention here that based on information released during last week’s SPIE Advanced Lithography (2014), it seems EUV is not going to be ready for the N+1 node (10nm). These costs, as well as other capital costs, increase, and thus drive up the wafer price as illustrated by the recent NVidia chart from Semicon Japan (Dec. 2013) below:
This escalating wafer cost eats away the higher transistor density gains, as articulated by NVidia and calculated by IBS’ Dr. Handel Jones and shown in the following table:
This is nicely illustrated by ASML slide from Semicon West (2013) below:
But this is just the smaller part of the problem. Advanced Integrated Circuits comprise far more than just logic gates. An SoC today contains a significant amount of embedded memories, I/Os and other support analog functions. Further, they include a large number of drivers and repeaters to reduce the RC delays that are escalating due to dimensional scaling. All of these scale very poorly.
The following chart was presented in an invited paper by Dinesh Maheshwari, CTO of Memory Products Division at Cypress Semiconductors, at ISSCC2014. It was also at the center of our recent blog “Embedded SRAM Scaling is Broken and with it Moore’s Law.”
This chart shows that eSRAM scaling is ~1.1X for decent performance as compared to ~4X for logic gates. The chart below (from Semico Research) shows that an average SoC has more than 65% of its die area allocated to eSRAM.
Consequently, the average SoC scaling to 16/14 nm could result in a significant cost increase, and hence 28nm is effectively the last node of Moore’s Law. To make things even worse, the remaining 35% of die area is not composed of only logic gates. More than 10% of the die area is allocated to I/O, pads and analog functions that either scale poorly or do not scale at all. And even in the pure logic domain scaling could not reach the potential 4X density improvements. The following chart was presented by Geoffrey Yeap, VP of Technology at Qualcomm, in his invited paper at IEDM 2013:
It illustrates the escalating interconnect RC delay with scaling – about 10X for two process nodes. This escalating RC delay eats away a significant part of the increase in gate density due to the exponential increase in buffer and driver counts and a similar increase in ‘white’ area kept for post layout buffer insertion, etc.
Final note: it seems clear that dimensional scaling has now reached negative returns, as is illustrated by the following GlobalFoundries chart:
The time is now to look for other alternatives, among which monolithic 3D seems a most compelling option. It allows us to leverage all our current silicon knowledge and infrastructure while continuing with Moore’s Law by scaling up at 28nm.
Well, that’s lukewarm information – the industry realized these facts over five years ago and _IS_ addressing it by 3D designs. Moore was well aware of basic semiconductor physics and quantum mechanics, so is the semiconductor industry. A MOSFET with a 2-unit cell thick oxide is a funny-acting tunnel diode, regardless of the design or the dielectric constant of the oxide.
Well, the industry is moving forward with 20 nm, 14 nm and people are talking about 10 nm and 7 nm. It was important to point out that dimension scaling could be done but it will no provide cost reduction as it did prior to 28 nm and with that we have reached the end of Moore’s Law. The real point is not semantic but rather fanatical. This end of cost reduction might cause real crises in the high-tech business.
True, people talk about 7 nm, only because it is not yet reached. You can scale down to maybe 10 / 8 nm but then Herr Hund and tovarishch Gamow will bar your way to anything lower. The tunneling effect (mentioned already I think…) IS a fundamental show stopper, and unlike costs will restrain even most desperate fanatics. At such scales, the transistor simply will not be controllable anymore and actually will not be a transistor as we know it. You could think of improving things with some kind of a majority voting / triplication logic (whatever it is called), but this will consume enormous amount of silicon budget….Therefore – go 3D (also mentioned :))! And true that the 3D integration technology is just a workaround, a temporary solution. But it will help, and a lot!
Now, if somebody thinks that you can substitute a silicon with another material – be my guest: we know everything about silicon; almost 70 years of experience, and you want to beat that? With what? Silicon is extremely universal – analog electronics, digital electronics, actuators…. Everything is based on silicon. It will be really, really, really hard (if not impossible) to find anything as flexible as silicon. Moreover, IC and silicon are synonyms 🙂 IMHO, if we will be lucky enough (in approx. 20-30 years) to develop a new platform for automation of our daily tasks and routines (games, communication, computation, making pictures, flying to Jupiter, etc.), it will be something very different from what we now call a conventional electronics (CMOS, 3D, finfet, gallium arsenide, imager, whatever). Maybe photonics?
Anyway, now we need to survive, and “More than Moore” technologies will help. And the 3D seems an appropriate solution.
Yes! More than Moore would help to walk or jump behind the red brick wall. Search and see my idea about a CMOS compatible thermal – electric logic circuit (TELC)!
First, the dimensional scaling to planer bulk 20nm, 14nm, 10nm and 7nm can’t be done today because of the short channel effects or unable to suppress transistor leakage currents. Therefore, the manufacturing costs are immaterial. That is why Intel has developed and manufactured FinFET at 20nm and 14nm today. Moore’s Law is not applicable to FinFET.
You write: “Moore’s Law is not applicable to FinFET”
Sorry to disappoint, but FinFET is simply part of a hierarchy that gives you extra process nodes compared with junction isolation. The first step in that hierarchy is FDSO, which should theoretically give slightly over one node, then FINFET, which shoud allow a further two-and-a-bit nodes, and finally nanowires, which might theoretically give a futher two nodes.
But it gets worse: so far as the FET is concerned it’s not only the field and bandgap properties that limit the scaling, but also the molecular structure; so, even though nanowires might otherwise take gate lengths to 3-nm, silicon itself limits the usable gate length to about 5-nm. Hence the search for better-organised 2D crystalline semiconductors, and preferebly with a native oxide that is stable and has a high high-dielectricelectrical properties that are more suitable for small geometries; it must also have a suitable bandgap and adequate mobility.
If we were to find an ideal material it miight theoretically take us as far as 1-nm, but then, of course there’s the small issue of interconnect…
I very respectfully disagree with your statement. Please do not take offense. Let me explain:
Sure – 3D IC, TSV and – eventually – silicon level 3D circuitry is moving forward and will help. But they are, collectively, just a stopgap.
Consider: there are three primary markets served by Silicon Valley: Consumer, Communications and Computing (the three C’s.) They’re all stagnant – Computing is continuing a long term trend of stagnation and now decline, Consumer is absolutely dead in the water because of the audio-visual limitations of human senses and a severe lack of disposable income for consumers, and communications is now re-entering stagnation because of the decline in pressure on the backhaul, cascading thru enterprise networking and storage, because of the rolling over of both smartphone and mobile computing markets, both of which are on the edge of saturation. Industrial is too fragmented to compensate for this, and automotive is not really a fresh avenue for growth, as it is saturating as well in terms of electronics content in addition to stagnating because of weakness in consumer disposable income.
In summary: silicon has run its course. We need something new – organic plastics, carbon nanotubes, quantum computing or another process technology. All of these have been prototyped and can make digital gates. In fact, Stanford built a functional 4004 with quantum computing technology in a lab. These technologies offer applications in sensors, textiles and other things which none of us have dreamed of yet – things that silicon cannot do effectively.
Disruptive invention for High Tech will HAVE to start at the chip level – the base level for everything in Electronics. From there, it will fan out chaotically or, if you will, fractally. It will also have revolutionary effects on how High Tech organizations work and organize themselves.
Without such base level Disruptive Inventions as an engine for change, Silicon Valley will go the way of the Pennsylvania, Michigan, Ohio and Indiana steel towns, the northern NJ fabric mills and all the rest of the old US industrial belt that began rusting out in the 70’s.
I predict an absolutely existential crisis for High Tech because of this. Consider: since the first real pioneering work in the 60’s and 70’s, 95% of everything Silicon Valley has done has been Evolutionary – modify, enhance, improve & innovate based on moving to the next node for more features and improving the 3 P’s (power, performance, price.) Management techniques, organizational hierarchies, strategies, operational norms and tactics have all reflected this for the last 30+ years. But to prevent Silicon Valley from turning into a Rust Belt, “innovation” will have to become a four letter word & give way to something truly, deeply scary for Silicon Valley companies – disruptive INVENTION.
Poet Technologies has patents and working products (PET) using Gallium Arsenide that can increase the processing power by a factor of 50 and reduce the power consumption to 10% of current chips. They can also have optical and digital circuits on one chip (POET). The chips can be produced on existing fab facilities without expensive upgrades.
Check out poet.technologies.com.
It’s poet-technologies.com
The answer to Moores law is POET, PTK.V … the game changer…..you have been told . whether you want to take advantage of this advice is up to you and it’s happening right now. They will be presenting at the GSF next week in Sinapore.
TSMC says 20nm will be a “long-lived node”, where the cost per transistor reaches a minimum value. However, IDMs like Intel claim Finfets on a wafer cost basis still allow cost per transistor scaling… is TSMC taking advantage of supply-demand dynamics to charge the world for Finfets? No foundry other than TSMC seems to have competitive Finfet offerings now…
TSMC’s 20nm process is planar… Everyone else’s will be as well (besides Intel of course) or it will be skipped directly to 14/16nm FinFet.
Where can find TSMC’s 20nm planar transistor performance data such as transistor transfer characteristics? Are they published somewhere such as IEDM or VLSI? Thanks
Yes, dimension scaling is surely going forward to 20 and 14 nm but the cost of end product will be higher and for most application quite a bit higher. Moore’s Law was about cost and the best integration cost would be at 28 nm. According 28 nm is the last node of Moore’s Law.
This may explain why companies are investing so high in small forms, like cell phones and tablets. Since the lower nodes won’t bring profits per size, they can at least cram more transistors at the same, small, area.
So, desktop stagnates, while cellphones will catch up with desktops, until both fuse into the same market, since both will have the same appeal for consumer, the difference being , primarily, the size of the screen and the keyboard.
… or maybe it’s possible there was a sea change in semiconductor technology evolution — away from a focused pursuit of area scaling, and more towards very low power. a finfet should offer dramatically reduced sub-threshold leakage, and that’s compelling with or without area scaling. that doesn’t mean that moore’s law died. it means that the marketplace is driving technologies along other vectors.
Yes, progress has not died and hopefully never will. But when we refer to Moore’s Law we are referring to specific observation he made in 1965 as one can see at the link and reference in the start of the blog. That one has stopped at 28 nm.
Zvi has been repeatedly saying that Moore’s law is talking about the cost benefit earned by miniaturizing devices, and the law has ended at 28nm even if we can still make the device size smaller than those of 28nm node rules. I agree with his idea since nothing can last forever. For example, people are trying to use air gap as an ultimate dielectric. But, what can you do with the heat accumulation in the device? Do you think the air gap, a nothing, can support the whole device structure? I mean everything is hitting the limits set by the nature!
Since cost is the important factor in the Moore’s Law discussion, we need to pay attention on the production yield, a biggest factor that can impact on the production cost. The exponential RC increase may be influenced by exponential increase of R with shrinking via/contact area, and any further complications, such as tiny impurities (contaminants) at the via bottom will make R even higher. A tiny dislocation of via that reduces the via contact area will have enormous impact to the production yield. These things were not seen in the larger generation devices, but we will see more of these in the future node generations. Please take a look at my patent US 8, 207,060 that stipulates how to make firm via/contact to secure lowest via resistance as possible, while removing impurities/contaminant from the via bottom, and still make via/contact engaged3 dimensionally with lower level conductor . BC Yang
Silicon Valley’s success is not linked to a specific set of technologies – it is a consequence of California’s employment laws. Non compete agreements are not legal in California. Employment doesn’t require you to give up all the past IP you developed by yourself. Poaching is not illegal, rather it is a bloodsport. That’s the secret sauce.
Silicon Valley all ready moved on from semiconductors. Software rules with IoT companies following close behind and Google and Apple in their own space. Some even predicting Intel moves it’s corporate HQ out of Santa Clara in 5 years.
This professional report makes me interested. The cost per gate is related to gate density, device size, the yield of each technology node as shown in the slide dones by Dr. Handel Jones. As the process control becoming challenge for advance process like 16/14nm FinFET, foundry will increase more design margin to increase yield rate at this moment. This might make 16/14nm FinFET not the cost effective one at this moment. Will it become better? No body knows, however, there are lots of RD working harder for that target.
If the small form chips become the bulk of profits for foundries, while the number of its transistors gets closer to the number of desktop standard (which should also shrink), they will converge in a very small area in small node. Curiously, it seems the number of transistors for the average desktop has became stagnated for a few years already.
So, wouldn’t defect tolerance increase with smaller dies?
Hi you all.
I was lucky enough to be at the Solid state conference in Philadelphia in 1966 and was in the audience where Dr More presented his paper defining Moore’s Law. A comment from the audience then was ” Nobody is going to tread those memory cores for less than 0.1Cents per bit. The law can not continue.” Dr Moore’s comment was: “Then we know one thing: Memories for computers will not be threaded ferrite cores in the future” Dr More was right.
We are not going to use the same technology to continue More’s Law. There is going to be something else. Believing that pushing present tecnology forever is a myopic point of view. I have no idea what that new technology is going to be, I just know from historical extrapolation that it is going to happen. More’s Law has ben declared stopped before but picked up agan then, and that will happen again.
HJW.
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MOORES LAW IS DEAD………..YOU JUST DONT KNOW IT YET
http://poet-technologies.com/wp-content/uploads/2014/02/POET-Technologies-Corporate-Overview.pdf
Back when Moore’s Law was written, we thought Pluto was a planet too. We know now that it is not. What if Moore’s Law was just a lucky guess that lasted this long?
Pluto as a planet or not is subjective: It’s never changed, we just changed our view of it. The thing is, Moore’s Law is nothing more than a keen observation. I think it foolish just to strive to make it hold true. For what are we doing it? You can’t even see 28nm with your naked eye.
Instead of despearately trying to cram as many transistors as possible inside a single chip, how about doing away with the circuit board? Laying things out on a flat plane is a horrible use of space – unless the flat plane is meant to be stacked multiple times…in many cases it’s not like in mainboards. I bet you could cram the innards of a high end gaming PC into something 5×5 inches square in three dimensions just by abandoning the flat circuit board.
1965s when Dr. Moore wrote his famous law were an era of the bulk silicon technology. Moore’s Law has not stopped at 28nm. In fact, Moore’s law has ended at 28nm bulk silicon technology node. The 28nm bulk CMOS is not scalable to 22nm bulk or beyond because of the short channel effects or unable to suppress transistor leakage current. That is why the planer 22nm bulk is not manufactured today by major semiconductor companies. This is not the manufacturing cost issues. That is why Intel has developed its first FinFET technology at 22nm node and is manufactured over two years and its 14nm FinFET is in volume manufactured today. Moore’s law is not applicable to FinFET because the FinFET is not planer bulk Si CMOS. FinFET has its own rule. The fin consists of a trapezoidal shaped vertical structure. The beauty of FinFET is its scalability in contrary to the planer 28nm bulk. In order to control the short channel effects or suppress transistor leakage current the fin-width(finW) at the bottom of the fin must be equal to or smaller than the channel length or gate length, Lg. That is, finW ≤ Lg This is the FinFET’s own rule. Therefore, FinFET is scalable to the end of the roadmap or to finW=Lg=5nm that is the end of the FinFET roadmap.
FinFET is great and it does solve the short channel effect BUT it does add to the fabrication cost. But the real issue is lithography costs. Below 28/22 nm we need double and quad litho which add significantly to the end device costs. As Moore’s Law is about the optimum cost, it accordingly stooped at 28 nm.
Well. We could really use an improvement in the way software works. That would give a significant boost to performance without a lot of change in silicon. “C” is very wasteful in terms of clock cycles. And that waste was buried by Moore’s Law.
I think an old and long bypassed language might be worth a look. Forth as embodied in the RTX2000 might be worth a look. The patents have run out. It was used in space missions where the MIPS per ma and per MHz were very important. A 32 bit or 64 bit version might be just what the market needs. With all the added peripherals common to today’s chips.
The dual stack architecture has a lot to recommend it.
ARM is too C centric.
Why do you think C is wasteful? As a computer programmer, I generally find that a program written in C uses much less memory and processes faster than any other high-level language. If you want to talk about a wasteful language, look at Ruby or PHP.
A very really brilliant presentation on the famous Moore’s law. Equally the blog posts are informative and inspirational.Thanks.
I think it is generally agreed that the exponential-cost phase of “Moore’s Law” is over. It has in fact persisted longer than Dr. Moore ever imagined. At the present the superficial appearance is that the exponential-cost phase continued until 28-nm, at which point cost reduction simply stopped. .I believe we are simply looking at a hiatus, and that there will eventually be further cost reduction using silicon at (around) 20-nm (with 3D extensions similar to those for 28-nm). Following this we can expect to see further advances as “exotic” materials and processes become economic, but at an ever slower rate, both in size and (probably) in the effect of optimum size on cost-per-function.
I see no technical reason why “children of silicon” should not eventually reduce the geometry for minimum cost-per-function to the 3-nm mark; however, I very much doubt this will ever happen – not because progress becomes impossible, but because other things take over.