CEA-Leti will present its latest results on CoolCube, the technique for stacking transistors sequentially in the same process flow for 3D-VLSI, at a Dec. 14 workshop in San Francisco, Calif. The workshop precedes IEDM 2014, Dec. 15-17.
“The technology is designed to allow a connection of the stacked active layers on a nanometric scale, with a very high density, due to their alignment by a standard lithographic process,” said Maud Vinet, Leti’s advanced CMOS laboratory manager, who will give the presentation. “This 3D concept should allow a gain of 50 percent in area and 30 percent in speed compared to the same technology generation in classic 2D – gains comparable to those expected in the next generation.”
Under development for eight years, CoolCube aims at cutting in half the thermal budget in manufacturing transistors, while maintaining their performance. This low-temperature fabrication allows vertical integration of a transistor without degrading the performance of the transistors beneath or the metal interconnects between the layers of the transistors.
During the continuation of the project over the next three years, Leti and its industrial partners will target development of a silicon component prototype of CoolCube.
In addition to the CoolCube overview, the workshop for invited guests will include summaries of:
- Leti’s innovative route with industry
- Emerging material for future market opportunities
- Leti’s vision towards 10nm and below
- Embedded NVM for the future
- Going further with disruptive designs and architectures
- Electronic medicine: a new market needing new medical methodologies
Leti also will present 17 papers, including four invited papers, at IEDM 2014.