Synopsys, Inc. today announced that TSMC has concluded 16 nanometer FinFET Plus (16FF+) v1.0 certification and reached the first milestone of 10 nanometer (nm) certification based on the most current DRM and SPICE model on a comprehensive list of Synopsys’ custom and digital design tools.  This certification enables mutual customers to deploy tools in Synopsys’ Galaxy Design Platform for 16nm production designs and 10nm early engagements. The certified platform delivers technologies including routing rules, physical verification runsets, signoff-accurate extraction technology files, statistical timing analysis that correlates with SPICE, and interoperable process design kits (iPDKs) for FinFET processes. TSMC and Synopsys have collaborated to enhance new tool features based on both 16nm and 10nm technology requirements in Synopsys’ IC Compiler II place and route solution with TSMC validation.  This includes full-flow color enablement, support for connected poly on gate oxide and diffusion edge (CPODE) technology, layer optimization, low Vdd timing closure and support for signal electro-migration. The two companies are also working together to complete IC Compiler II certification for 16nm by the end of April and 10nm in June 2015.

“The combination of tool certification and our longstanding collaboration with Synopsys is enabling customers’ 16FF+ production ramp-up and early engagements at 10-nanometer,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division.  “With a full suite of TSMC-certified digital, signoff, and custom implementation solutions from Synopsys, our mutual customers will achieve improved performance and lower power while attaining their time-to-market goals.”

“Our deep collaboration with TSMC on 16-nanometer and 10-nanometer FinFET processes allows our mutual customers to use silicon-proven FinFET tools to achieve predictable design closure with faster turnaround time,” said Bijan Kiani, vice president of product marketing in Synopsys’ Design Group. “With the latest certification for these two FinFET processes, designers can take advantage of this game-changing implementation technology for their next-generation chip designs.”