FOWLP and embedded packaging

BY PHIL GARROU, Contributing Editor

At the recent IMAPS conference, Yole’s Jerome Alzemer updated the audience on the Fan Out and Embedded die marketplace, based on his new report “Fan out and Embedded Die: Technology and Market Trends.”

Embedded packaging refers to many different concepts, IP, manufacturing infrastructures and related technologies. The two main categories of embedded packages are (1) those based on a molded wafer infra- structure such as FOWLP and (2) those based on a PWB/ PCB laminate panel infrastructure.

Fan-out WLP are “re-configured” by placing known good ICs active face down on a foil and by over-molding them. These wafers are then flipped and processed in the wafer fab with RDL/ball placing and diced.

For chip embedding in laminate, known good ICs are picked and placed on top of an organic layer of Printed circuit board and subsequent layers are laminated on top. Regular PCB manufacturing operations then take place on the panel containing the embedded ICs.


Unlike Fan In WLP, which has been commercialized since the late 1990’s, FOWLP is not constrained by die size, and thus can offer an unlimited number of interconnects for maximum connection density. One can also achieve finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and perfor- mance demands of the mobile market.

Commercialization of the Infineon e-WLB (embedded wafer level BGA) technology started in 2009 with single die packages for cell phone baseband chips. The Infineon technology was later licensed to OSATS Nanium, STATSChipPAC and ASE, thus creating a multi-sourced infrastructure.

A similar process called Redistributed Chip Packaging (RCP) was developed by Freescale during the same time period. It was subsequently licensed to NEPES but has not yet reached HVM. Other developing FOWLP technologies — including those of TSMC (called InFO), SPIL and J- Devices — are approaching commercialization but will initially lack the multi- sourcing available with eWLB.

The second generation of FOWLP are multichip packages including PoP and SiP configurations. These are generating increased interest in this packaging approach.

As of 2014 Yole estimates that the market is ~ $174MM. With the expected entry of several major players like TSMC, Yole envisions the market growing at a 30% CAGR to > $600MM by 2020.

Technical challenges such as warpage, die shift, chip- to-mold non planarity and topography remain significant limitations.


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