UPDATE:15 December 2015: Minor changes made to reflect correct ARM product nomenclature.
By Jeff Dorsch, Contributing Editor
Those 16-nanometer chips with FinFETs? Yesterday’s news. Taiwan Semiconductor Manufacturing wants you to know that they’re ready, willing, and able to help you design chips with 10-nanometer features.
The foundry presented Monday morning with its long-time partners, ARM Holdings and Synopsys, on its preparations for the 10nm process node.
“The N10 design ecosystem is ready for customer design starts,” said Willy Chen, TSMC’s deputy director of Design & Technology Platform. He noted that TSMC has been collaborating with Synopsys for 15 years, while ARM and TSMC together offer “the most advanced ARM processor cores in the most advanced TSMC technology.”
Rob Aitken of ARM added, “10-nanometer enablement needs an ecosystem,” which the three companies are prepared to provide. He said ARM has “some cool things under development to make chip design faster,” without elaborating.
Haroon Gahur, principal design engineer at ARM, began the program by describing attributes of the ARM Cortex-A72 processor design, which he said consumes 75% less energy than previous ARM cores.
Joe Walston of Synopsys said ARM used the DC Graphical, IC Compiler I, and IC Compiler II tools from Synopsys in developing Cortex-A72, with signoff performed by PrimeTime SI. ARM’s Gahur noted that IC Compiler II provided a significant runtime advantage over its predecessor, IC Compiler I, by completing its run in five hours, compared with about 24 hours for IC Compiler I.
The program also featured Denny Liu, deputy general manager of Design Technology at MediaTek, who spoke of his company’s involvement with Synopsys and TSMC. He detailed MediaTek’s Helio X20, introduced last month, which is a tri-cluster mobile processor with 10 cores. MediaTek also employed IC Compiler II in designing the chip.
For all the 10nm talk, TSMC is hitting its stride with the N16FF+ process. Synopsys and TSMC announced Monday that the IC Compiler II place-and-route tool is certified for the foundry’s 16nm FinFET Plus process.
“The 16FF+ design flow is here,” TSMC’s Chen said.
The program finished with a presentation by Henry Sheng, group director of research and development at Synopsys, who noted that 90 percent of FinFET tapeouts are done with Synopsys place-and-route tools. Touting his company’s “healthy working relationship with TSMC,” Sheng said that emerging process nodes present a number of challenges, specifically new yield and manufacturing rules, process scaling, and new FinFET devices. Of FinFETs, he said, “These things are electrically different.”
Separately, Synopsys announced Sunday that it has agreed to acquire Atrenta, without disclosing financial terms. The transaction is expected to close this summer.