By Jeff Dorsch, Contributing Editor
The era of three-dimensional chips is upon us.
At the Design Automation Conference last month in the Moscone Center, I saw a Hybrid Memory Cube in the booth of Open-Silicon in the South Hall. There before me was technology I had read about for years, without witnessing it in person.
The Hybrid Memory Cube, High-Bandwidth Memory technology, and logic parts such as Intel’s Xeon Phi “Knights Landing” microprocessor are leading examples of 3DIC technology. Meanwhile, other advances in packaging – chip-scale packages, copper pillar bumping, fan-in wafer-level packaging, flip-chip ball grid arrays, and wafer-level fan-out packages, among others – are gaining in adoption.
The Semiconductor Technology Symposium during SEMICON West 2015 will include two sessions devoted exclusively to advanced packaging on Tuesday, July 14. Packaging: The Very Big Picture is scheduled for 10 a.m., while Packaging: Digital Health and Semiconductor Technology will commence at 2 p.m.
SEMI reported packaging materials represented $20.4 billion in worldwide sales during 2014. That figure was essentially flat with 2013. SEMI noted that if bonding wire were excluded from the segment, sales would have been up more than 4 percent from the previous year. “The continuing transition to copper-based bonding wire from gold is negatively impacting overall packaging materials revenues,” SEMI stated.
McKinsey & Co. last year published a report on advanced packaging technologies that estimated the number of integrated circuits containing 2.5DIC and 3DIC technologies will increase from about 60 million units in 2012 to more than 500 million units in 2016.
“There still is a lot of uncertainty in the market about 2.5DIC and 3.0DIC technologies – for instance, when and how exactly to adopt these newer packaging configurations, who will dominated among the players, and the role China will play,” the authors of the report wrote.
Through-silicon vias figure in many 3DIC schemes, while silicon interposers are often regarded as a bridge to 3DIC technology and called 2.5DIC packaging. Ed Korczynski, senior technical editor of Solid State Technology magazine, wrote last month about recent developments in 3DIC technology.
The emergence of advanced packaging and 3DICs hasn’t escaped the attention of semiconductor equipment vendors, of course. KLA-Tencor in April introduced two systems – the CIRCL-AP for characterization and modeling of wafer-level packaging processes and the ICOS T830 for automated optical inspection of IC packages with 2D and 3D measurements. Both products are already installed in facilities around the world.
“Advanced packaging technologies offer device performance advantages, such as increased bandwidth and improved energy efficiency,” Brian Trafas, KLA-Tencor’s chief marketing officer, said in a statement. “The packaging production methods, however, are more complex – involving the implementation of typical front-end IC manufacturing processes, such as chemical mechanical planarization and high-aspect-ration etch, and unique processes, such as temporary bonding and wafer reconstitution.”
For 2014, Amkor Technology reported that “advanced products” accounted for $1.553 billion in revenue, or 49.6 percent of the company’s total revenue. That figure has steadily risen over the past three years.
Phil Garrou, a senior consultant for Yole Developpement, speaking last December at a symposium in Burlingame, Calif., took a hardline position on the subject of 2.5D technology. “It’s 2D or 3D,” he said, with nothing in between. “Interposers are packages,” he added.
Wherever you stand on 2D, 2.5D, or 3D, there will be much to discuss at SEMICON West this week.