At the 65th IEEE ECTC, several companies presented advances in thermos-compression bonding.
BY PHIL GARROU, Contributing Editor
Jie Fu of Qualcomm discussed “Thermal Compression Bonding for Fine Pitch Solder Interconnects.” Mass reflow-based interconnects, using either solder bump or Cu-column on bond on lead are the typical low-cost flip chip assembly approaches used by industry. These interconnects face challenges related to shorting and non-wets at sub 100μm pitches.
Transitioning below 100μm pitch requires a new approach, such as thermos- compression flip chip (TCFC). While TCFC provides higher accuracy bonding and allows for use of smaller solder cap which enables tighter FC pitch, it also presents new challenges. The major challenges for TCFC bonding include lower throughput and control of non-conductive paste (NCP) voids.
Overall, bond head ramp rate, temperature uniformity, peak temperature and dwell time must be fine-tuned in tandem to compensate for manufacturing tolerances and to get the desired end of line solder joint structure. In addition, controlling the temp exposure for the NCP material before NCP cure is critical to enable a robust TCFC solder joint. Too much thermal exposure and the NCP begins to cure prior to solder melting, which can leading to NCP entrapment and unreliable TCFC solder joints. Laminate surface finish is also an important variable.
In a similar study Cho and co-workers at GlobalFoundries presented “Chip Package Interaction Analysis for 20-nm Technology with Thermo-Compression Bonding with Non-Conductive Paste.” Strong market demand for finer pitch interconnects to enable higher I/O counts in a smaller form factor is driving another transition from conventional MR bonding process to thermo-compression bonding using non-conductive paste (TC-NCP). FEA simulation results for TC-NCP vs mass reflow show that TCNCP has significantly reduced thermomechanical stress at the ULK level and the bump level.
Horst Clauberg of K&S discussed “High Productivity Thermo- compression Flip Chip Bonding.” There is tremendous effort by IDMs, OSATs, materials suppliers and equipment suppliers to bring thermos-compression bonding to commercial reality. The most significant technical challenges have for the most part been solved and limited commercial production is taking place. However, relatively low throughput and high equipment cost create adoption resistance, especially in the all-important consumer market.
Thermocompression bonding can be segmented into two different processes. The first process differentiation is whether the underfill is pre-applied before the semiconductor chip is mounted or not. Pre-applied underfill comes either as a film applied to the die or as a paste applied to the substrate. In both cases the underfill must not only create a void-free bond, but also provide flux to remove oxide on the solder caps. The alternative process is thermocompression – capillary underfill (TC-CUF) where the die is underfilled in the same way as standard flip chip, except that the underfill process is much more challenging because of the more narrow bondline of a typical thermocompression bonded device. In TC-CUF, flux can be applied either by dipping the die into flux before bonding, or applying flux to the substrate.
Doug Hiner in a joint presentation between Qualcomm and Amkor presented “Multi-Die Chip on Wafer Thermo-Compression Bonding Using Non-Conductive Film.” Non-conductive films have been in development as a replacement to the liquid preap- plied underfill materials used in fine pitch copper pillar assembly.
Several assembly methods are available for chip on wafer assembly including: (1) traditional chip attach with mass reflow (MR) and capillary underfill (CUF), (2) thermo-compression bonding (TCB) of copper pillar interconnects using noncon- ductive paste (NCP) underfill (TCB+NCP), and thermocom- pression bonding of copper pillar with non-conductive film (NCF) underfill (TCB+NCF).
The TCB+NCP process carries concerns with the underfill time on stage which prevents the dispensing of the NCP material across the wafer prior to the chip bonding process. This constraint effects process costs significantly. The TCB+NCF process to date have not met the cost/benefit needs of the industry. NCF assembly provides significant improve- ments in the design rules associated with die to package edge, die to die, and fillet size. The NCF process also resolves the time on stage concerns associated with the NCP process by laminating the NCF material to the bonded die instead of to the interposer or receiving wafer surface.