BY PHIL GARROU, Contributing Editor
One of the plenary presentations at this year’s IEEE 3DIC conference was “Advanced 2.5D/3D Hetero-Integration Technologies at GINTI, Tohoku University” by KW Lee, Koyanagi-san and co-workers, detailing the activities at the University and the prototyping spin-out.
The Global Integration Initiative (GINTI) is 8/12-inch R&D foundry fab for the R&D of 2.5D/3D integration technologies and applications. GINTI provides a process development infrastructure in a manufacturing-like fab environment and “low cost,” prototyping of proof of concepts using commercial/customized 2D chip/wafer, and a base-line process.
State-of-the technologies include design, layout and mask making to wafer thinning, forming of TSV on chip/ wafer (front side/backside TSV), redistribution routing, both side micro-bump formation, chip/wafer stacking, failure analysis, and reliability testing.
GINTI can provide 3D prototype LSI stacking using commercial 2D chips by die-level 3D hetero-integration, backside TSV formation and various stacking (C2C C2W, W2W, and self-assembly) technologies.
GINTI mainly focuses on a via-last backside TSV approach, because they feel it is a better solution for heterogeneously integrating different function, size, and material devices, with better flexibility for commercial chip/ wafers.
Figure 1
Figure 2
Their process flow for via-last backside TSV fabrication is shown in FIGURE 1. The incoming LSI device wafer with metal bumps is temporarily bonded onto a support wafer. Then the Si substrate is thinned to target thickness from the backside by grinding and CMP. After via patterning on the ground surface, the deep Si trench is formed from the backside by RIE processing until the first level metallization layer (M1) is exposed. Oxide liner is deposited into via holes and the bottom oxide liner in via hole is selectively etched by dry etching to re-expose the M1 layer. Next, the deep trench is filled with Cu by electroplating after dep of barrier and seed metal layers. Re-distribution layer (RDL) is then formed on the backside and metal bumps are formed on the RDL by electroplating.
Finally, the support wafer is de-bonded from the thinned LSI wafer.
To create new 3D hetero-integrated systems they have developed die-level 3D integration technology. Commer- cially available 2D chips with different functions and sizes such as those of sensor, logic, and memories which were fabricated by different technologies, are processed to form TSVs and metal micro-bumps and integrated to form a 3D stacked chip in die level. FIGURE 2 shows a 3D stacked image sensor chip comprising three layers of CIS, CDS, and ADC chips for high speed image sensor system.