Yearly Archives: 2015

ON Semiconductor Corporation and Fairchild Semiconductor International Inc. today announced plans for ON Semiconductor to acquire Fairchild for $20.00 per share in an all cash transaction valued at approximately $2.4 billion. The acquisition creates a leader in the power semiconductor market with combined revenue of approximately $5 billion, diversified across multiple markets with a strategic focus on automotive, industrial and smartphone end markets.

“The combination of ON Semiconductor and Fairchild creates a power semiconductor leader with strong capabilities in a rapidly consolidating semiconductor industry. Our plan is to bring together two companies with complementary product lines to offer customers the full spectrum of high, medium and low voltage products,” said Keith Jackson, president and chief executive officer of ON Semiconductor. “The immediate EPS accretion and potential to significantly augment ON Semiconductor’s free cash flow, make the Fairchild acquisition an excellent opportunity for ON Semiconductor stockholders.”

“As part of ON Semiconductor, Fairchild will continue to pioneer technology and design innovation in efficient energy consumption to help our customers achieve success and drive value for our partners and employees around the world,” stated Mark Thompson, chairman and chief executive officer of Fairchild. “We look forward to working closely with the ON Semiconductor team to ensure a smooth transition.”

Following consummation, the transaction is expected to be immediately accretive to ON Semiconductor’s non-GAAP earnings per share and free cash flow, excluding any non-recurring acquisition related charges, the fair value step-up inventory amortization, and amortization of acquired intangibles. ON Semiconductor anticipates achieving annual cost savings of $150 million within 18 months after closing the transaction.

The transaction is not subject to a financing condition. ON Semiconductor intends to fund the transaction with cash from the combined companies balance sheet and $2.4 billion of new debt. The debt financing commitment also includes provisions for a $300 million revolving credit facility which will be undrawn at close. ON Semiconductor remains committed to its share repurchase program, and the agreed upon financing provides flexibility to continue share repurchases going forward.

Follow other industry acquisition news here.

CEA-Leti and its partners in the European FP7 project PLAT4M today announced they have built three silicon photonics platforms. The four-year project, which launched in 2013, aims at building a European-based supply chain in silicon photonics and speeding industrialization of the technology. PLAT4M, which is funded by a European Commission grant of 10.2 million euros, includes 15 leading European R&D institutes and CMOS companies, key industrial and research organizations in design and packaging, as well as end users in different application fields, to build the complete supply chain.

Midway through the project, the consortium has developed advanced technologies and tools by building a coherent design flow, demonstrating manufacturability of elementary devices and process integration, and developing a packaging toolkit. The supply chain is based on technology platforms of Leti, imec and STMicroelectronics, supported by a unified design environment. The high level of maturity of the technology offered by these platforms makes them readily accessible to a broad circle of users in a fabless model.

Imec’s silicon photonics platform, based on 200mm substrates, has matured thanks to the PLAT4M project. The platform is based on SOI substrates with 220nm crystalline silicon on a 2,000nm buried oxide. During this project the existing fabrication processes and integration flow have been fine tuned to have stable and repeatable performance for all photonics building blocks (couplers, waveguides, phase shifters, photodetectors). This feeds the process design kit’s robust performance specifications and guarantees quality and first-time-right designs for the platform’s fabless users for high data-rate telecom and non-telecom applications. PLAT4M partners Thales, Polytec and TNO already are using the technology.

Beyond the 200mm platform, imec has pushed the limits of silicon photonics, exploiting advanced optical lithography with its 193nm immersion lithography scanner. It also has demonstrated very low propagation loss (~0.6dB/cm) for fully etched waveguides with excellent within-wafer linewidth control (standard deviation

Using the imec platform, Thales demonstrated a coherent combination of laser beams (CBC). Ultimately, this application aims at producing high-power, high-energy laser sources for sensing, industry or fundamental physics. The CBC rationale is to push the limits of single laser emitters (typically fiber amplifiers) by using a large number of amplifiers and coherently adding the output beams. The coherent addition requires locking the phase of all the amplifying channels. With the number of channels, potentially very large (from tens to thousands), an integrated technology is a major concern in terms of possible industrial products. The first generation CBC demonstrator of PLAT4M, which was packaged by Tyndall UCC, included a one-to-16 channel splitter tree, plus 16 independent thermal phase modulators. The CBC experiment showed the successful coherent addition of 16 laser beams at 1.55µm.

cea-leti supply chain

Leti has developed a new photonic platform based on 200mm SOI wafers. This process offers multilevel silicon patterning that allows the design of various passive and active devices (e.g. modulator and photodiode) with thermal tuning capability. Two AlCu levels are available for routing. A process design kit (PDK) is available for circuit design and an MPW service will be proposed in 2016. State-of-the-art performances have been demonstrated: insertion losses are below 2dB/cm for monomode waveguide and below 0.2dB/cm for multimode devices. Germanium photodiode responsivity is > 0.75A/W for a bandwidth >30GHz. Mach-Zehnder modulator VpLp is in the 2V.cm range for 2V operation with an E/O bandwidth > 25GHz. Moreover, Leti and III-V Lab have developed integrated hybrid III-V lasers and electro-absorption modulators (EAM) on silicon using a wafer-bonding technique. The hybrid lasers operate in the single-mode regime and the EAMs exhibit an extinction ratio higher than 20 dB with a drive voltage lower than 2V. Clear eye diagram has been achieved at a bit-rate of 25 Gb/s, confirming strong potential for telecom applications.

During the project, ST developed an additional silicon-photonic platform in 300mm technology to be used as an R&D tool for proof-of-concept purposes. The technology, called DAPHNE (Datacom Advanced PHotonic Nanoscale Environment), is designed for evaluating new devices and subsystems for demonstration. DAPHNE is a flexible platform that perfectly fits R&D needs. While developing it, ST demonstrated wavelength-division-multiplexing solutions using arrayed waveguide gratings, echelle gratings, cascaded Mach-Zehnder interferometers and side-coupled integrated spaced sequence of resonators. Some of the configurations are designed for the 100GBase-LR4 standard, and the experimental characterization results show insertion losses below 0.5dB and channel cross-talks above 25dB for a band flatness of 2nm. Furthermore, proper operation of receiver-and-transmitter blocks to be interfaced to optical devices above them has been demonstrated at 28Gbps, making use of 65nm-node technologies.

The PLAT4M WP2 work has led to a qualitative leap of the design flow for silicon photonics, allowing the photonics community to design more complex and more robust circuits. The electronics OpenAccess standard for data sharing between design-automation tools includes an extension for silicon photonics in a beta phase today. Simulation capabilities were leveraged thanks to an extensive characterization effort from the three partner fabs and thanks to the statistical data gathered for variability prediction. Paris-Sud University has studied theoretically the behavior of different phase shifters and photodetectors for a time-efficient and precise modeling. Mentor Graphics and PhoeniX Software partners have improved phase-aware routing and tool interoperability. Verification and manufacturability have reached industry-requirement standards thanks to the development of new techniques based upon the Mentor Graphics Calibre platform that delivers layout-versus-schematic comparison (Calibre nmLVS), photonic rule checks (PRC) and curvilinear-aware design-rule checks (Calibre nmDRC). Mask preparation is also improving with better pattern-density control and mask correction.

Stacking instead of mixing


November 18, 2015

The overheating of computer chips is a major obstacle to the development of faster and more efficient computers and mobile phones. One promising remedy for this problem could be a class of materials first discovered just a few years ago: topological insulators, which conduct electricity with less resistance and heat generation than conventional materials. Research on these materials is still in its early stages. A team from Jülich and Aachen has now found a way to control the desired conducting properties of this type of material more precisely and reliably than ever before. The results have been published in the current edition of the journal Nature Communications (DOI: 10.1038/ncomms9816).

So-called “topological” materials have different physical properties on their surface than they do on their inside. Topological insulators are in effect insulators on the inside, but on their surfaces and edges they conduct electric currents almost as if they were running along railway tracks: faster, with less resistance and less heat production than with conventional materials. Additionally, the tracks act as a one-way street for electrons. The inherent angular momentum of the electrons – known as “spin” – determines in which direction the electrons can flow. This property is also useful for information processing and can pave the way for the development of new spintronic components.

Researchers from the Peter Grünberg Institute and RWTH Aachen University have now shown how the conductivity and the energy requirements of these materials can be optimized. Put in highly simplified terms, their recipe for success is: stacking instead of mixing. Prof. Detlev Grützmacher of the Peter Grünberg Institute first came up with the crucially important idea: “Instead of alloying two different types of semi-conductors as usual, in order to obtain a topological insulator, we stacked both semiconductors on top of each other, atomic layer by atomic layer, placing this in turn on a silicon backing layer with the help of molecular beam epitaxy.” Molecular beam epitaxy is an extremely precise method of producing thin crystalline layers, and is increasingly used not only in research but also in the industrial production of semiconductors.

By varying the thickness of the layers of semiconductor sandwiches made from silicon (grey area), bismuth-telluride, an n-type semiconductor (red area) and antimony telluride, a p-type semiconductor (green), topological insulators can be customized according to needs, as shown by the experiments conducted by researchers from Jülich and Aachen. The quality of the layers they produced using molecular beam epitaxy were verified by ultra high-resolution scanning electron microscopy. The atomic layers are clearly visible on the left side of the cube's edge. Credit: Forschungszentrum Jülich

By varying the thickness of the layers of semiconductor sandwiches made from silicon (grey area), bismuth-telluride, an n-type semiconductor (red area) and antimony telluride, a p-type semiconductor (green), topological insulators can be customized according to needs, as shown by the experiments conducted by researchers from Jülich and Aachen. The quality of the layers they produced using molecular beam epitaxy were verified by ultra high-resolution scanning electron microscopy. The atomic layers are clearly visible on the left side of the cube’s edge. Credit: Forschungszentrum Jülich

In this way, the scientists were able to control the atomic construction with great precision, which they documented with the use of ultra high-resolution electron microscopy. “Achieving the perfect atomic composition of the topological insulators is vital for the electronic properties, and thus for energy efficiency, but the alloying process is difficult to monitor,” explained Dr. Lukasz Plucinski from the Peter Grünberg Institute.

The researchers were able to discover exactly which layer thickness goes hand in hand with optimal conduction properties using the technology of angle-resolved photoemission spectroscopy. Here, samples are bombarded with photons to trigger the release of electrons from the material. Their energy and exit angle is measured, providing information about the energy and distribution of the electrons at the sample’s surface.

In principle, topological insulators can also be controlled with the help of external electric fields in semiconductor alloys and other materials. Using the sandwich method that the scientists have developed together within the framework of the Jülich Aachen Research Alliance “Future Information Technology” (JARA FIT), such complex technological procedures are no longer necessary and in addition, the silicon substrate material makes it simpler to integrate in applications at later stages.

Scientists at the Virtual Institute for Topological Insulators (VITI), coordinated by the Peter Grünberg Institute in Jülich, are continuing to conduct basic research on further possible uses for the new materials. This could, for example, make it possible to prove the existence of novel, only theoretically predicted quantum phenomena, such as so called topological exciton condensates, formed by electron-hole pairs at the surfaces.

TowerJazz, a global specialty foundry, announced today it has signed an agreement with Maxim Integrated Products, Inc. to purchase Maxim’s 8-inch fabrication facility in San Antonio, Texas, United States.

The proposed purchase will expand TowerJazz’s current worldwide manufacturing capacity, cost-effectively increasing production by approximately 28,000 wafers per month. The availability of additional capacity is expected to be needed to serve TowerJazz’s current and forecasted robust customer demand. TowerJazz and Maxim expect to close the transaction in January 2016, subject to customary closing conditions.

As part of the transaction, the companies have also signed a long-term supply agreement for TowerJazz to manufacture products for Maxim in the San Antonio facility. The transaction is to be paid with TSEM ordinary shares with a total value of approximately 40 million US dollars.

All of the site’s nearly 500 employees will be retained. The headcount consists of production operators, highly experienced production support personnel and process and integration engineers, the majority of which possess graduate degrees.

The facility can support the advanced analog platforms using geometries down to 130nm and can be used also to manufacture third party products using TowerJazz specialty process technologies. TowerJazz plans to quickly qualify its core specialty technologies, including its advanced Radio-Frequency Silicon-on-Insulator (RF-SOI) offering, to serve the substantial growth in demand from its customers.

“We are very excited about this fab purchase. It will provide a quick solution for our significantly growing customer demand, while gaining additional high quality manufacturing capabilities and global flexibility with the incremental capacity,” said Dr. Itzhak Edrei, TowerJazz’s President. “The multi-year supply agreement with Maxim and the new available capacity will enable continuous growth with increased manufacturing scale to support our position as the worldwide leading specialty analog foundry.”

“We know Maxim very well, having been their supplier for a family of high-end SiGe based products for many years. During this period we have developed an appreciation for Maxim’s technical capabilities, business vision and corporate culture. Above all, we built a strong relationship of mutual trust and respect,” said Russell Ellwanger, TowerJazz’s Chief Executive Officer. “The San Antonio factory enables us to further strengthen our relationship with Maxim, in a true win-win business model enabling TowerJazz incremental capacity supported by a proven high performing technical and operational team.”

“We needed a trusted partner to manage our proprietary process technology who also shared our commitment to the employees in San Antonio. Tower Jazz has a proven track record with Maxim and similar beliefs about employees, so this is a natural fit. I look forward to our continued partnership over the coming years,” said Vivek Jain, Senior Vice President of Maxim Integrated’s Technology and Manufacturing Group. “With this arrangement, we will continue to support our customers for years to come, improve utilization in our Oregon fab, and advance our manufacturing flexibility.”

TowerJazz manufactures integrated circuits, offering a broad range of customizable process technologies including: SiGe, BiCMOS, mixed-signal/CMOS, RF CMOS, CMOS image sensor, integrated power management (BCD and 700V), and MEMS. TowerJazz also provides a world-class design enablement platform for a quick and accurate design cycle as well as Transfer Optimization and development Process Services (TOPS) to IDMs and fabless companies that need to expand capacity.

To provide multi-fab sourcing and extended capacity for its customers, TowerJazz operates two manufacturing facilities in Israel (150mm and 200mm), one in the U.S. (200mm) and three additional facilities in Japan (two 200mm and one 300mm) through TowerJazz Panasonic Semiconductor Co. (TPSCo), established with Panasonic Corporation of which TowerJazz has the majority holding. Through TPSCo, TowerJazz provides leading edge 45nm CMOS, 65nm RF CMOS and 65nm 1.12um pixel technologies, including the most advanced image sensor technologies.

Novel, chemically precipitated sub-micron silver materials from Ames Goldsmith Corporation will be introduced Nov. 18 at Printed Electronics 2015 in Hall C, Booth R20. This proprietary technology platform enables fine-line flexible circuits, allowing product designers more versatility and greater freedom to incorporate electronics into broader applications than previously possible to expand commercialization of advanced technologies such as flexible displays and printed, flexible circuits.

Average particle sizes range between 200–400 nanometers. Ames controls particle synthesis of the sub-micron silver material via chemical precipitation, which allows its surface chemistry to be tailored to match customers’ needs to optimize specific ink systems. This produces conductive inks, pastes, and adhesives with controlled rheology and viscosity for finer and sharper line definition.

Ames Goldsmith controls synthesis of its proprietary sub-micron Ag material via chemical precipitation to produce well-defined, uniform spherical particles to customers’ targeted size and morphology with very tight distribution. Average particle sizes range between 200–400nm, with specific surface area > 1.5 m2/g and tapped density > 3.5g/cm3. The spherical sub-micron material are compatible with many solvents.

Ames Goldsmith controls synthesis of its proprietary sub-micron Ag material via chemical precipitation to produce well-defined, uniform spherical particles to customers’ targeted size and morphology with very tight distribution. Average particle sizes range between 200–400nm, with specific surface area > 1.5 m2/g and tapped density > 3.5g/cm3. The spherical sub-micron material are compatible with many solvents.

The new sub-micron silver materials offer cost-efficient performance and are commercially available in high-volume quantities.

Ames Goldsmith is a supplier of silver-based, gold, platinum, palladium and copper products to the global printed electronics, EO catalyst refining, photographic, and health care industries. Ames Goldsmith and Ames Advanced Materials Corporation develop next generation metal products for the electronics industry. The company’s Catalyst Refiners, Inc. subsidiary provides a variety of silver oxide and refining services on a global basis.

Intel and ASM look to TCB


November 17, 2015

BY PHIL GARROU, Contributing Editor

In the September column, we looked at some of the key thermo-compression bonding (TCB) papers at ECTC. Is there any question that TCB is real and will be the next big bonding technology? The focus this month is more on this very important new assembly process from Intel and ASM.

Intel introduced TCB into high volume manufacturing in 2014. As substrate and die become thinner and solder bump sizes and pitches get smaller, the thin organic substrate tends to warp at room temp and as the temp is increased during the reflow process. The thin die can also demonstrate temperature dependent warpage, which can come into play during the reflow process. The extent of warpage of the substrate and die at high temperatures can overcome the natural solder surface tension force leading to die misalignment with respect to the substrate, resulting in tilt, non-contact opens (NCO) and in some cases solder ball bridging (SBB). FIGURE 1 shows these various defects.

Phil Garrou

In the Intel TCB process, the substrate with pre-applied flux is held flat on the hot pedestal under vacuum. The die is picked up by the bond head, held securely and flat on the bond head with vacuum. After the die is aligned with the substrate, the bond head comes down and stops when the die touches the substrate. A constant force is then applied while the die is heated up quickly beyond the solidus temperature. As soon as the solder joint melts, the die is moved further down (solder chase) to ensure all solder joints are in contact. The die is held in position allowing the solder to reflow completely, and to wet the bump pads and copper pillars. While the solder is still in the molten state, the bond head retracts upwards controlling the solder joint height. The bond head then releases the vacuum holding the die and moves away as the solder joints have solidified. The major process parameters, i.e temperature, force and displacement are continuously monitored during the TCB bonding process.

Large differences in the CTE between the organic substrate and die results in different magnitude of expansions when heated which can lead to serious bump offset at corners. To minimize the thermal expansion mismatch, the substrate is processed at a lower temperature (e.g. 140°C) while the die and solder is rapidly heated up for reflow and cooled down for solidification using a pulse heater with heating ramp rate exceeding 100°C/s and cooling ramp rate exceeding 50°C/s. This reduces the heat transfer to the substrate. The bulk of the substrate can remain at low temperature and does not expand extensively.

In another ASM paper on TCB they examined what they call liquid phase contact (LPC) TCB. The goal is to increase the throughput of the TCB process. Process flow is shown below. Flux is printed or sprayed on the substrate. Then the bonding head picks up a die from the carrier at an elevated temperature, but below the solder melting point. Then the bonding head is heated up to a temperature higher than the solder melting point and the chip is aligned with the substrate. The chip is then contacted and wetted on the substrate at a predeter- mined bonding height. After a predetermined bonding time, the bonding head can move is cooled down to a temperature below the melting point of solder. They claim this results in attachment of 1200 units/hr vs 600 for the standard TCB flux process.

BY PETER CONNOCK, Chairman of memsstar

The dramatic shift from the trend for increasingly advanced technology to a vast array and volume of application-based devices presents Europe with a huge opportunity. Europe is a world leader in several major market segments – think automotive and healthcare as two examples – and many more are developing and growing at a rapid rate. Europe has the technology and manufacturing skills to satisfy these new markets but they must be addressed cost effectively – and that’s where the use of secondary equipment and related services comes in.

While Moore’s Law continues to drive the production of advanced devices, the broadening of the “More than Moore” market is poised to explode. All indicators are pointing to a major expansion in applications to support a massive increase in data interchange through sensors and related devices. The devices used to support these applications will range from simple sensors to complex packages but most can, and will, be built by “lower” technology level manufacturing equipment.

This equipment will, in many cases, be required to be “remanufactured” and “repurposed” but will allow semiconductor suppliers to extend the use of their depreciated equipment and/or bring in additional equipment, matched to their process needs, at reduced cost. In many cases this older equipment will need to be supported by advanced manufacturing control techniques and new test and packaging capabilities.

SEMI market research shows that investment in “legacy” fabs is important in manufacturing semiconductor products, including the emerging Internet of Things (IoT) class of devices and sensors, and remains a sizeable portion of the industries manufacturing base:

  • 150mm and 200mm fab capacity represent approximately 40 percent of the total installed fab capacity
  • 200mm fab capacity is on the rise, led by foundries that are increasing 200mm capacity by about 7 percent through to 2016 compared to 2012 levels
  • New applications related to mobility, sensing, and IoT are expected to provide opportunities for manufacturers with 200mm fabs

Out of the total US$ 27 billion spent in 2013 on fab equipment and US$ 31 billion spent on fab equipment in 2014, secondary fab equipment represents approximately 5 percent of the total, or US$ 1.5 billion, annually, according to SEMI’s 2015 secondary fab equipment market report. For 2014, 200mm fab investments by leading foundries and IDMs resulted in a 45 percent increase in spending for secondary 200mm equipment.

Secondary equipment will form at least part of the strategy of almost anyone manufacturing or developing semiconductors in Europe. In many cases, it is an essential capability for competitive production. As the secondary equipment industry increases its strategic importance to semiconductor manufac- turers and researchers it is critical that the corresponding supply chain ensures a supply of quality equipment, support and services to meet rapidly developing consumer needs.

Common challenges across the supply chain include:

  • How to generate cooperation across Europe between secondary equipment users and suppliers and what sort of cooperation is needed?
  • How to ensure the availability of sufficient engineering resource to support the European secondary installed base?
  • Are there shortages of donor systems or critical compo- nents that are restricting the use of secondary equipment and, if so, how might this be resolved

Europe’s secondary industry will be in the spotlight during two sessions at SEMICON Europa 2015:

  • Secondary Equipment Session – Enabling the Internet of “Everything”?
  • SEA Europe ‘Round Table’ Meeting

The sessions are organised by the SEMI SEA Europe Group and are open to everyone associated with the secondary industry, be they device manufacturer or supplier, interested in the development of a vibrant industry providing critical support to cost effective manufacturing in Europe.

Due to their exciting properties, 2D crystals like graphene and transition metal dichalcogenides promise to become the material of the future.

BY STEFAN DE GENDT, CEDRIC HUYGHEBAERT, IULIANA RADU and AARON THEAN, imec, Leuven, Belgium.

As we enter into the era of functional scaling where the cross-roads of More-Moore and More-Than-Moore meet, the search for new devices and their enabling material comes to the forefront of technology research. 2D crystals provide very interesting form-factors with respect to traditional 3D crystals (bulk, Si, and III-V semiconductors). In this elegant 2D form, electronic structure, mechanical flexibility, defect formation, and electronic and optical sensitivity become dramatically different. Aaron Thean: “As researchers at imec explore the physics and applications of such material, it is now becoming important to find a wafer-scale path towards technology implementation and integration of these novel materials.” Working closely with research teams across universities and industry partners, the first important step for imec is to enable the flake-to-wafer transition, while concurrently exploring the material, and device-to-circuit applications. The work will build new infrastructure (e.g. epitaxy, metrology, patterning, and electrical characterizations, etc.) around it.

Graphene and beyond

A 2D material is basically formed as a regular network in two dimensions, not extending in the third dimension. It is a monolayer-type of material, where monolayer should be understood as ‘up to a few monolayers’. The most known 2D material is graphene, a crystalline monolayer of carbon atoms arranged in a hexagonal honeycomb lattice structure. Recently, the exploration of 2D materials has moved beyond graphene. Stefan De Gendt: “2D materials cover all classes of materials, from semiconductors to insulators to metals. Graphene is a prominent example of a (semi-)metal. Transition metal dichalcogenides (or MX2 with M a transition metal and X a chalcogen such as sulfur or selenium) and hexagonal boron nitrides are well known examples of 2D semiconductors and insulators, respectively.”

2D materials: the new silicon?

Many of these materials exhibit remarkable properties that can be exploited in a range of applications. Cedric Huyghebaert: “Graphene, for example, is a fantastic electronic and thermal conductor. It has a record thermal conductivity, a very high intrinsic mobility, a high current density and long mean free path of electrons. Its surface is chemically inert, it has a low surface energy and no out-of-plane dangling bonds. MX2 have versatile properties that complement those of graphene. For example, they have a wide range of bandgaps as opposed to graphene, where the bandgap is absent. In case of graphene, we have to open the bandgap by using e.g. graphene nanoribbons or bilayer graphene.”

2D materials represent interesting alternatives to Si-based transistors. Iuliana Radu: “When scaling the gate length of a traditional Si-based MOSFET, overlapping junctions lead to short channel effects which degrade transistor performance. By introducing 2D materials in the channel of the MOSFET, they could show superior immunity to short channel effects. 2D materials could therefore extend traditional CMOS scaling beyond its current limits. They are also being considered for tunnel-FET (or TFET) applications, where carrier transport happens through band-to-band tunneling. In principle, 2D materials have no dangling bonds at the interfaces. These dangling bonds are one of the main limiters for TFETs with conventional semiconductors and limit strongly their performance.”

2D materials hold promises in other domains as well. Cedric Huyghebaert: “Many applications become possible by integrating these exciting materials in a monolithic way on top of CMOS. In (bio)sensing applications, for example, owing to their ability to adsorb and desorb various atoms and molecules. Or in optoelectronics, where the combination of a low absorption and high carrier mobility turns out very beneficial. Researchers are also assessing the potential of 2D materials to replace copper wires in back-end-of-line interconnects. Finally, 2D materials have been considered for appli- cation in domains such as plasmonics, photovoltaics and energy storage, and as transparent electrodes. In the latter applications, the requirements for graphene are less stringent than in aggressive transistor scaling. Therefore, the first graphene-based commercial products will most likely be introduced in one of these domains.”

The hamburger experience

Stefan De Gendt: “Ultimately, they potentially enable the engineering of new nano-based stacks: sandwich structures that are composed of various 2D materials, including semiconductors, metals and insulators. This view was nicely described at the 2013 IEDM conference, by the plenary speaker Andrea Ferrari. If you take a hamburger, it’s a layered combination of various ingredients, each with a specific flavor. But it’s the combination of all these layers that makes the hamburger a unique experience. The same will potentially hold for stacks made up of different 2D materials.”

From flakes to large-area synthesis

Applications based on graphene and other 2D materials have become very popular. Many of the above concepts have been successfully demonstrated and have been comprehensively described in scientific journals. However, so far, most of the demonstrations are limited to the lab, using 2D materials in the form of small exfoliated flakes. Iuliana Radu: “The real challenge today is maturing these concepts from flake-based devices towards real products that can be mass produced; only then, can they revolutionize multiple industries. And this has become a key goal at imec. Our goal is to demonstrate the manufacturability of these devices in a 300mm CMOS environment. And we house the expertise to run process flows on these materials (FIGURE 1). At imec, we work on all the unit process steps and on the sequence of steps towards an end application (e.g. TFETs, optical I/O, interconnects), and combine this with modeling and device benchmarking. We also take part in the Graphene Flagship, Europe’s 1 billion euro program that covers the whole value chain from materials production to components and systems.”

Materials 1

The road towards manufacturability

Due to the nature of the 2D materials, almost every unit process step such as contacting, doping, gate engineering, patterning and etch, etc, is a challenge. These steps, combined with the ability to integrate them into a cleanroom compatible process flow, are however essential to progress towards applications.

Cedric Huyghebaert: “A first challenge is related to the growth of these materials on large area templates, and their subsequent transfer to the final substrate. Graphene, for example, is typically grown on a metal template at high temperatures, up to 1000°C. The template is crucial, since the quality of graphene is very much dependent on the quality of the underlying template. Usually, the better the quality of graphene, the more difficult the transfer process becomes. At imec, we are actively working on the growth and defect-free transfer of graphene (FIGURES 2 and 3). In collaboration with AIXTRON, we focus on the synthesis of large area graphene using AIXTRON BM technology, compatible with 200 and 300mm processes. For the transfer, we rely on our knowledge on 3D Si integration processes. We also work on growth of MX2 materials by a direct sulfurization process or by atomic layer deposition in the 200 and 300mm imec fabs.”

Materials 2&3

Another hurdle is doping of the 2D semiconducting materials, which is needed to tune their energy levels and control their properties. Cedric Huyghebaert: “In the classical way, doping a semiconductor material means replacing an atom in the 3D structure. If you replace an atom in a 2D structure, you have a defect. So we have to consider different ways of doping these materials. At imec, we do this in collaboration with universities. We explore the possibility of achieving for example a semi-permanent doping by interaction with chemical molecules. Besides doping, contacting is also a challenge. The contribution of the electrodes to the total resistance of the device needs to be as low as possible. We therefore look into materials and architectures that allow for the lowest possible contact resistance.”

Several applications require a dielectric to be grown on top of the active semiconducting material. Stefan De Gendt: “In case of 2D materials, you have an almost perfectly passivated material, with no anchoring sites for the dielectric to nucleate. Consequently, the more perfect the 2D material, the more defective the dielectric on top may be.” Aaron Thean: “This is completely unlike 3D semiconductor processing, where a large part of material functionalization is achieved by surface and bulk material bond breaking and forming reactions, like dopant activation, oxidation, etc. This potential almost dangling-bond free weakly-interacting Van-Der-Waals nano-sheet system gives rise to new process challenges, as well as new opportunities like surface molecular doping and multi-layer channel stacking. One such approach is to transfer a 2D dielectric material to the 2D semiconducting material – like the hamburger experience described before.” Imec is working on understanding how to passivate, dope and grow dielectrics on various 2D materials. And there is patterning and etch, litho, and finally, characterization. Iuliana Radu:

“We are used to work with 3D bulk materials. But when you need to characterize only one or a few monolayers, there is hardly any material that can take part in the measurement. Therefore, the signals obtained with any classical characterization technique are extremely weak. And this requires new characterization strategies. At imec, we have established procedures that rely in a first phase on the physical characterization of the initial material properties. As the quality of the materials improve, we will cross-correlate physical characterization and electrical behavior of the layers.”

Demonstrating the potential

At IEDM 2014, imec and its associated lab at Ghent University have demonstrated an integrated graphene optical modulator on silicon. Cedric Huyghebaert:

“Integrated optical modulators with high modulation speed, small footprint and broadband a-thermal operation are highly desired for future chip-level optical interconnects. Due to its fast tunable absorption over a wide spectral range, graphene is well suited to achieve this. We could demonstrate a hybrid graphene-silicon modulator at bit rates up to 10Gb/s. This shows that it is possible to introduce CVD-grown graphene in a high quality Si platform and obtain a performance that can compete with traditional SiGe-based modulators. Moreover, if CVD graphene quality becomes more mature and can be brought into production, we will most probably end up with a device that is far less expensive than today’s optical components.”

Vacuum technology trends can be seen over the period of innovation defined by Moore’s Law, particularly in the areas of increasing shaft speed, management of pumping power, and the use computer modeling.

BY MIKE CZERNIAK, Edwards UK, Crawley, England

The sub-fab lies beneath. And down there in that thicket of pipes amidst the hum of vacuum pumps, the sentinel of gas combustors and the pulse of muscular machinery doing real work — innovation has also played a crucial role in enabling Moore’s Law. Without it the glamor boys up top with their bunny suits and FOUPS would not have achieved the marvelous feats of engineering derring-do for which they are so deservedly celebrated.

Vacuum and abatement are two of the most critical functions of the sub-fab. Many process tools require vacuum in the process chamber to permit the process to function. Vacuum pumps not only provide the required vacuum, they also remove unused process gases and by-products. Abatement systems then treat those gasses so they are safe to release or dispose. Vacuum and abatement systems in the sub-fab have had to innovate just as dramatically as the exposure, deposition and etch tools of the fab. In many cases, new processes would not have been possible without new vacuum pumps that could handle new materials and new abatement systems that could make those materials safe for release or disposal.

Moore’s Law

Moore’s Law originated in a paper published in 1965 and titled “Cramming More Components onto Integrated Circuits,” written by Gordon Moore, then director of research and engineering at Fairchild Semiconductor [1]. In it Moore observed that the economics of the integrated circuit manufacturing process defined a minimum cost at a certain number of components per circuit and that this number had been doubling every two years as the manufacturing technology evolved. He believed that the trend would continue for at least the short term, and perhaps as long as ten years. His observation became a mantra for the industry, soon to be known as Moore’s Law (FIGURE 1).

Vaccuum 1

More an astute observation than a law, Moore’s Law is remarkable in several respects. First, the rate of improvement it predicts, doubling every two years, is unheard in any other major industry. In “Moore’s Curse” (IEEE, March 2015) Vaclav Smil calculated historical rates of improvement for a variety of essential indus- tries over the last couple of centuries and found typical rates of a few percent, and order of magnitude less than Moore’s rate [2]. Second, is its longevity. Moore thought it was good for the short term, perhaps as long as ten years. This is perhaps due, at least partly, to the unique role Moore’s Law has assumed within the semicon- ductor industry where it has become both a guide to and driver of the pace of innovation. The Law has become a guiding principle – you shall introduce a new generation with double the performance every two years. It is a rule to live by, enshrined in the industry’s roadmap, and violated only at great peril. Only painfully did Intel recently admit that the doubling period for its latest generation appeared to have stretched to something more like two and a half years [3]. To an extent the Law is a self-fulfilling prophecy, which some have argued works to the detriment of the industry when it forces the release of new processes before they are fully optimized. Whatever you might think of it, the Law’s persistence is remarkable. The literature is full of dire predictions of its demise, all of which, at least so far, have proven premature.

Finally we must ask, what is meant by the names assigned to each new node? What exactly does 14nm, the current state of the art, mean? Although Moore originally described the number of components per integrated circuit, the Law was soon interpreted to apply to the density of transistors in a circuit. This was variously construed. Some measured it as the size of the smallest feature that could be created, which determined the length of the transistor gate. Others pointed to the spacing between the lines of the first layer of metal conductors connecting the transistors, the metal-1 half-pitch. These may have been a fairly accurate measures twenty years ago at the 0.35μm node, but node names have since steadily lost their connection to physical features of the device. It would be difficult to point to any physical dimension at the 14nm node that is actually 14nm. For instance, the FinFET transistor in a 22nm chip is 35nm long and the fin is 8nm wide.

What remains true is that in each successive generation the transistors are smaller and more densely packed and performance is significantly increased. Each generation seems to be named with a smaller number that is approximately 70% of the previous generation, reflecting the fact that a 70% shrink in linear dimension equates to a 50% reduction in area and therefore a nominal doubling in transistor density.

Enabling Moore’s Law in the sub-fab: A brief chronology

In the 1980s, new semiconductor processes and increasing gas flows associated with larger diameter wafers led to problems with aggressive chemicals and solids collecting in the oil used in oil-lubricated “wet” pumps, resulting in short service intervals and high cost of ownership. These were resolved by the development and introduction of oil-free “dry pumps” which have subsequently become the semiconductor industry standard.

Dry rotary pumps require extremely tight running clearances and multiple stages to achieve a practical level of vacuum. Additional cost of these machines, however was more than offset by the benefits offered to semiconductor manufacturing. Dry pumps use a variety of pumping mechanisms — roots, claw, screw and scroll (FIGURE 2).

Vaccuum 2

Many of these are new concepts, but modern machining capabilities made it possible to produce them at a realistic cost, the most notable being Edwards’ introduction of the first oil-free dry pump in the 1980’s. Each pumping mechanism has been successfully deployed and each has its own advantages and disadvantages in a given application. The scroll pump, for example, is unique in its ability to economically scale down to much smaller sizes.

In the early 1990s it became apparent that with the introduction of dry pumps, the pump oil no longer acted as a “wet scrubber” to collect process by-product gases, which therefore passed into the exhaust system. The solution was the development of the Gas Reactor Column (GRC) to chemically capture process exhaust gases in a disposable/recyclable cartridge, minimizing exhaust emissions to the atmosphere.

At about the same, new, more aggressive process gases being used in leading-edge semiconductor processes posed significant challenges for turbo molecular pumps (TMPs) due to the damage they caused to the mechanical bearings used to support their high-speed rotating shafts (typically ~40,000 rpm). Turbo pumps use rapidly spinning blades to impart direction to gas molecules, propelling them through multiple stages of increasing pressure. Early turbo pumps used oil- or grease-lubricated bearings. Similar to the problems encountered with oil sealed rotary pumps, the new process chemicals tended to degrade the oil, frequently causing pumping failures in as little as a few weeks. This problem was solved by introducing magnetic bearings to levitate the pump drive shaft and eliminate the need for lubricating oil.

In the mid-1990s the semiconductor industry started to use perfluorinated compounds (PFC’s) as a convenient source of chamber cleaning and etch gases. However, since only ~30% of the input gas was consumed in the process chamber, there were considerable PFC emissions to the atmosphere. Of particular concern was CF4 due to its half-life of 50,000 years. The solution was the Thermal Processor Unit which offered the first system with proven destruction reaction efficiency (DRE) of 90% or more for CF4.

In the 2000’s safety concerns regarding the increasing use of toxic gases led to increasing concerns about the abatement of these materials before they were released to the environment and the safety of personnel within the fab. Integrated vacuum and abatement systems, where everything is contained in a sealed and extracted enclosure, offer a significant improvement in safety. Integrated systems have since been refined with improvements such as a common control system, reduced footprint and installation costs, and shorter pipelines to reduce operating and maintenance costs.

Abatement systems have continued to evolve. New processes using new materials often require a different approach the abatement. For example, new technologies were developed for high hydrogen processes, copper interconnects and low k dielectrics.

Trends and prospects

Certain vacuum technology trends can be seen over this history of innovation, particularly in the areas of increasing shaft speed, management of pumping power, and the use computer modeling to monitor performance and predict when maintenance will be required so that it can be synchronized with other activities in the fab.

Shaft Speed

When dry pumps were first introduced, they typically operated at around 3,000 to 3,600 rpm. Today’s dry pumps use electric drives to run considerably faster, typically 6,000 rpm for claw, screw, and multi-stage roots pumps (FIGURE 3).

Vaccuum 3

Increasing a pump’s rotational speed delivers a number of advantages. It makes it possible to build more compact pumps and motors, with less internal leakage, which in turn, enables a reduction in the number of pump stages required. It also allows the speed to be reduced when wafers are not being processed, thereby saving energy. Combined, these benefits help reduce the overall pump cost.

Each type of pumping mechanism has different characteristics in the size and shape of volume to fill. A scroll mechanism, with a narrow, ported inlet and long, thin volume space, is one of the slowest pumping mechanisms to fill, so its performance does not increase in proportion to increasing shaft speed. Most scroll pumps operate at just 1500 rpm. A roots mechanism, by contrast, has a very large opening and a short volume length, enabling it to fill quickly allowing efficient use of higher shaft speeds.

The conductance ceiling for roots and screw pumps is probably ~15,000 rpm. Achieving this speed, will require incremental improvements in materials, bearings, and drives. It is likely that we will reach the conductance ceiling for most of the current primary pumping mechanisms within the next decade, although some, such as roots and screw mechanisms, may prove more durable than others.

Turbomolecular pump conductance is governed by blade speed and molecular velocities. Turbo performance has been limited primarily by the maximum speed the bearings and rotor can withstand. The industry is looking for new materials that are lighter and stronger to enable increased speed. While this pump type may be reaching its conductive limit on heavier gases, it is far from reaching it for lighter gases, such as hydrogen. This may take a much longer time to achieve.

Power management

Significant advances have been made in improving the energy efficiency of both vacuum pumps and abatement systems. Improvements in pump design have increased energy efficiency. Variable speed motors and controllers allow better matching of the motor speed to varying pump requirements. Idle mode allows both pumps and abatement systems to go into a low power mode when not in use. Improvements in burner design have reduced the fuel consumption of combustion based abatement. With the increase in concern about environmental impact and carbon foot print continued improvement in this area can be expected.

Modeling

Computer modeling has been applied extensively to all stages of pump performance. Such variables as stage size, running clearance, leakage, and conductance can all be modeled quite effectively. This allows design simulation and the optimization of performance, such as the shape of the power and speed curve. In this way, a pump can be designed for specific duties, such as load lock pumping or processing high hydrogen flows (FIGURE 4).

Vaccuum 4

Vacuum pumps of the future will be more reliable and capable of operating for longer periods of time before requiring maintenance. They will be safer to operate, will occupy less fab space, run cleaner and require less power, as well as generate less noise, vibration, and heat. They will also have improved corrosion resistance and the ability to run hotter when required.

As a result, vacuum pumps will be more environmentally friendly, running cleaner and using less power to help reduce their carbon footprint. In addition, they will likely make much greater use of recycled materials and use fewer consumables, thereby helping to reduce overall pump costs. The pumps will be easier to clean, repair, and rebuild for reuse.

Likely technical developments will also include higher shaft speeds, a growing proliferation of pump mechanisms and combinations of mechanisms to increase performance. Finally, vacuum pumps will incorporate new materials and improved modelling to further sharpen performance and reduce system and operating costs.

References

1. G. Moore, “Cramming more Components onto Integrated Circuits” in Electronics, April 19, 1965.
2. V. Smil, “Moore’s Curse” in IEEE Spectrum, March 19, 2015.
3. R. Courtland, “The Status of Moore’s Law: It’s Complicated” in IEEE Spectrum October 28, 2013.

MIKE CZERNIAK is the Environmental Solutions Business Development Manager, Edwards UK, Crawley, England.

The use of sapphire in the manufacturing of Light Emitting Diodes (LEDs) is covered in the second part of a two part series.

BY WINTHROP A. BAYLIES and CHRISTOPHER JL MOORE, BayTech-Resor LLC, Maynard, MA

In Part 1 of this article, we discussed the optical and mechanical properties of sapphire and its use in the mobile device industry. In part 2, we will discuss the use of sapphire in the LED process including some of the newer technologies that produce these devices.

Solid state lighting (or “LED bulbs” as they are commonly known) have become a mainstream product in our culture. Their longer life time and lower power usage (along with the banning of incandescent bulbs) have ensured that more and more consumers are moving to this type of lighting. Like a fluorescent light (where the white light is produced by a phosphor coating excited by the excited gas molecules) solid state lights use a phosphor excited by the short wavelength light emitted by an LED. What you may not know is that about 8 out of every 10 LED bulbs sold uses sapphire as the starting material for their manufacturing process.

As we summarized in part 1, sapphire has some good points: hard, strong, optically transparent and chemically inert (there is a reason high end watches use sapphire crystals) and some bad points: hard, strong, and chemically inert (which is why sapphire crystals are more expensive than glass). What we did not discuss is that single crystal sapphire has turned out to be an ideal material on which to grow the layers of material needed to make an LED.

As FIGURE 1 shows an LED is made by growing epitaxial layers of Gallium Nitride (GaN), AlGan or InGaN on a substrate. Ideally one would use GaN as the substrate material (similar to growing epitaxial Si on Si for integrated circuits) as this would result in the highest quality material and thus the most efficient LED’s. Unfortunately GaN substrates are very difficult to make in any reasonable size and the costs have ruled out using this approach except in certain niche markets. The three main substrate alternatives have been silicon (Si), silicon carbide (SiC) and sapphire.

Sapphire 1

As a substrate material Si would be expected to be the best choice due to its high quality, low cost and ready availability. To date, the quality of GaN type layers grown on Si has not been sufficient for large scale manufacturing processes. Work continues on improving this process and although it may one day dominate the process it currently remains a small part of the business.

SiC substrates are higher cost than Si but have been successfully used for LED manufacturing processes. Much of the LEDs produced by Cree (who also manufacture SiC substrates) use this type of substrate. However, the higher cost and limited availability of 6 inch SiC material means that the majority of LED producers use sapphire.

Thus sapphire substrates account for the majority of LED devices produced [1]. Although not as cheap as Si they are cheaper than SiC, available from a number of manufacturers and are able to survive the high temperature processes needed to produce a short wavelength LED. FIGURE 2 schematically shows the production process for a typical non-patterned sapphire wafer.

Sapphire 2

The sapphire production process starts when a seed crystal and a mixture of aluminum oxide and crackle (un-crystallized sapphire material) is heated in a crucible. Included in this mix is a cookie-sized seed crystal which forms the pattern to be replicated as the crystal grows. Each furnace manufacturer has its own special recipe which heats the material using a specific temperature/ time profile based on the size of melt and the type of crystal to be grown. Once the correct growth temperature is reached the melt is cooled (this process can take two weeks depending on the amount of sapphire being produced) using another set of carefully controlled time/temperature profiles. When done correctly, the cookie-sized seed grows and produces a single-crystal sapphire boule. (FIGURE 3). In reality, two weeks is a long time and any number of can go arise during this process including gas bubbles, mechanical faults such as cracks and contamination. Each of these problems affects the sapphire and its crystal properties. Each crystal fault can become a nucleation site for defects in the epitaxy grown on wafers produced from the boule. There is a clear correlation between the time taken to grow a boule and the potential quality of the boule produced. Many of the problems encountered in the upscaling of the sapphire production process have come from trying to grow large boules at high speeds.

Sapphire 3

At this point in the process you have a boule which in fact has the wrong crystal orientation for growing GaN epitaxy. Unlike the Si crystal growth process where the cylindrical boules can be ground to size and then cut into wafers, sapphire boules are often cored at right angles to the boule axis. Some companies produce sapphire using a silicon like process [2] but the majority of sapphire produced has to be cored. Thus the next step in the process is to “core-drill” a boule to produce one or more smaller round cylinders (ingots) depending on the original boule size and the size of wafers to be produced.

The ability to grow large sized boules on a regular basis is not in question; most important is how much of that boule is bubble-, crack- and impurity-free. In some cases the boules are inspected with various metrology techniques to determine which sections of the boule can be used and which cannot. The section of the boules not used is recycled into the original growth process (unless contaminated). Obviously if one is producing 6 inch wafers larger volumes of the boule need to be defect free than if one is producing 2 inch or 4 inch. Currently most of the LEDs produced are produced on 4 inch wafers with a few newer 6 inch lines and a number of older 2 inch lines. 8 inch sapphire wafers do exists but are not in mass production at this time.

The process after this is very similar to that used in the silicon industry to produce the wafers which will be used as substrates. A diamond saw (remember, Sapphire is a very hard material) is used to cur the ingot into a number of thin disc shapes by cutting perpendicular to the ingot’s long sides. Each of these discs is then ground to its final size, surface-ground and mechanically and chemically polished to produce sapphire substrates. These substrates, after cleaning, can be used as starting material for the epitaxial process used to produce the LED structure. FIGURE 4 shows some pictures of typical 2, 4 and 5 inch sapphire substrates. As discussed earlier the more defect free the surface is the better the quality of epitaxial film that can be grown. The video listed in reference [3] produced by GTAT shows many of the steps discussed above.

Sapphire 4

Recently one further step has been taken to produce what are called patterned sapphire substrates (PSS). The multiple quantum well layer shown in Fig. 1 is the layer that generates light in an LED. As you can imagine this light is emitted in all directions. However, once packaged most LED’s emit light from only one surface of the device. In the case of Fig. 1, a typical package collects the light emitted from the top of the device. This of course means that all of the light emitted in any other direction is wasted. In particular, since sapphire is transparent, little of the light emitted toward the substrate can be used.

One obvious solution to this would be to coat the substrate with something that reflects the light (i.e. metal). Unfortunately this interferes with the epitaxial layer growth process, producing poor devices. One partial solution to the reflection problem is to pattern the sapphire surface such that it reflects light. This pattern can be a series of microscopic pyramidal structures or more rounded bump like structures on the surface. FIGURE 5 shows top and side view SEM pictures of some of the patterns produced by manufacturers. These patterns scatter the light and reflect some of it back towards the surface of the device increasing the light output from the LED. In addition to increasing the apparent light output a number of manufacturers have claimed that epitaxial layers grown on patterned substrates is of better quality than that grown on bare sapphire substrates.

Sapphire 5

Patterned substrates can be produced by the manufacturer of the sapphire substrates. However, factories now exist which begin with a non-patterned substrate and produce specific patterns (normally via chemical etch) for specific LED manufacturers.

Once valued only as a gemstone, sapphire is now an engineered material with a wide variety of industrial uses. These two article have concentrated on its use in mobile devices for everything from camera lens covers to touch sensors and touch screens to the starting material on which most of the solid state lights produced are made. Cost of the material continues to be a limiting factor in its widespread adoption for certain industries. However, as the technology for producing sapphire matures material costs are decreasing and in some ways sapphire substrates have become a commodity rather than a rarity.

Additional reading and viewing material

1. http://rubicontechnology.com/sites/default/files/Opportu- nities%20for%20Sapphire%20White%20Paper-Rubicon%20 Technology.pdf
2. http://www.arc-energy.com/products-services/CHES/Foundations/1
3. https://www.youtube.com/embed/mHrDXyQGSK0