Yearly Archives: 2015

Recent trends and future directions for wafer bonding are reviewed, with a focus on MEMS.

BY ERIC F. PABO, CHRISTOPH FLÖTGEN, BERNHARD REBHAN, PAUL LINDNER and THOMAS UHRMANN, EV Group, St. Florian, Austria

All devices and products are evaluated to varying degrees on the following factors: 1) availability or assurance of supply, 2) cooling requirements, 3) cost, 4) ease of integration, 5) ease of use, 6) performance, 7) power requirements, 8) reliability, 9) size, and 10) weight. MEMS devices are no exception and the explosive growth of MEMS devices during the last decade was driven by substantial improvements in some of the aforementioned variables. MEMS manufacturing is based on patterning, deposition and etch technologies developed over the last 50 years for the manufacturing of ICs along with the relatively new technologies of aligned wafer bonding and deep reactive ion etch (DRIE). This article will review the recent trends and future directions for wafer bonding with a focus on MEMS along with some mention of wafer bonding for RF and power devices.

The incredible growth in MEMS over the last 20 years has been enabled by the development of the DRIE process by Bosch and by aligned wafer bonding. Many MEMS devices have very small moving parts, which must be protected from the external environment. Initially, this was done using special packages at the die level, which was relatively expensive. Wafer-level capping of MEMS devices seals a wafer’s worth of MEMS devices in one operation, and these capped devices can then be packaged in a much simpler and lower-cost package. Anodic bonding and glass frit bonding were the initial bonding processes used for MEMS and are often referred to as “tried and true.” However, both of these processes have challenges, and as a result, few new MEMS products and processes are being developed using these processes.

Anodic bonding requires the presence of Na or some other alkali ion which causes several problems. The first is that Na ions are driven to the exterior of the wafer during the bonding process and will accumulate on the bonding tooling, requiring the tooling be cleaned on a periodic basis. The second is that Na can cause CMOS circuits to fail – preventing anodic bonding from being used to combine MEMS and CMOS. Almost all MEMS devices require a CMOS ASIC to process the output signal from the MEMS device. Historically, this integration has been done at the package level with wire bonding but now some high-volume products are available where the integration of the CMOS and the MEMS is done as part of the wafer-level capping process. Also, anodic bonding typically requires a maximum process temperature of over 400 ̊C and the presence of a strong electric field during bonding. The high temperature influences the throughput of the bonding process and some devices cannot tolerate the high electric field.

Even though the majority of the MEMS parts that exist today were probably bonded using glass frit, this wafer bonding process has several challenges as well. The major one is that the glass frit is applied and patterned using a silk screen process, which has a typical resolution in the 250 to 300μm range. This means that as the size of the MEMS die decreases, an ever greater percentage of the wafer surface is consumed by the bond line, which limits the number of die per wafer and increases the cost per die. FIGURE 1 shows the effect of bond line width and die size on the percentage of the wafer surface that is consumed by the bond line [1]. Also, many of the glass frits contain Pb to lower the glass transition temperature. Although the amount of Pb is very small, there is widespread concern regarding the use of Pb and being RoHS (Restriction of Hazardous Substance) compliant.

Wafer bonding 1

 

Both anodic bonding and glass frit bonds are nonconductive and therefore not suitable for the formation of connections to electrically conductive through silicon vias (TSVs) at the same time as the seal ring is formed. This means that these processes are not as suitable for the 3D integration of CMOS and MEMS.

For MEMS applications there is a strong trend toward the use of metal-based wafer bonding; in particular, liquid metal-based processes such as solder, eutectic and transient liquid phase (TLP). This trend is driven by the aforementioned challenges with anodic and glass frit bonding. Moving from glass frit to a metal-based bonding for a die size of 2mm2 can result in up to a 100% increase in the die per wafer. This doubling of the die per wafer will result in an approximately 50% decrease in the cost per MEMS die.

Some of the metal-based aligned-wafer-bonding processes that are currently used in high-volume manufacturing are: Au-Au thermo-compression bonding, which has been in volume production for over 10 years; and Al-Ge eutectic bonding, which is very popular even though it requires a very careful process setup and control and has a peak process temperature of over 400 ̊C. Cu-Sn transient liquid phase (TLP) wafer bonding, another metal-based process, is used in low-volume production of hermetically sealed devices such as micro-bolometers [2] but is not currently used in medium- or high-volume production. Cu-Sn TLP wafer bonding also requires very careful design and control of the metal stack as well as the bonding process.

The maximum process temperature that is required for a bonding process has three significant effects. The first is that the bonding process takes longer as the maximum process temperature increases due to the increased time required to heat up to the bonding temperature from the loading temperature and the time required to cool down to the unload temperature. The bonding process time determines the throughput of the wafer bonder(s) and factors into the cost of ownership (CoO) for the bonding process. The second is that the process temperature required for bonding may damage the devices on the wafers being bonded. The aluminum metallization of certain CMOS devices may be damaged at tempera- tures greater than 450 ̊C. The VOx or vanadium oxide used on the sensor pixels for micro-bolometers will be damaged by temperatures greater than 200 ̊C. The third is the internal stress that is created when wafers with mismatched coefficients of thermal expansion (CTE) are bonded together at an elevated temperature. In this case the higher the bonding temperature, the higher the internal stress at room temperature.

Unless the bonding metals are noble metals such as Au, oxides will form on the metal layer and have a negative effect on the bonding process – making an oxide management strategy necessary. This oxide management strategy can have elements that prevent the oxide from growing using special storage conditions or coatings, removing the oxide before bonding, and heating in an inert or reducing environment. In some cases, the bonding process can also be adjusted to overcome the effect of the oxides by increasing the pressure, temperature and time for the bonding process.

There is substantial interest in bonding processes and equipment that are capable of removing the native oxide from metals and other materials prior to wafer bonding and preventing the regrowth of oxide. Equipment capable of running such a process will have several substantial advantages. The first is that it will allow materials that have been previously difficult to bond to be bonded at or near room temperature. For example, Al-Al thermo-compression wafer bonding without the removal of the native oxide has previously been demonstrated, but required a process temperature of greater than 500 ̊C, which made the process unattractive for production [3]. Low temperature Al-Al thermo-compression bonding has been demonstrated by using a special surface treatment and doing all handling in a high vacuum environment (FIGURE 2). A low-temperature Al-Al thermo-compression bonding process has the advantage of using an inexpensive readily available conductive material and increased throughput due to the low process temperature. In addition to being used to form the seal ring, this low-temperature Al-Al bonding could be used for the 3D integration of MEMS and CMOS through the use of TSVs filled with Al.

Wafer bonding 2

This surface pretreatment and handling in high vacuum enables covalent bonding of two wafers at or near room temperature with no oxide in the interface. This process has several very significant advantages. The first is that the low process temperature allows the bonding of substrates with substantially different CTE such as LiNbO3 or LiTaO3 to Si or glass. This combination of materials has drawn the interest of RF filter manufacturers due to its ability to reduce the temperature sensitivity of surface acoustic wave (SAW) devices. The second is that materials with both a CTE mismatch and a lattice mismatch can be bonded together without the development of major crystalline defects that can arise when forming the material stack by growing one crystalline layer on top of another when there is a lattice mismatch. One interesting possibility is bonding GaN to diamond for applications where large amounts of heat must be removed from the GaN device. In addition, bonding a thin layer of monocrystalline SiC to a polycrystalline SiC could offer wafers with the electrical performance of monocrystalline SiC at a cost closer to the cost of polycrystalline SiC. Another application of this bonding process is to join materials such as GaInP, GaAs, GaInAsP and GaInAs for fabrication of quadruple junction concentrated solar cells with record conversion efficiency of 44.7% [4, 5].

A high-vacuum cluster tool capable of aligned wafer bonding offers significant advantages for MEMS applications where the vacuum level in the cavity after bonding is important, such as gyroscopes and micro-bolometers (FIGURE 3) [6]. Modules can be added to the base cluster tool to enable the wafers to be baked out at a controlled elevated temperature prior to alignment and bonding in high vacuum. Getter activation can also be done in the bake-out module without loading or saturating the getter, as all subsequent steps are done in high vacuum. For devices where getter activation requires a high temperature and the other wafer has thermal limits, two bake-out chambers allow a high-temperate bake-out and getter activation while the other chamber performs a lower-temperature bake out. For example, micro-bolometers that used vanadium oxide on the detector pixel have a thermal limit of about 200 ̊C, whereas the cap wafer contains a getter that should be activated around 400 ̊C. Also, the high-vacuum capability is beneficial for producing devices that are heated and use vacuum for thermal isolation because a higher vacuum reduces the heat loss, which reduces the power required to maintain the fixed temperature.

Wafer bonding 3

This high-vacuum cluster tool allows the separation of the process steps of bake out, surface treatment, alignment and bonding as well as allows the tool to be configured to the specific application needs. Also, the cluster tool base makes it possible to develop modules for specific applications without redesigning the entire tool.

The availability of reliable, highly automated, high-volume aligned wafer bonding systems and processes was one of the keys to the growth of MEMS over the past 15 years. The next 15 years are expected to be an exciting period of advancement for aligned wafer bonding as new equipment and processes are introduced, such as the tools and processes that allow separate pre-processing of the top and bottom wafer, as well as all handling, alignment, and bonding in vacuum. The cluster tools that will be used to do this will allow for further innovation by adding new modules to the cluster tool. In addition, the ability to remove surface oxides prior to bonding, prevent these oxides from reforming, bond at or near room temperature, and have a strong, oxide-free, optically transparent, conductive bond with very low metal contamination will allow many new product innovations for RF filters, power devices and even products that have not yet been thought of.

References

1. E. F. Pabo, “Metal Based Bonding – A Potential Cost Reducer?,” in MEMS MST Industry Conference, Dresden, 2011.
2. A. Lapadatu, “High Performance Long Wave Infrared Bolometer Fabricated by Wafer Bonding,” Proc. SPIE, vol. 7660, no. 766016-12.
3. E.Cakmak,“Aluminum Thermocompression Bonding Characterization,” in MRS Fall Mtg, Boston, 2009.
4. Fraunhofer ISE, Fraunhofer ISE Teams up with EVGroup to Enable Direct Semiconductor Wafer Bonds for Next-Generation Solar Cells, Freiburg: Press Release, 2013.
5. F. Dimroth, “Wafer bonded four-junction GaInP/GaAa/GaInAsP/ GaInAs,” Progress in Photonics, vol. 22, no. 3, pp. 277-282, 2014.
6. V.Dragoi,“Wafer Bonding for Vacuum Encapsulated MEMS,” Proc. SPIE9517 Smart Sensor, Actuators, and MEMS VII, 2015.

ERIC F. PABO is Business Development Manager, MEMS; CHRISTOPH FLÖTGEN, and BERNHARD REBHAN are scientists, PAUL LINDNER is Executive Technology Director and THOMAS UHRMANN is Director Of Business Development at EV Group, St. Florian, Austria

Due to the growth of the semiconductor business, the wider adoption of Cu pillar solutions and the introduction of Flip Chip technology for LED and CMOS Image Sensors (CIS) applications, the Flip Chip market is expending. Under this context, more and more industrial companies including OSATs, IDMs IC foundries and bumping house undertake in this market.

The “More than Moore” market research and strategy consulting company Yole Développement (Yole) explored this industry and proposes today a detailed technology and market report, entitled “Flip Chip: Technologies & Market Trends”. Yole’s team is daily discussing with the leaders of the Advanced Packaging industry. Based on these interactions, the consulting company highlights the evolution of the technical needs and market trends. These major results make Yole’s analysts to think that full capacity should be reached in 2017.

What are the required investments to support this growth? Are there competitive technologies such as TSMC’s new solution, high-performance integrated fan-out wafer level packaging (InFO-WLP), that could answer the market needs and compete Flip Chip technology?

Under “Flip Chip: Technologies & Market Trends” report, Yole’s advanced packaging team provides an overview of Flip Chip technology and market trends. The company reviews the competitive landscape including player dynamics and key market trends; they also detail the Flip Chip market capacity and wafer forecast. Yole’s report also includes a detailed technology roadmap.

“Based on the discussions we had with the major advanced packaging companies, at Yole, we think that demand for Flip Chip is expected to reach the current maximum capacity in 2017,” said Santosh Kumar, Senior, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole. And he adds: “Therefore, new investment will be needed starting in 2018.”

Since Cu pillar processing can be performed by standard foundries and IDMs, the supply chain may see some slight modification. Yole’s analysts expect higher investment in Cu pillar 12” line wafer bumping lines from wafer foundries such as TSMC and SMIC. This change will affect OSATs’ wafer bumping revenue since foundries will gain market share.

OSATs will maintain their strong position in wafer bumping and assembly thanks to of their huge experience and low cost solutions. Their business model enables them to better control the supply chain, as they provide for the complete set of flip-chip services: package design and qualification, wafer bumping, substrate in-sourcing, assembly and final test.

However, big IDM companies like Intel and Samsung maintain their dominance in terms of wafer bumping capacity.

flip chip bump

“At Yole, we expect that even in 2020 Intel will remain the highest-capacity player in Cu pillar wafer bumping,” commented Thibault Buisson, Technology & Analyst, Advanced Packaging at Yole. Foundries and OSATs are also establishing joint ventures for wafer bumping to provide turnkey solutions to customers from chip fabrication to assembly at competitive cost.

And what about the Chinese companies? Do they have a role to play in the Flip Chip market? Chinese players are significantly increasing their presence in wafer bumping and Flip Chip assembly by mergers and acquisitions. JCET acquired STATS ChipPAC and FCI was acquired by Tianshui Huatian Technology Company.

In that context, Yole’s report, Flip Chip: Technologies & Market Trends report gives insights on the future strategies that players may adopt. A detailed description of this report is available on www.i-micronews.com, advanced packaging reports section.

Graphene is the first truly two-dimensional crystal, which was obtained experimentally and investigated regarding its unique chemical and physical properties. In 2010, two MIPT alumni, Andre Geim and Konstantin Novoselov were awarded the Nobel Prize in Physics “for ground-breaking experiments regarding the two-dimensional material graphene.” There has now been a considerable increase in the number of research studies aimed at finding commercial applications for graphene and other two-dimensional materials. One of the most promising applications for graphene is thought to be biomedical technologies, which is what researchers from the Laboratory of Nanooptics and Plasmonics at the MIPT’s Center of Excellence for Nanoscale Optoelectronics are currently investigating.

Label-free biosensors are relatively new in biochemical and pharmaceutical laboratories, and have made work much easier. The sensors enable researchers to detect low concentrations of biologically significant molecular substances (RNA, DNA, proteins, including antibodies and antigens, viruses and bacteria) and study their chemical properties. Unlike other biochemical methods, fluorescent or radioactive labels are not needed for these biosensors, which makes it easier to conduct an experiment, and also reduces the likelihood of erroneous data due to the effects that labels have on biochemical reactions. The main applications of this technology are in pharmaceutical and scientific research, medical diagnostics, food quality control and the detection of toxins. Label-free biosensors have already proven themselves as a method of obtaining the most reliable data on pharmacokinetics and pharmacodynamics of drugs in pre-clinical studies. The advantages of this method are explained by the fact that the kinetics of the biochemical reactions of the ligand (active substance) with different targets can be observed in real time, which allows researchers to obtain more accurate data about the reaction rates, which was not previously possible. The data obtained gives information about the efficacy of a drug and also its toxicity, if the targets are “healthy” cells or their parts, which the drug, ideally, should not affect.

This is a schematic cross-sectional view of the graphene biosensor chip from US Patent Application No. 2015/0301039 (Oct 2015). Credit: MIPT

Most label-free biosensors are based on the use of surface plasmon resonance (SPR) spectroscopy. The “resonance” parameters depend on the surface properties to such an extent that even trace amounts of “foreign” substances can significantly affect them. Biosensors are able to detect a trillionth of a gram of a detectable substance in an area of one square millimetre.

Commercial devices of this type are sold in a format similar to “razor blade” business model, which includes an instrument and highly expensive consumables. The instrument is the biosensor itself, comprising optics, microfluidics and electronics. The consumables for biosensors are sensor chips comprised of a glass substrate, thin gold film and a linking layer for the adsorption of biomolecules. Sensor chips currently use two types of linking layer technology that were developed more than 20 years ago and are based either on a layer of self-assembled thiol molecules, or a layer of hydrogel (usually carboxymethyl dextran). The profit that companies have received from the sale of biosensors and consumables is evenly distributed at a ratio of 50:50.

The authors of the patent, Aleksey Arsenin and Yury Stebunov, are proposing an alternative to existing sensor chips for biosensors based on surface plasmon resonance. Under certain conditions, the use of graphene or graphene oxide as a linking layer between metal film and a biological layer comprised of molecule targets is able to significantly improve the sensitivity of biodetection. The graphene sensor chips were tested on Biacore T200 (General Electric Company) and BiOptix 104sa biosensors.

The use of graphene oxide sensor chips to analyse DNA hybridization reactions is described in detail in a recent paper by the authors in the American Chemical Society’s journal ACS Applied Materials & Interfaces. In addition to a higher level of sensitivity than similar commercial products, the proposed sensor chips possess the required property of biospecificity and can be used multiple times, which greatly reduces the costs of conducting biochemical studies using the chips.

The use of graphene increases the sensitivity of analyses conducted using SPR spectroscopy more than ten times, which will revolutionize the field of pharmaceutical biodetection. The application of biosensors is currently limited to analysing biological products based on large molecules, whilst more than half of the drugs produced each year have a low molecular weight (no more than a few hundred Daltons). Immobilization of drug targets on the surface of a graphene chip will enable scientists to test the interaction between targets and small molecules. An example of this could be the development of drugs that act on receptors coupled with G-proteins (GPCRs), which are currently the targets for 40% of drugs on the market. Pharmaceutical studies of drugs acting on GPCRs are not currently conducted using SPR due to the insufficient sensitivity of the method. It is therefore expected that the use of graphene biosensors in pharmaceutical studies will help to accelerate the development of drugs and overcome dangerous diseases that cannot be treated with the drugs currently on the pharmaceutical market.

The authors are continuing to work to improve their development and expect that for certain reactions, biosensor chips based on the new carbon materials will provide a level of sensitivity that is dozens or hundreds of times higher than similar commercial products currently on the market. They are also considering the possibility of commercializing graphene chips. In 2014 alone, approximately 10 billion US dollars were spent on pre-clinical studies. According to estimates, the annual market for biosensor chips is worth a total of approximately 300 million US dollars. The excellent properties of graphene biosensor chips will enable them to compete strongly with existing types of chips – up to one third of the entire market.

Researchers from RMIT University in Melbourne have helped crack the code to ultra-secure telecommunications of the future in an international research project that could also expedite the advent of quantum computing.

A team co-led by RMIT MicroNano Research Facility Director Professor David Moss has added a new twist to create photon pairs that fit on a tiny computer chip.

Researchers pioneered a new approach to create photon pairs that fit on a computer chip. Credit: RMIT University

The breakthrough, published in Nature Communications, heralds the next-generation of integrated quantum optical technology, being compatible with current technology and secure communications.

The team pioneered a new approach based on a micro-ring resonator – a tiny optical cavity – in which energy conservation constraints can be exploited to suppress classical effects while amplifying quantum processes.

They used laser beams at different wavelengths and then had to overcome the risk of the two pump beams being able to destroy the photons’ fragile quantum state.

“One of the properties of light exploited within quantum optics is ‘photon polarization’, which is essentially the direction in which the electric field associated with the photon oscillates,” Moss said.

“Processes used to generate single photons or photon pairs on a chip allow the generation of photons with the same polarization as the laser beam, forcing us to find a way to directly mix, or cross-polarize, the photons via a nonlinear optical process on a chip for the first time.”

Moss worked with Professor Roberto Morandotti at the INRS-EMT in Canada and researchers from the University of Sussex and Herriot Watt University, City University of Hong Kong, and the Xi’an Institute in Chin, on the research.

“While a similar suppression of classical effects has been observed in gas vapours and complex micro-structured fibres, this is the first time it has been reported on a chip, opening a route for building scalable integrated devices that exploit the mixing of polarization on a single photon level,” he said.

“It also has the advantage that the fabrication process of the chip is compatible with that currently used for electronic chips which not only allows the exploitation of the huge global infrastructure of CMOS foundries, but will ultimately offer the potential to integrate electronic devices on the same chip.

“Both of these are fundamental requirements for the ultimate widespread adoption of optical quantum technologies.”

Micron Technology, Inc. this week announced the production of 8GB DDR4 NVDIMM, the company’s first commercially available solution in the persistent memory category. Persistent memory delivers a unique balance of latency, bandwidth, capacity and cost, delivering ultra-fast DRAM-like access to critical data and allowing system designers to better manage overall costs. With persistent memory, system architects are no longer forced to sacrifice latency and bandwidth when accessing critical data that must be preserved.

As data centers evolve to handle the massively growing influx of data, the cost of moving data and storing it away from the CPU becomes increasingly prohibitive, creating the need for a new generation of faster, more responsive solutions. Persistent memory, a new addition to the memory hierarchy, allows greater flexibility in data management by providing non-volatile, low latency memory closer to the processor. With NVDIMM technology, Micron delivers a persistent memory solution capable of meeting many of today’s biggest computing challenges.

Micron’s NVDIMM begins to address some of the difficult architectural challenges facing CIOs today, and is ideal for applications such as big data analytics, storage appliances, RAID cache, In-Memory Databases and On Line Transaction Processing. Traditional memory architectures force system architects to sacrifice latency or bandwidth needed to access the critical data for these applications, and as a result, performance is often limited by I/O bottlenecks. Micron’s NVDIMM solutions deliver architectures suited to meet the demands of applications that require high performance coupled with frequent access to large data sets while being sensitive to down time. In the event of a power failure or system crash, Micron’s NVDIMM solution provides an onboard controller that safely transfers data stored in DRAM to the onboard non-volatile memory, preserving the data that would otherwise be lost.

“Micron is delivering on the promise of persistent memory with a solution that gives system architects a new approach for designing systems with better performance, reduced energy usage and improved total cost of ownership,” said Tom Eby, vice president for Micron’s compute and networking business unit. “With NVDIMM, we have a powerful solution that is available today. We’re also leading the way on future persistent memory development by spearheading R&D efforts on promising new technologies such as 3D XPoint memory, which will be available in 2016 and beyond.”

Persistent memory: A new architecture for the new data age

Micron’s NVDIMM technology is a non-volatile solution that combines NAND flash reliability, DRAM performance and an optional power source into a single memory subsystem, delivering a powerful solution that ensures data stored in memory is protected against power loss. By placing non-volatile memory on the DRAM bus, this new architecture allows customers to store data close to the processor and significantly optimize data movement by delivering faster access to variables stored in DRAM.

“Persistent memory is a critical new technology to move computing forward. The amount of information that can be found in data produced by today’s organizations requires a platform with the performance abilities to more efficiently store, manage and analyze large data sets frequently and quickly,” said Greg Wong, founder and principal analyst at Forward Insights. “Micron’s NVDIMM technology is a positive step in this direction, delivering a solution that fills a gap in the current memory hierarchy right now.”

Additional Resources:

Bosch Sensortec announced that its CEO, Dr. Stefan Finkbeiner, has been chosen by the MEMS & Sensors Industry Group to receive its prestigious MEMS/Sensors Lifetime Achievement Award.

Stefan Finkbeiner: CEO of Bosch Sensortec (PRNewsFoto/Bosch Sensortec)

Stefan Finkbeiner: CEO of Bosch Sensortec (PRNewsFoto/Bosch Sensortec)

The award was made at the recent MEMS Executive Congress US 2015 in Napa, California.

Dr. Finkbeiner was appointed as CEO of Bosch Sensortec in 2012, having previously served as General Manager and CEO of Akustica Inc, a Bosch Group company which develops MEMS microphones for consumer electronics applications and is located in Pittsburgh, PA, USA. Dr. Finkbeiner joined Robert Bosch GmbH in 1995 and has been working for more than 17 years in different positions related to the research, development, manufacturing, and marketing of sensors. Senior positions at Bosch have included Director of Marketing for sensors, Director of Corporate Research in microsystems technology, and Vice President of Engineering for sensors.

MEMS Industry Group (MIG) is the trade association advancing MEMS and sensors across global markets. Its members comprise nearly 200 companies and industry partners.

Now in its eleventh year, MEMS Executive Congress is an annual event that brings together business leaders from a broad spectrum of industries: automotive, communications, consumer goods, energy/environmental, industrial and medical.

Today, SEMI announced additional details on the 29th annual SEMICON Korea, with more than 40,000 expected attendees, the largest semiconductor technology event in Korea.  The theme for the January 27 through 29 exhibition at Seoul’s COEX is “Connect to the Future – Markets, Technology, and People.”  SEMICON Korea will feature new innovations, technologies and present the future of semiconductor processing technology. The event will be co-located with LED Korea 2016, the leading exhibition for LED manufacturing.

SEMICON Korea 2016 will feature over 530 leading companies from 20 countries with expectation of a record 1,870 exhibition booths. With 97 presentations on diverse topics for 60 hours, the event offers exceptional opportunities to learn and network. In addition, four industry thought leader keynotes will provide insight into the future of global semiconductor industry (including a keynote that will be announced soon before SEMICON Korea):

  • Dr. Ahmad Bahai, CTO of Texas Instruments
  • Dr. Aart de Geus, chairman and co-CEO of Synopsys: “IoT: from Silicon to Software”
  • Berthold Hellenthal, head of the Audi Progressive Semiconductor Program at Audi: “Inventing the Automotive Future”

The keynotes will be followed by a broad offering of deep programs including the SEMI Technology Symposium where experts in semiconductor manufacturing processes will discuss the latest issues and new technologies. The event also covers advanced lithography, advanced process technology, device technology, plasma science and etching, contamination-free manufacturing and CMP, and advanced packaging technologies.

In addition, forums and seminars cover major issues in the semiconductor market, including System LSI, Metrology and Inspection (MI) and Test. The SEMI Standards Program, which develops the global standards indispensable in the strengthening of international competitiveness, will conduct a strong program. Two other programs are increasingly popular with their exclusive navigation of the semiconductor manufacturing supply chain:  Supplier Search – featuring the world’s leading materials manufacturers, and OEM Supplier Search – which facilitates business cooperation between global suppliers and Korea’s parts manufacturers.  The President Reception is a SEMICON Korea highlight where industry leaders network — bringing together suppliers, customers, and innovation leaders.

For a complete schedule of technical sessions and events, visit http://www.semiconkorea.org/en/attend/program-sessions.

SEMICON Korea 2016 registration (www.semiconkorea.org/en) opens November 16. Complimentary registration includes access to the exhibition area and attendance of the keynote speeches.

While conventional thin film transistor liquid crystal (TFT LCD) displays are rapidly trending towards commoditization and currently suffering from declining prices and margins, China is quickly adding capacity in all flat-panel display (FPD) manufacturing segments. Supported by financial incentives from local governments, Chinese TFT capacity is projected to grow 40 percent per year between 2010 and 2018. In 2010 China accounted for just 4 percent of total TFT capacity. However by 2018, China is forecast to become the largest FPD-producing region in the world, accounting for 35 percent of the global market, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight.

While Chinese capacity expands, Japan, South Korea and Taiwan have restricted investments to focus mainly on advanced technologies. TFT capacity for flat panel display (FPD) production in these countries is forecast to grow on average at less than 2 percent per year between 2010 and 2018.

Based on the latest IHS Display Supply Demand & Equipment Tracker, BOE Technology Group stands out as the leading producer of FPDs in China. With a capacity growth rate of 44 percent per year between 2010 and 2018, BOE will become the main driver for Chinese share gains. By 2018, the company will have ramped up more FPD capacity than any other producers, except for LG Display and Samsung Display.

“Despite growing concerns of oversupply for the next several years in most parts of the display industry, there is still little evidence that Chinese makers are reconsidering or scaling back their ambitious expansion plans,” said Charles Annis, senior director at IHS. “On the contrary, there continues to be a steady stream of announcements of new factory plans by various regional governments and panel makers.”

In China, the central government has generally encouraged investment in FPDs, in order to shift the economy to higher technology manufacturing, to increase domestic supply and to support gross domestic product (GDP) growth. Provincial governments have become the main enabler of capacity expansion through product and technology subsidies, joint ventures and other direct investments, by providing land and facilities and through tax incentives. In return, new FPD fabs increase tax revenue, support land value appreciation, increase employment and spur the local economy. The economic benefits generated from the feedback loop between local governments, panel makers and new FPD factories are still considered sufficiently positive in China to warrant application of significant public resources.

“China currently produces only about a third of the FPD panels it consumes. However, by rapidly expanding capacity, panel makers and government officials are expecting to double domestic production rates in the next few years and are also looking to export markets,” Annis said. “How excessive global supply, falling prices and lower profitability will affect these plans over time is not yet exactly clear. Even so, there is now so much new capacity in the pipeline that China will almost certainly become the top producer of FPDs by 2018.”

The IHS Display Supply Demand & Equipment Tracker covers metrics used to evaluate supply, demand, and capital spending for all major FPD technologies and applications.

Systematic – and predictive – cost reduction in semiconductor equipment manufacturing

BY TOM MARIANO, Foliage, Burlington, MA

After a period of double-digit growth, the semiconductor equipment industry has now stabilized to the point where recent market forecasts are predicting anemic single-digit growth rates. This is driven by total market demand from chipmakers. For example, despite strong growth of 12.9 percent in 2014, Gartner, Inc. projects worldwide semiconductor capital spending to only grow 0.8 percent in 2015, to $65.7 billion. [1] Additionally, this industry has always been subject to volatile demand cycles that are notoriously difficult to predict.

Translation: It’s extremely challenging for today’s semiconductor equipment manufacturers to improve their financial performance. There are fewer and fewer opportunities to grow topline revenue through innovation and new product development. And, after several years of cutting costs on existing products and not realizing enough cost reduction to improve margins, it’s difficult to know how to do it differently.

Yet a viable alternative to improve financial performance does exist: A disciplined, rigorous, and systematic approach to reducing costs that delivers more predictive results.

A systematic approach to cost reduction

Where cutting costs was once perceived as the end result of “desperate times, desperate measures,” many innovators are now using this approach much more proactively. By
meeting the idea of cost reduction head on – as an opportunity, not a last resort – many semiconductor equipment makers are uncovering wasteful, inefficient, and costly processes, often in areas they once overlooked. At this point, you may be thinking, “All of this sounds great, but what is a systematic approach to cost reduction, and how is it different from what I’m doing?”

Remember that many manufacturers (in all industries) tend to have a hard time driving costs down. They may set cost reduction goals and then attempt to achieve them using various ad hoc approaches. But they really need to understand exactly what their true costs are, where they exist, and which areas will improve their margins.

A systematic approach to cost reduction gives them this insight. With improved visibility into the entire organization, various processes, and how they execute, semiconductor equipment manufacturers can’t identify the right places to cut costs and hit their cost savings goals. This is a very detailed and planned approach in which organizations closely examine areas such as cost of goods sold, R&D, and service to make more informed decisions that will position their business for long-term success. This is the value of a systematic approach to cost reduction.

This approach also introduces the element of speed, helping equipment makers realize cost savings much faster than ad hoc cost-cutting initiatives and puts them on a path to achieve more predictive results. Beyond the positive (and more obvious) impact successful cost reduction has on a semiconductor equipment manufacturer’s bottom line, it also provides a number of significant benefits such as improving productivity, freeing up key personnel, and providing needed capital to fuel new growth.

The path to predictive results

Even if the concept of a more strategic approach to cutting costs sounds reasonable, many semiconductor equipment manufacturers struggle with how to begin and where to focus. All to often they resort to making reactive decisions regarding existing products without the necessary data, leading them to ask questions such as, “Should we have an obsolescence plan for this product?” “How much could we save?” and “Will this lead to bigger problems down the road?”

Without understanding where your best opportunities for cost cutting are, it’s a lot larder to predict when, and if, cost reduction goals will be met. A systematic approach to cost reduction includes establishing clear cost targets, communicating them to leadership, and measuring and reporting results along the way.

The first step is to engage with an outside firm that has a singular focus on cost reduction, and one that is clearly separated from day-to-day operations and current organizational dynamics. Such an engagement will yield an actionable list of improvements with specific cost targets, realistic timelines for achieving these goals, and future plans for reinvesting the cost savings.

More specifically, a systematic cost reduction approach will focus on three key areas: material costs, R&D costs, and service costs:

1. Material costs: The bill of materials is one of the most common ways to see all the components needed to produce the end product. But this goes well beyond the pure cost of materials. Research has shown that improving the way these components are managed can affect 80-90% of the product’s total costs.[2]

For semiconductor equipment manufacturers, the cost reduction process should start with the selection of the products or sub-assemblies that have the highest potential for savings. Focus on those products that are still generating significant revenue, but may not be receiving much attention in terms or engineering upgrades and enhancements. Thoroughly examine the bill of materials for these products by addressing materials, design, complexity reduction, the potential to create common assemblies, and more.

Value engineering efforts can simultaneously improve product functionality and performance while reducing bill of material costs. This effort should factor in ways to meet RoHS requirements and when to make end-of-life decisions for various electrical components to improve design efficiency and the effectiveness of the product.

A realistic cost reduction goal can then be created and a resulting value-engineering project can commence, often using low-cost offshore resources to best achieve those savings.

2. R&D costs: Making better decisions related to R&D processes and product development can shave considerable costs. Some areas to focus on include:

• When to officially end of life non-performing products
• When to consolidate products, or possibly even entire R&D departments
• When and how to move sustaining engineering efforts offshore, or to other lower-cost alternatives

The critical next step is to look at all products and all product variations to determine if an official end-of-life program should be employed. These decisions are notoriously hard to make and often require difficult conversations with key customers, but they are necessary nonetheless.

Many semiconductor equipment manufacturers have grown through acquisitions, creating redundant engineering groups that can be eliminated or downsized. Performing an organizational analysis of all R&D activities may uncover opportunities to consolidate and combine functions or create centers of excellence that focus on specific technical areas eliminating redundancies of technical specialty.

3. Service costs: Examine engineering and design processes to find ways to improve performance, reliability, and costs. For example, adding data collection technology or product diagnostics to enhance remote support efforts and predictive maintenance.

Improvement of product reliability is usually a large multiplier when it comes to service and spare parts costs. Collect and analyze field data to find the most significant issues driving service costs and then look to cut where possible.

For example, equipment in the field often does not have the capability to report enough information to effectively identify a problem. Adding increased data logging and communication can be used to clarify machine status and point services in the right direction. Connectivity can also help with remote diagnostics, all of which helps reduce costs, uptime, and customer satisfaction.

Cost Reduction as a Competitive Advantage

Short-term market forecasts will continue to make it challenging for semiconductor equipment manufacturers to deliver improved financial results. Yet the concept of a systematic approach to cost reduction is a proven way for them to proactively cut costs – in the right places – and also make better decisions related to existing products and other business systems and processes.

By taking a disciplined, rigorous, and objective look at any and all parts of their organization, semiconductor equipment makers can capitalize on new opportunities to free valuable resources, improve processes and future technology, and reinvest savings for future growth. For many equipment manufacturers the greatest obstacle to successfully exploiting these opportunities is insufficient experience and expertise with a disciplined and unconventional way of approaching cost reduction projects. A systematic approach to cost reduction will be the key to success for companies looking to improve their competitive advantage.

References

1. Gartner, Inc., “Gartner Says Worldwide Semiconductor Capital Spending to Increase 0.8 Percent in 2015: Conser- vative Investment Strategies Paving the Way to Slower Growth in 2015,” January 13, 2015. http://www.gartner. com/newsroom/id/2961017.

2. Forbes, “Product Lifecycle Management: A New Path to Shareholder Value?” August 5, 2011, http://www. forbes.com/sites/ciocentral/2011/08/05/product-lifecycle- management-a-new-path-to-shareholder-value/.

Sapphire is hard, strong, optically transparent and chemically inert.

BY WINTHROP E. BAYLIES and CHRISTOPHER JL MOORE, BayTech-Resor LLC, Maynard, MA

Have you ever wondered what blue gemstone earrings, an LED lightbulb and an Apple Watch have in common? The answer (at least for this article) is that all depend on sapphire as part of their manufacturing process. In part 1 of the following two part article, we will discuss how sapphire is becoming an important part of the mobile device food chain. Part 2 will concentrate on how sapphire is used in LED production.

Sapphire (chemical composition Al2O3) has a high melting point of 2040°C (3704°F) and is chemically resistant even at high temperatures. It is an anisotropic material meaning that its mechanical/thermal properties depend on the direction of the crystal plane that is cut and polished. An insulator with a 9.2 eV energy gap it is optically transparent. With a hardness of 9 on the Mhos scale, it is almost as hard and strong as diamond (10 Mhos).

To summarize, sapphire has some good points: hard, strong, optically transparent and chemically inert (there is a reason high end watches use sapphire crystals) and some bad points: hard, strong, and chemically inert (which is why sapphire crystals are more expensive than glass). That is, the very properties that make it ideal for applications needing mechanical strength and hardness mean that it is a difficult material to grow, machine and polish.

There are several places where sapphire can be (or is now) used in the manufacture of mobile devices. The most publicity in this area was generated in 2014 with significant speculation in both the trade magazines and newspapers (such as the Wall Street Journal) that the iPhone 6 would be released with a sapphire touch screen or at the very least a sapphire cover glass over the existing touchscreen. Part of this speculation was fueled by the large number (1700 to 2500 depending on source) of sapphire producing furnaces being installed at an Apple facility in Mesa Arizona. However, the sapphire iPhone 6 was not released due in part to the difficulties in growing and processing enough sapphire screens at a reasonable cost to supply the significant number of phones produced. There are now sapphire touch screen phones available from other suppliers and recently, the Apple Watch was released with a sapphire screen. In addition, many fingerprint sensors and camera cover glasses are now produced using sapphire as the cover material.

Requirements for sapphire material is clear (forgive the pun). For screens and cameras, it must be of good optical quality i.e. transmit light well and have low surface roughness. For fingerprint sensors, it needs consistent surface quality and electrical properties.

Production process

FIGURE 1 shows a schematic of the production process for sapphire used in a mobile device screen. The following paragraphs provide more detail on this process [1] as well as a few of problems encountered along the way.

Sapphire Fig 1

The sapphire production process starts when a seed crystal and a mixture of aluminum oxide and crackle (un-crystallized sapphire material) is heated using a specific temperature/time profile, then cooled (this process can take two weeks depending on the amount of sapphire being produced) using a carefully controlled set of time/temperature profiles. When done correctly, the cookie sized seed grows and produces a single-crystal sapphire boule. That at least is the theory. In reality, two weeks is a long time and any number of problems can go wrong during this process including gas bubbles, mechanical faults such as cracks and contamination. Each of these problems can affect the sapphire and its optical/electrical properties. There is a clear correlation between the time taken to grow a boule and the potential quality of the boule produced. Many of the problems encountered in the upscaling of the sapphire production process sprang from trying to grow large boules at high speeds.

It is at the next step in the process where boule size does matter. Typically, the boule will be drilled or cut to produce material near the size needed for the particular application. It makes a significant difference if the material is for a watch crystal (say 1.5 inch diameter ~ 1.7 square inches). Here you can “core-drill” a boule to produce a number of smaller cylinders. For a phone screen/cover plate (at 4 by 6 inch i.e. 24 square inches) a larger portion of the boule is needed for a box shape. The ability to grow large sized boules on a regular basis is not in question; most important is how much of that boule is bubble-, crack- and impurity-free. In some cases the boules are inspected with various metrology techniques to determine which sections of the boule can be used and which cannot. The section of the boules not used is recycled into the original growth process (unless contaminated).

Given the hardness of the sapphire, diamond wire saws or diamond core drills are used for cutting or coring the boules. The yield from any boule is a function of the original boule size, the size of the cores or slabs being produced and the volume of the boule free from imperfections. As was discussed earlier, and is typical of many processes, the larger the size of the piece the lower the yield.

The next step is to take the cylindrical cores (or rectangular slabs) and cut them into appropriate sized pieces. The thickness of the desired part and the amount the producer is willing to invest in high technology solutions determines what is done next. On one end of the technology scale, the parts are cut using a wire saw or an abrasive cutoff saw. On the other end of the scale, you can ion implant the surface to produce a damaged layer at a depth below the surface determined by the original ion energy. If the slab is heated after sufficient implantation is done, a thin sheet will separate from the surface. Both processes result in parts of the approximate size needed for the application; a discussion of the pros and cons of each approach is beyond the scope of this article.

The process after this point depends on the parts’ final application and their manufacturer. Given the difficulty of polishing a material this hard many of the bigger companies have developed proprietary process for grinding or mechanically polishing the sapphire parts to the desired shape and surface roughness/finish. From a mechanical strength standpoint, it is important that there be no significant scratching of the surface or chipping of the edges which could severely limit the mechanical strength of the final piece. From an optical standpoint, it is important to produce a uniform finish so as not to effect the overall appearance of the part. At this stage, the parts are then ground to their final size and any additional shaping of the part including holes/ profiles is done. FIGURE 2 shows a variety of sapphire parts at this stage of the process.

Sapphire Fig 2

In most sapphire part production these parts are next coated with a variety of optical and/or electrical and/ or chemical films again depending on their application. Because of its high index of refraction (1.76) a sapphire screen or watch crystal is highly reflective. For this application, the parts are typically coated with a series of films to produce an anti-reflection coating enhancing final screen readability. For parts that will be touched on a regular basis such as touchscreens or fingerprint sensors coatings, it is important that they be “self-cleaning.” In these cases, hydrophobic and oleophobic coatings are used to make sure your fingerprints are less likely to stay behind after the material has been touched. FIGURE 3 shows a series of parts after the coating and silk screening process. They are now ready for assembly into the mobile device.

Sapphire Fig 3

The use of sapphire in mobile devices is driven by two main concerns. One is that the final screen/sensor be mechanically stronger and harder than most glasses. There are a number of videos [2] available showing cement blocks being dragged over cell phones to show the sapphire screens’ scratchproof capabilities. The second (and not as well known) factor is the significant data showing that touch sensors made using sapphire have better performance characteristics due to its superior electrical properties and electrical uniformity. This allows the development of sensors which have improved performance in the field.

The downside of using sapphire remains its cost. Estimates [3] have reported sapphire costs 2 to 10 times the price of an equivalent glass part. Although these costs are coming down, in price sensitive applications glass continues to dominate at this time and it is expected that only higher end phones will use sapphire screens.

In the second part of this article, we will discuss the importance of sapphire in the LED industry and the difference in process needed for this material.

Additional reading/viewing material

1. http://www.businessinsider.com/how-sapphire- glass-screens-are-made-2014-9
2. Video Aero Gear’s Flight Glass SX Sapphire Crystal vs a Concrete
3. http://seekingalpha.com/article/2230553-ignore- the-sapphire-threat-corning-is-on-a-roll