Yearly Archives: 2015

The availability of patterning alternatives in the lithography landscape represents a big opportunity to properly address the coming needs generated by the IoT.

BY LAURENT PAIN, RALUCA TIRON, LUDOVIC LATTARD, STEFAN LANDIS and CYRILLE LAVIRON, CEA-Leti, Grenoble, France

The Internet of Things (IoT) is expected to fuel significant growth opportunities for the semiconductor industry, as demand increases for wireless components and more and more embedded functionalities such as memory and sensors. This growth will affect almost all integrated circuit (IC) sectors (FIGURE 1). The chip industry will continue to need advanced technologies to provide the most powerful functionalized ICs with lower power consumption for the IoT, but manufacturing costs remain a key challenge. Lithography and related patterning technologies can represent up to 50 percent of total IC production costs, and significant efforts have to be made in the coming years to slow and even reverse this trend.

Litho Fig 1

In the lithography landscape for the development of advanced technology nodes, extreme-UV (EUV) lithography technology recovered some credibility at the beginning of 2015 with the release and installation of the first 80W power sources[1]. However, its adoption by the industry remains uncertain, because its infrastructure still requires significant development. Also, the recurrent questions about the real cost of ownership associated with the ability of the 0.33NA platform to address sub-7nm technology nodes continue to dominate the debate in the semiconductor community, especially since 3D-stacking strategies are being seriously investigated. This potentially could slow demand for high-resolution and therefore delay the new advanced lithography solutions.

Meanwhile, 193nm immersion lithography, with double- or quadruple-patterning strategies, supports the industry preference for advanced-node developments, despite the tremendous effort required for process controls (alignment, mask manufacturing etc.). In this landscape, lithography alternatives maintain promise for continued R&D because they may present competitive compromises for the industry. Massively parallel electron-beam and nano-imprint lithography techniques remain highly attractive, as they can provide noteworthy cost-of-ownership benefits for IC manufacturers. In addition, directed self-assembly (DSA) lithography with block copolymer shows promising resolution capabilities and appears to be an option to reduce multi-patterning strategies, and therefore the associated mask-set budgets. But what is the current status of these technologies? Are they really able to meet industry expectations for advanced technology nodes? Are they indeed able to reduce manufacturing costs? What are their introduction points into the production environment?

CEA-Leti is working to answer these questions and has initiated collaborative R&D programs to assess and boost the development of these alternative technologies through strategic partnerships. Three programs have been launched with the primary goals of demonstrating that these lithography options can meet industry needs, assessing industrial use of them and proposing to Leti’s IDM partners real turn-key integrated process-flow solutions.

  • IMAGINE: launched in 2009 with MAPPER Lithography, this program is pushing for the insertion of massively parallel direct-write electron-beam technology. Other participants include TSMC, STMicroelectronics, Nissan Chemical, Mentor Graphics, SCREEN, Tokyo Electron and Aselta Nanographics.
  • IDEAL: DSA lithography represents a promising solution for advanced patterning. Leti has worked with Arkema since 2011 on the qualification and demonstration of materials for insertion into industrial production flow. Other partners include ST, Tokyo Electron, SCREEN, Mentor Graphics and CNRS-LCPO.
  • INSPIRE: established in 2015 with the EV Group, this program will focus on the assessment of imprint technology on large-scale patterning.

Directed self assembly: the resolution is in polymer matrix

Since 2010, DSA has steadily attracted attention of R&D laboratories and the IDM industry. The natural high-resolution capability of the block copolymer (sub-10nm) may meet the requirements of future technology nodes. Significant work in this area is underway at R&D consortia such as imec, IBM Research in Albany, N.Y., and Leti, as well as directly in the fab[2,3]. For example, Leti and its partners put in place a full infrastructure to qualify the new material developed by the chemical company Arkema (FIGURE 2). A full 300mm line is operational at Leti using a Tokyo Electron track and a customized SCREEN DUO track able to handle the latest process possibilities. This type of infrastructure is required to validate in fab-like conditions the new materials (PS-PMMA and high chi platforms) and their associated integration flows. Those operating conditions give industry the capability to quickly evaluate the full process-flow performances with all the required classic statistical data for final validation.

Litho Fig 2

Focusing on defectivity Intel showed convincing data at 1def/cm2 on line-and-space structures, confirming the potential of DSA to reach the ITRS target and therefore to be used for manufacturing in the near future (FIGURE 3). As well, Leti results on grapho-epitaxy process are also very encouraging with zero visual-defect process flow for contact/via application measured with low statistical level[4]. Those results are the first positive key trends in the DSA technology. Evaluating the compatibility of DSA with semiconductor process flows is the next important step. The control of the iso-dense configuration focused a lot of attention on the grapho-epitaxy process, in which block copolymer film-filling uniformity is affected by the topography effects of the guide patterns. Leti developed and patented a flow allowing a proper control of CD and CDU in all density configurations. (FIGURE 4) This solution preserves the interest of DSA as it is integrated in the process flow itself and because it does not imply a need for any additional design-rule restriction[4].

Litho Fig 3

Nevertheless, some hurdles remain to be overcome before its final adoption. The control of the surface affinity is one key aspect. It can greatly affect the final defectivity level and impact the complexity of the integration flow (FIGURE 5). Any non-uniform control of the bottom residual polymer thickness in the bottom of the guide cavity may lead to post-etch opening issues and final circuit-yield drop. Moreover, to be fully adopted, DSA technology also must be aligned with the compatible design rule manuals. Insertion in the DRM is essential and it implies adding new specific constraints due to the nature of the block copolymer and to the lithography guide realization. All these R&D efforts must be pushed to value the advantages of DSA technology: the natural high resolution of this solution and its cost effectiveness from reducing multi-exposure strategy. In addition to ensuring DSA’s ability to extend 193nm immersion lithography,it also supports the use of the EUV 0.33NA tool for the development of 7nm nodes and below.

Litho Fig 4

Massively parallel electron-beam writing

Despite recurrent delays in new developments, parallel electron-beam lithography remains an attractive alternative option. The massively parallel writing solutions developed by MAPPER Lithography and IMS Nanofab-rication for wafer and mask writing, respectively, offer good compromises: a significant alliance of resolution and advantageous manufacturing costs. But this technology also benefits from additional advantages, such as writing flexibility and a significant throughput improvement due to the parallel exposure concept that can boost the throughput in the future up to 100 wafers per hour in a cluster-tool configuration. First pre-industrial units are today installed in pilot-line environments, foreshadowing their introduction into production lines in coming years.

MAPPER and Leti’s collaboration is focused on introducing this technology for direct-write application. This joint program started in 2009 around the MAPPER’s pre-alpha tool that validated the key concept of the MAPPER technology in terms of parallel writing and resolution capabilities (FIGURE 6). The partnership entered in a new phase in 2014 with the installation of the first FLX-1200 pre-production platform, (FIGURE 7), operating 1,300 beam lines for a targeted throughput of 1 wph and then scalable to 10 wph by increasing the beam line count up to 13,000.

Litho Fig 5 Litho Fig 6

This FLX-1200, which is being ramped up now, already has shown imaging performances that match its specifications. Full 300mm wafers can be printed in one hour with 32nm half-pitch resolution (FIGURE 8). In the IMAGINE program, Leti and its partners are also working to validate a complete turn-key integrated solution allowing fast and secure wafer processing from design to silicon. Such infrastructure developments around data treatment, materials, process, etch and metrology will be required to speed-up the insertion of the MAPPER technology into future production lines.

Litho Fig 7

Leti and MAPPER will demonstrate the operational capability of the FLX-1200 in its final configuration, including mix-and-match alignment performances. The achievement of this key demonstration milestone is essential to launching this technology. Then, after final ramp-up, the MAPPER platform is expected to be aligned in terms of specifications with 14nm technology (32nm hp). A wide range of potential applications based on its mask-less concept and throughput potential already have been clearly identified: CMOS prototyping and low-volume production, complementary lithography concept for high-end patterning[6], new industry segments (photonics, low-cost circuit functionalization, large field exposure, etc.).

Nano-imprint lithography

Nano-imprint lithography (NIL) stands out from the other conventional lithography processes (photo-lithography, electronic lithography, EUV lithography) because of the fundamental mechanism of creating the final structures. In the case of nano-imprint, the flow of the resist directly shapes the pattern through the stamp cavities, eliminating the need for chemical contrast, as is the case for optical lithography resists. In recent decades, significant efforts have been made to extend the distance between the photomask and the resist-coated wafer to reduce defectivity and enhance resolution. Therefore, for many scientists, NIL technology appeared to be a UFO, since the process is based on the intimate contact between the working stamp and the resist to be embossed.

In the past 20 years, significant progress has been made to make the technology more mature and ready for high-volume manufacturing. Among the several existing NIL technology alternatives, the UV-based imprint, using transparent stamp, is today the standard one. Two well-established options are now available on the market: the full-wafer imprint (the size of the stamp corresponds to the size of the wafer to be printed) and the step-and-flash imprint in which a small stamp (i.e. die size) is stepped, as in optical lithography across the wafer to be processed (FIGURE 9).

Litho Fig 8

If the step-and-flash NIL technology is better suited to address the semiconductor markets (NAND flash memory, DRAM and logic) with its high level-alignment capability and its good control of defectivity density[7], the full-wafer NIL option could quickly become the reference manufacturing option for the emerging and growing markets such as LED and photonics-based devices (FIGURE 10).

Litho Fig 9

However, this wafer-scale imprint solution still lacks quantitative data regarding its technology assessment for high-volume manufacturing. Commercial equipment[8] and resists, the cornerstones of this technology, are already available. But some links in the industrial supply chain (design rules, master manufacturing and repair, in-line defectivity and metrology controls, fully integrated process flows) still must be established and qualified to make this technology more mature.

To accelerate adoption of this technology, Leti and EV Group launched in June 2015 a new collaborative industrial program called INSPIRE, aimed at demonstrating the benefits of this full-wafer NIL technology and spreading its use for applications beyond the traditional semiconductor industry. Much more than a classic industrial partnership, the program is designed to support development of new applications from the feasibility-study stage up to the first manufacturing steps, including the prototyping phase in Leti’s clean room. INSPIRE is also designed to demonstrate the technology’s cost-of-ownership benefits for a wide range of application domains. The final objective of this program is to facilitate the transfer of the developed integrated process solutions to industrial partners. The steps should significantly lower the entry barrier for NIL technology and speed up its use in production lines.

Conclusion

The availability of patterning alternatives in the lithography landscape represents a big opportunity to properly address the coming needs generated by the IoT. Besides conventional optical lithography, they offer industry new and/or complementary advantages: innovation capability and opportunities to better manage cost of ownership. But not only that! The high-resolution potential, the ability to facilitate design-innovation validation, and the complementarity of these alternatives with other patterning solutions also highlight their strengths. The step now is to finalize the evaluation of these technologies with respect to industry standards and establish them as real and credible lithography alternatives.

References

1. A. Schafgans et al, Proc SPIE, Extreme Ultraviolet Lithography VI, Vol. 9422, 2015
2. S. Sayan et al, Proc. SPIE, Advances in Patterning Materials and Processes XXXII, Vol. 9425, 2015
3. H. Tsai et al, ACS nano, vol 8 (5), pp. 5227-5232, 2014
4. R. Tiron et al, Alternative Lithographic Technologies II, Vol. 9423, 2015

By Dr. Harry Zervos, Principal Analyst, IDTechEx

Flexible electronic devices are starting to experience significant proliferation, with more and more devices with innovative form factors being brought to market, from small components such as disposable sensors that have been in the market for quite some time now, all the way to new flexible smart phones currently being demonstrated by consumer electronics giants like Samsung and LG.

While printing technologies enable lower manufacturing costs and superior performance in many applications, vacuum deposition still claims significant market share in flexible electronics, although sometimes a combination of both can be the ideal combination.

From test strips to OLEDs 

Glucose test strips are a great example of the prevalence of both printed and vacuum deposited devices. Over ten billion test strips are being manufactured worldwide, in order to cater for the needs of the ever-increasing number of people living with diabetes. Although each manufacturer/brand has its own technology and design, the following cross-section shows the key parts of a test strip.  Manufacturers follow both thick film (screen printing) and thin film (sputtering) techniques for depositing the circuit in test strips, each of the techniques with its own merits.

Screen printing technology involves printing patterns of conductors and insulators onto the surface of planar solid (plastic or ceramic) substrates based on pressing the corresponding inks through a patterned mask. Each strip contains printed working and reference electrodes with the working one coated with the necessary reagents and membranes, with the reagents commonly dispensed by ink jet printing technology and deposited in the dry form. With thin film deposited electrodes, sputtering or laser ablation is commonly utilized. Lifescan for instance, a Johnson & Johnson company, mostly prints electrodes whereas Roche utilizes laser ablation in its Indianapolis plant. Along with the very specialized organic materials utilized in assays in the actively sensing part of the test strips, advanced devices integrating thin film technology utilize gold nanoparticles and mesoporous Pt electrodes, and even the use of carbon nanotubes and graphene has been demonstrated in certain designs.

OLED displays are a good example where the advent of printing techniques is meant to bring about much larger displays, manufactured at lower costs but for the time being, the OLED industry makes displays that are almost exclusively vacuum evaporated. Optimized solution processed materials are also becoming available but for now, vacuum deposited options perform better. Sunic, Aixtron, Canon Tokki and ULVAC are some of the companies that actively design and market equipment and materials for industrial vacuum technology in OLED applications.

Most of these companies, along with others such as Applied Materials are active in making more than just the active OLED layers, providing equipment for TFT deposition, encapsulation, etc.

The opportunity here is significant: The OLED market is meant to reach over $50bn in the next decade, with flexible and rigid plastic OLED displays surpassing 16 billion by 2020.

Flexible encapsulation & thin film PV

Encapsulation of flexible versions of OLED displays is set to become an exciting market: flexible barrier films – whether utilizing CVD or PVD processes or even in cases when ALD is utilized to make high quality, defect free layers- are hugely benefiting from vacuum deposition techniques and have created encapsulation materials that can reach the water vapor transmission rates required to allow flexible OLED displays the necessary lifetimes required to become commercially viable. Encapsulation for flexible OLED devices is a market that is expected to reach almost $340m by 2022 according to IDTechEx Research in the report “Barrier Layers for Flexible Electronics 2016-2026: Technologies, Markets, Forecasts”.

Flexible versions of thin film photovoltaics also require stringent encapsulation, but thin films have had harsh competition from low cost crystalline silicon cells from China, that have significantly reduced their market share in recent years. Just over 7% of the overall market for PV this year is expected to be thin-film based, according to research from SPV Research.

It is interesting to point out that manufacturing of all thin films for solar cell applications is fully vacuum based: PECVD for amorphous silicon platforms, sputtering or co-evaporation tends to be the preferred deposition techniques for CIGS technologies while CdTe leader First Solar has developed and optimized its own unique vacuum deposition technique, High Rate Vapor Transport Deposition (HRVTD). In this process, co-developed with NREL in an effort that started back in the early 1990’s, the material to be deposited is carried on a gas stream in powder form, then heated and vaporized as it passes through a membrane before depositing on a glass substrate. The technology can deposit a thin uniform layer of CdTe (or CdS, a common material system used as a buffer layer in CdTe cells) on 8 square feet of glass in less than 40 seconds, a deposition rate much higher than other rival thin film solar technologies that proved to be key in First Solar’s success in improving yield and output and consequently lower production costs for its thin film solar cells.

Conclusions 

The conclusion is simple: commercializing flexible or printed electronics will invariably require a deeper understanding of vacuum deposition technologies. Printing techniques are not the only manufacturing option that can allow for the freedom in design that the advent of flexibility in form factor is ushering in. In fact, vacuum deposition technologies are currently enabling the proliferation of a wide range of components and devices, from encapsulation films to thin flexible batteries to transparent conductive films and backplane elements. In many cases, having reached economies of scale, vacuum deposited devices have reached attractive cost structures that make it harder for printed versions to compete, having to “dig deep” in order to bring forward additional selling points than just reductions in cost.

Printed Electronics USA 2015 taking place in Santa Clara, CA on the 18th and 19th of November this year is going to focus on the importance of vacuum deposition, with both the conference as well as the trade show featuring contributions from end users, device manufacturers and manufacturing equipment suppliers of vacuum deposition technologies.

Worldwide silicon wafer area shipments decreased during the third quarter 2015 when compared to second quarter area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,591 million square inches during the most recent quarter, a 4.1 percent decrease from the record amount of 2,702 million square inches shipped during the previous quarter. New quarterly total area shipments were flat when compared to third quarter 2014 shipments.

“After two consecutive record breaking quarters, quarterly silicon shipment growth slightly declined,” said Ginji Yada, chairman of SEMI SMG and general manager, International Sales & Marketing Department of SUMCO Corporation. “Quarterly shipments for the most recent quarter are on par with the same quarter as last year, with total silicon shipment volumes for 2015 through the end of the third quarter higher relative to the same period last year.”

Quarterly Silicon* Area Shipment Trends

Million Square Inches

Q3-2014

Q2-2015

Q3-2015

9M-2014

9M-2015
Total

2,597

2,702

2,591

7,548

7,930

* Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

Security by design


November 13, 2015

Chowdary_Yanamadala-150x150By Chowdary Yanamadala, Senior Vice President of Business Development, ChaoLogix

The advent of Internet-connected devices, the so-called Internet of Things (IoT), offers myriad opportunities and significant risks. The pervasive collection and sharing of data by IoT devices constitutes the core value proposition for most IoT applications. However, it is our collective responsibility, as an industry, to secure the transport and storage of the data. Failing to properly secure the data risks turning the digital threat into a physical threat.  

Properly securing IoT systems requires layering security solutions. Data must be secured at both the network and hardware level. As a hardware example, let’s concentrate, on the embedded security implemented by semiconductor chips.

Authentication and encryption are the two main crypto functions utilized to ensure data security. With the mathematical security of the standardized algorithms (such as AES, ECDSA, SHA512, etc.) is intact, hackers often exploit the implementation defects to compromise the inherent security provided by the algorithms.

One of the most dangerous and immediate threats to data security is a category of attacks called Side Chanel Analysis attacks (SCA). SCA attacks exploit the power consumption signature during the execution of the crypto algorithms. This type of attack is called Differential Power Analysis (DPA). Another potent attack form of SCA is exploiting the Electromagnetic emanations that are occurring during the execution of the crypto algorithm – or Differential Electromagnetic Analysis attacks (DEMA).

Both DPA and DEMA attacks rely on the fact that sensitive data, such as secret keys, leaks via the power signature (or EM signature) during execution of the crypto algorithm.

DPA and DEMA attacks are especially dangerous, not only because of their effectiveness in exploiting security vulnerabilities but also due the low cost of the equipment required for the attack. An attacker can carry out DPA attacks against most security chips using equipment costing less than $2,000.

There are two fundamental ways to solve the threat of DPA and DEMA. One approach is to address the symptoms of the problem. This involves adding significant noise to the power signature in order to obfuscate the sensitive data leakage. This is an effective technique.  However, it is an ad-hoc and temporary measure against a potent threat to data security. Chip manufacturers can also apply this technique as a security patch, or afterthought, once  and architecture work is completed.

Another way (and arguably a much better way) to solve the threat of DPA is to address the problem at the source. The source of the threat derives from the leakage of sensitive data the form of power signature variations. The power signature captured during the crypto execution is dependent on the secret key that is processed during the crypto execution. This makes the power signature indicative of the secret key.

What if we address the problem by minimizing the relation between the power signature and the secret key that is used for crypto computation? Wouldn’t this offer a superior security? Doesn’t addressing the problem at the source provide more fundamental security? And arguably a more permanent security solution?

Data security experts call this Security By Design. It is obvious that solving a problem at the source is a fundamentally better approach than providing symptomatic relief to the problems. This is true in the case of data security as well. In order to achieve the solution (against the threat of DPA and DEMA) at the source, chip designers and architects need to build the security into the architecture.

Security needs to be a deliberate design specification and needs to be worked into the fabric of the design. Encouragingly, more and more chip designers are moving away from addressing security as an afterthought and embracing security by design.

As an industry, we design chips for performance, power, yield and testability. Now it is time to start designing for security. This is especially true for chips used in IoT applications. These chips tend to be small, have limited computational power and under tight cost constraints. It is, therefore, difficult, and in some cases impossible, to apply security patches as an afterthought. The sound approach is to start weaving security into the building blocks of these chips.

In sum, designing security into a chip is as much about methodology as it is about acquiring various technology and tools. As IoT applications expand and the corresponding demand for inherently secure chips grows, getting this methodology right will be a key to successful deployment of secure IoT systems.

Related data security articles: 

Security should not be hard to implement

ChaoLogix introduces ChaoSecure technology to boost semiconductor chip security

From laptops and televisions to smartphones and tablets, semiconductors have made advanced electronics possible. These types of devices are so pervasive, in fact, that Northwestern Engineering’s Matthew Grayson says we are living in the “Semiconductor Age.”

“You have all these great applications like computer chips, lasers, and camera imagers,” said Grayson, associate professor of electrical engineering and computer science in Northwestern’s McCormick School of Engineering. “There are so many applications for semiconductor materials, so it’s important that we can characterize these materials carefully and accurately. Non-uniform semiconductors lead to computer chips that fail, lasers that burn out, and imagers with dark spots.”

Grayson’s research team has created a new mathematical method that has made semiconductor characterization more efficient, more precise, and simpler. By flipping the magnetic field and repeating one measurement, the method can quantify whether or not electrical conductivity is uniform across the entire material – a quality required for high-performance semiconductors.

“Up until now, everyone would take separate pieces of the material, measure each piece, and compare differences to quantify non-uniformity,” Grayson said. “That means you need more time to make several different measurements and extra material dedicated for diagnostics. We have figured out how to measure a single piece of material in a magnetic field while flipping the polarity to deduce the average variation in the density of electrons across the sample.”

Remarkably, the contacts at the edge of the sample reveal information about the variations happening throughout the body of the sample.

Supported by funding from the Air Force’s Office of Scientific Research, Grayson’s research was published on October 28 online in the journal Physical Review Letters. Graduate student Wang Zhou is first author of the paper.

One reason semiconductors have so many applications is because researchers and manufacturers can control their properties. By adding impurities to the material, researchers can modulate the semiconductor’s electrical properties. The trick is making sure that the material is uniformly modulated so that every part of the material performs equally well. Grayson’s technique allows researchers and manufacturers to directly quantify such non-uniformities.

“When people see non-uniform behavior, sometimes they just throw out the material to find a better piece,” Grayson said. “With our information, you can find a piece of the material that’s more uniform and can still be used. Or you can use the information to figure out how to balance out the next sample.”

Grayson’s method can be applied to samples as large as a 12-inch wafer or as small as an exfoliated 10-micron flake, allowing researchers to profile the subtleties in a wide range of semiconductor samples. The method is especially useful for 2-D materials, such as graphene, which are too small for researchers to make several measurements across the surface.

Grayson has filed a patent on the method, and he hopes the new technique will find use in academic laboratories and industry.

“There are companies that mass produce semiconductors and need to know if the material is uniform before they start making individual computer chips,” Grayson said. “Our method will give them better feedback during sample preparation. We believe this is a fundamental breakthrough with broad impact.”

By Dr. Lianfeng YangLianfeng Yang, Vice President of Marketing, ProPlus Design Solutions, Inc.

The squeaky wheel gets the grease, or so it seems in the semiconductor industry, as the high level of the design process seems to get the most attention. Meanwhile, the transistor level appears to have been largely forgotten.

With increasing complexities and scale of electronic system, design and verification have moved up the abstraction level from register transfer level (RTL) to the electronic system level (ESL) with help from high-level synthesis software and other new EDA technologies. Portable stimulus is available at ESL to test specifications and virtual platforms enable early software consideration, for example.

Throughout, transistor-level challenges are ongoing but appear to be largely forgotten. New process technologies, such as FinFET, increasingly stress transistor-level verification tools, in particular, SPICE and FastSPICE simulators, and designer needs are greater. Highly accurate and reliable verification and sign-off tools for large post-layout simulation is one of many.

When designers move to 16/14 nanometer and beyond with FinFETs, accuracy is a priority and essential for characterization, verification and signoff, due to reduced Vdd and the impact of process variations. Device characteristics and physical behavior is more complicated with these process nodes. Circuit size is increasing and design margins are shrinking. Every aspect that contributes to leakage and power must be measured and accurately modeled. The entire circuit, including all parasitic components, has to be simulated accurately.

While circuit designers may not be squeaky wheels, they do need to be confident of their designs, as they’re under the pressure from ever-increasing design and manufacturing complexities and cost. FastSPICE simulators used in final verification and signoff do not offer enough accuracy. This is true for small currents critical to low-power design and achieving sufficient noise margins. Often, FastSPICE simulations rely on special, fine-tuned options and start with non-converged DC, further challenging accuracy.

Designers use FastSPICE to verify timing and power before tapeout. Unfortunately, they can’t be sure of the results, risk expensive respins and missing market windows, for applications sensitive to small current or noise elements, such as advanced memory designs. This is an all-too-familiar scenario where wheels should be squeaking.

What sends the situation out of control is FastSPICE’s lack of a golden to refer. FastSPICE provides many options for designer to tune to trade-off accuracy and speed, which worked in past generations. Such an option tuning strategy, however, becomes unreliable for advanced designs where designers have much less design margin than before. Designers now see more and more failure or inaccurate cases due to fundamental accuracy limitations of FastSPICE.

Traditional SPICE simulators were the “golden” simulator to validate FastSPICE, but only for small blocks as no commercially available SPICE simulator can offer simulation capacity for verification and signoff that FastSPICE used. And such validation can’t automatically scale up. The circuit size continues to increase and giga-scale designs are common. At 16nm and beyond, 3D device structures add greater capacity and accuracy challenges. FastSPICE simply doesn’t offer enough confidence and may introduce unpredictably inaccurate or wrong verification results, which designers don’t want to risk for tapeout.

Well, circuit designers may not be squeaking, but help is on the way nevertheless. A new type of SPICE simulator known as giga-scale SPICE simulators or GigaSpice, is able to support giga-scale circuit simulation and verification with a pure SPICE engine. It features SPICE accuracy and FastSPICE-like capacity and performance through advanced parallelization technology. It does not require option tuning and always converges on DC, making it easy for designers to adopt and offering accurate and reliable results for designers. GigaSpice can be a golden reference for FastSPICE and a replacement for memory characterization, large block simulation and full-chip verification.

The squeaky wheel may be noisy, but a few clever developers have been paying attention to the new developments for transistor-level verification and signoff and are responding.Giga-scale SPICE simulators are fast becoming part of circuit-level design flows for squeaky wheel results.

Dr. Lianfeng Yang currently serves as the ProPlus Design Solutions’ vice president of marketing and general manager of Beijing R&D Center. Previously, he was a senior product engineer leading the efforts on product engineering and technical support for the modeling product line to Asian customers at Cadence Design Systems, Inc. Dr. Yang holds a Ph.D. degree in Electrical Engineering from the University of Glasgow, UK.

SAN JOSE, Calif. — Nov. 11, 2015 — Ultratech, Inc., a supplier of lithography, laser-processing and inspection systems used to manufacture semiconductor devices and high-brightness LEDs (HB-LEDs), as well as atomic layer deposition (ALD) systems, today introduced the Superfast 4G+  in-line, 3D topography inspection system. Ultratech’s new 4G+ system builds on the field leadership of the Superfast 4G, providing the industry’s highest-productivity and lowest-cost solution for high-volume manufacturing. The Superfast 4G+ system’s patented coherent gradient sensing (CGS) technology enables Ultratech customers to use a single type of wafer inspection tool to measure patterned wafers across the entire fab line at the lowest cost. Ultratech plans to begin shipping the Superfast 4G+ systems in the first quarter of 2016.

Superfast 4G+ features include:

  • Direct, front-side 3D topography measurement for opaque and transparent stacks patterned wafers
  • 150 wph, the highest industry 3D in-line inspection throughput with the smallest footprint
  • 1-mm edge exclusion enabling full-wafer pattern inspection and thin-film 3D process control
  • Large bow option for in-line manufacturing control of highly bowed wafers without impacting throughput

Damon Tsai, Ultratech Asia Director for Inspection Systems, said, “Our current leadership position in in-line 3D inspection at advanced memory and foundry manufacturers with Superfast 4G has provided us with a tremendous learning environment. Our partners have helped us develop new hardware capabilities like the ‘Recipe Driven Range Control,’ an innovative high-throughput, large bow optical option on board the Superfast 4G+, as well as new fleet management performance metrics. The inherently simple design of the CGS technology is enabling us to rapidly deliver new capabilities and performance improvements over more complex optical solutions.”

Based on patented CGS technology, Ultratech’s Superfast 4G+ inspection system provides the industry’s highest throughput (150 wph) with the lowest cost-of-ownership compared to competing systems. The direct, front-side 3D topography measurement capability is well-suited for patterned wafer applications such as lithography feed-forward overlay distortion and edge-defocus control as well as thin-film deposition stress and planarization control. Delivering a 2X improvement in performance with fleet matching TMU (Total Measurement Uncertainty), along with the ability to measure opaque and transparent stacks on patterned wafers, the Superfast 4G+  provides cost-effective technology to address the critical needs of its global customers. In addition, leveraging the same breakthrough CGS optical module, the Superfast 4G+ is available as a field upgrade of the Superfast 4G.

Santa Clara, Calif. — November 11, 2015 — GLOBALFOUNDRIES today announced the availability of FX-14, an application-specific integrated circuit (ASIC) offering built on the company’s next-generation 14nm FinFET process technology. The GLOBALFOUNDRIES FX-14 ASIC offering is an ideal solution for customers seeking to strike a balance between high bandwidth, low power, and cost for cloud networking, wireless base station, compute, and storage applications.

With the recent acquisition of IBM’s Microelectronics Division, the FX-14 ASIC offering combines GLOBALFOUNDRIES’ manufacturing scale and process technology leadership with a legacy of ASIC expertise that has helped customers bring some of the industry’s most complex ASICs to market. Using GLOBALFOUNDRIES’ 14LPP process technology, FX-14 leverages the production-proven 14nm FinFET platform from the company’s Fab 8 facility in Saratoga County, NY.

“In order to enable extremely high-speed connectivity solutions for a wide range of networking applications, we require ASIC solutions that provide an optimal balance of performance, power and cost,” said Kianoosh Naghshineh, CEO, Chelsio Communications, Inc. “The combination of the recently acquired IBM ASIC design expertise and GLOBALFOUNDRIES’ 14LPP technology enables Chelsio to continue to push the price-performance curve and deliver industry-leading solutions to our customers.”

“The FX-14 ASIC offering continues to extend our leadership in delivering the most advanced ASIC solutions for the wired and wireless networking infrastructure,” said Mike Cadigan, senior vice president of product management at GLOBALFOUNDRIES. “Coupling the legacy of strong ASIC expertise with GLOBALFOUNDRIES’ 14LPP technology provides our customers the best combination to differentiate and stay ahead of evolving marketplace demands.”

The FX-14 ASIC offering includes an enhanced, optimized intellectual property (IP) portfolio, featuring leading-edge ARM cores and ARM® Artisan® physical IP. The broad lineup of cores for system-on-chip designs include 64-bit ARM Cortex®-A72 and ARM Cortex-A53 processors.

“The industry-leading ARM processors that power more than 95% percent of the smartphones shipping today are an ideal complement to GLOBALFOUNDRIES’ FX-14 ASIC offering,” said James McNiven, general manager, CPU group, ARM. “Our latest collaboration efforts with GLOBALFOUNDRIES on the FX-14 ASIC offering will further enable our mutual silicon partners to deliver highly-advanced SoCs.”

The FX-14 offering also delivers an optimized IP portfolio including High Speed Serdes (HSS) solutions. The HSS solutions range from the best in class architecture for high performance 56G backplane and chip-to-chip designs to optimized 30G and 16G SERDES designs covering a broad range of interface standards. GLOBALFOUNDRIES’ embedded memory solutions include ternary content-addressable memory (TCAM), capable of billions of searches per second as well as high density and high performance memory compilers. These memory compilers exploit the industry’s smallest memory cell to achieve outstanding SRAM density as well as take advantage of a performance-tuned memory cell to achieve the best in class performance.

GLOBALFOUNDRIES’ 14LPP technology offering was qualified in the third quarter of 2015 and is on track for volume production in 2016. FX-14 design kits are available to customers now.

 

Baltimore, MD — November 11, 2015 — Pixelligent, a leader in high-index advanced materials, today launched a new family of PixClear® materials for display and optical components and films. The PixClear product line is now available in a new solvent system — a low boiling ethyl acetate (ETA) — that delivers the same high performance while easing integration with customer manufacturing processes. Now leading manufacturing companies will have the choice of a standard, high boiling propylene glycol methyl ether acetate (PGMEA) or the low boiling ETA for their testing. These materials are available in both 20 percent and 50 percent loadings for PixClear PG and PixClear PB.

“The launch of our new PixClear ETA materials is a response to customer demand. These low boiling ETA dispersions will result in brighter, clearer devices produced at a lower cost, which directly supports reducing time to innovation for our customers in the display and adhesives space,” said Craig Bandes, President and CEO of Pixelligent. “At Pixelligent, we continue to expand our matrix of high quality, high-index nanomaterials in order to support the growth of our customers.” Matt Healy, Vice President of Product Management adds, “In August, we launched a full OLED materials family, which includes four products for testing internal light extraction structures for OLED lighting. All totaled, we have introduced 12 new products for customer testing in the past three months.”

PixClear zirconia dispersions are now available for order in two solvents, and at two different loadings, to complement the processes used for the production of displays and optical components.

Gartner, Inc. forecasts that 6.4 billion connected things will be in use worldwide in 2016, up 30 percent from 2015, and will reach 20.8 billion by 2020. In 2016, 5.5 million new things will get connected every day.

Gartner estimates that the Internet of Things (IoT) will support total services spending of $235 billion in 2016, up 22 percent from 2015. Services are dominated by the professional category (in which businesses contract with external providers in order to design, install and operate IoT systems), however connectivity services (through communications service providers) and consumer services will grow at a faster pace.

“IoT services are the real driver of value in IoT, and increasing attention is being focused on new services by end-user organizations and vendors,” said Jim Tully, vice president and distinguished analyst at Gartner.

Enterprises to Bolster IoT Revenue

“Aside from connected cars, consumer uses will continue to account for the greatest number of connected things, while enterprise will account for the largest spending,” said Mr. Tully. Gartner estimates that 4 billion connected things will be in use in the consumer sector in 2016, and will reach 13.5 billion in 2020 (see Table 1).

Table 1: Internet of Things Units Installed Base by Category (Millions of Units)

Category 2014 2015 2016 2020
Consumer 2,277 3,023 4,024 13,509
Business: Cross-Industry 632 815 1,092 4,408
Business: Vertical-Specific 898 1,065 1,276 2,880
Grand Total 3,807 4,902 6,392 20,797

Source: Gartner (November 2015)

In terms of hardware spending, consumer applications will amount to $546 billion in 2016, while the use of connected things in the enterprise will drive $868 billion in 2016 (see Table 2).

Table 2: Internet of Things Endpoint Spending by Category (Billions of Dollars)

Category 2014 2015 2016 2020
Consumer 257 416 546 1,534
Business: Cross-Industry 115 155 201 566
Business: Vertical-Specific 567 612 667 911
Grand Total 939 1,183 1,414 3,010

Source: Gartner (November 2015)

In the enterprise, Gartner considers two classes of connected things. The first class consists of generic or cross-industry devices that are used in multiple industries, and vertical-specific devices that are found in particular industries.

Cross-industry devices include connected light bulbs, HVAC and building management systems that are mainly deployed for purposes of cost saving. The second class includes vertical-specific devices, such as specialized equipment used in hospital operating theatres, tracking devices in container ships, and many others.

“Connected things for specialized use are currently the largest category, however, this is quickly changing with the increased use of generic devices. By 2020, cross-industry devices will dominate the number of connected things used in the enterprise,” said Mr. Tully.