Yearly Archives: 2015

ORBOTECH LTD. today announced that SPTS Technologies, an Orbotech company and a supplier of advanced wafer processing solutions for the global semiconductor and related industries, has supplied CEA-Leti, one of Europe’s largest micro- and nanotechnologies research institutes, with its vapor HF etch release systems for 300mm microelectromechanical systems (MEMS) on CMOS development. Installed in 2015 at CEA-Leti’s facility in Grenoble, France, the Monarch300 joins the 200 and 300mm etch, CVD and PVD systems previously supplied by SPTS and which are already operational in CEA-Leti’s MEMS and packaging lines.

“The co-integration of MEMS and CMOS has the potential to create a new family of sensors with improved performance,” said Kevin Crofton, President of SPTS and Corporate Vice President at Orbotech. “The Monarch 300 uses our patented Primaxx vapor HF etch technology and is capable of processing thirteen 300mm wafers simultaneously. NEMS and MEMS are at the core of CEA-Leti’s activities, and we are pleased to be able to supply this highly valued partner with additional capability to support its 300mm MEMS program.”

Marie-Noëlle Semeria, CEO of Leti and President of the Nanoelec RTI board, commented: “MEMS devices co-integrated with CMOS help Leti achieve a long-standing goal of enabling smaller and more powerful sensors and actuators, without exceeding power budgets.”

“After characterizing the performance of a number of competing vapor HF etch methodologies, we selected SPTS’ Primaxx reduced-pressure, dry technology because it extends our existing process capability significantly and offers enhanced compatibility with materials of interest. Leti intends to lead the way in developing MEMS devices on 300mm formats, and to achieve this we are partnering with industry leaders such as SPTS, who have the specialist process knowledge needed to transfer our 300mm MEMS developments to high-volume production,” added Fabrice Geiger, Head of the Silicon Technologies Division of CEA-Leti.

SPTS and CEA-Leti entered into a two-year agreement that will encompass full performance characterization and process optimization of both the 200mm and 300mm vapor HF process modules. This collaboration will further extend the long-standing relationship between these partners who already collaborate on the development and optimization of a range of etch and deposition processes for next-generation 3D high-aspect-ratio through-silicon-via (TSV) solutions.

Between 2015 and 2019, worldwide systems revenues for applications connecting to the Internet of Things will nearly double, reaching $124.5 billion in the final year of this decade, according to IC Insights’ new 2016 edition of its IC Market Drivers report.  During that same timeframe, new connections to the Internet of Things (IoT) will grow from about 1.7 billion in 2015 to nearly 3.1 billion in 2019 (Figure 1), based on the forecast in the new 450-page report, which examines emerging and major end-use applications fueling demand for ICs.

Figure 1

Figure 1

The new IC Market Drivers report shows about 30.0 billion Internet connections are expected to be in place worldwide in 2020, with 85% of those attachments being to web-enabled “things”—meaning a wide range of commercial, industrial, and consumer systems, distributed sensors, vehicles, and other connected objects—and 15% for electronics used by humans to communicate, download and receive streams of data files, and search for online information.  It was the opposite of that in 2000, with 85% of 488 million Internet connections providing human users with online access to the World Wide Web and the remaining 15% serving embedded systems, remote sensing and measurements, control, and machine-to-machine communications.

Strong double-digit increases in the Internet of Things market will drive up IC sales in IoT applications by a compound annual growth rate (CAGR) of 15.9% between 2015 and 2019 to about $19.4 billion in the final year of this decade (Figure 2), according to the new report.  IoT applications will also fuel strong sales growth in optoelectronics, sensors/actuators, and discrete semiconductors (O-S-D), which are projected to rise by a CAGR of 26.0% between 2015 and 2019 to $11.6 billion in four years.  The new IC Market Drivers report shows microcontrollers and system-on-chip microprocessors topping integrated circuit sales growth with a CAGR of 22.3% in the next four years, followed by memories at 19.8%, application specific standard products (ASSPs) at 16.4%, and analog ICs at an annual growth rate of 12.7%.

Figure 2

Figure 2

In the 2014-2019 forecast period of the IC Market Drivers report, wearable systems are projected to be the fastest growing IoT application with sales increasing by a CAGR of 59.0%, thanks in great part to a 440% surge in 2015 due to the launch of Apple’s first smartwatches in 2Q15.  Sales of IoT-connected wearable systems are expected to reach $15.2 billion in 2019 compared to $1.5 billion in 2014 and about $8.1 billion in 2015.

Meanwhile, connected vehicles (passenger cars and light trucks) are expected to be the second fastest market category for IoT technology with revenues growing by a CAGR of 31.5% between 2014 and 2019 to $5.3 billion in the final year of this decade.

At last week’s IEEE International Electron Devices Meeting 2015, nanoelectronics research center imec, KU Leuven, and Neuro-Electronics Research Flanders (NERF, set up by VIB/KU Leuven and imec) presented a set of silicon neural probes that combine 12 monolithically integrated optrodes using a CMOS compatible process. The probes enable optical stimulation and electronic detection of individual neurons, based on optogenetics techniques. They pave the way to a greater understanding of the brain and towards novel treatments for brain disorders such as Alzheimer’s, schizophrenia, autism, and epilepsy.

The enormous burden that brain disorders pose on affected individuals and health care systems calls for new ways to prevent, treat and cure these diseases. Currently available devices for recording neural activity to study the functioning of the brain typically have a limited number of electrical channels. Additionally, the brain is composed of many genetically and functionally distinct neuron types, and conventional probes cannot disambiguate recorded electrical signals with respect to their source. Imec’s and KU Leuven’s novel neural probes tackle these challenges, set a path towards greater understanding of the brain, and enable novel treatment options for brain disorders.

Imec’s and KU Leuven’s novel probes combine electronics and photonics to perform extremely sensitive measurements. The fully integrated implantable neural microsystems have advanced capabilities to detect, process and interpret neural data at a cellular scale. The systems feature a very high density of electrodes and nanophotonic circuits (optrodes). Such optrodes are used to optically stimulate single neurons using optogenetics, a technology in which neurons are genetically modified to make them light-sensitive and thus susceptible to stimulation through light pulses.

This research is supported by the Agency for Innovation by Science and Technology in Flanders (IWT) through the OptoBrain project.

Probe tip with activated light output

Probe tip with activated light output

CVD Source Materials


December 17, 2015

Reaction materials for chemical vapor deposition (CVD) and atomic layer deposition (ALD) are typically delivered into the chamber in a gaseous form. CVD polycrystalline silicon, for example, is deposited from trichlorosilane (SiHCl3) or silane (SiH4), using the following reactions:

SiH3Cl → Si + H2 + HCl
SiH4 → Si + 2 H2

This reaction is usually performed in LPCVD systems, with either pure silane feedstock, or a solution of silane with 70–80% nitrogen. Polysilicon may be grown directly with doping, if gases such as phosphine, arsine or diborane are added to the CVD chamber.

Silicon dioxide (usually called simply “oxide” in the semiconductor industry) may be deposited by several different processes. Common source gases include silane and oxygen, dichlorosilane (SiCl2H2) and nitrous oxide (N2O), or tetraethylorthosilicate (TEOS; Si(OC2H5)4). The reactions are as follows:

SiH4 + O2 → SiO2 + 2 H2
SiCl2H2 + 2 N2O → SiO2 + 2 N2 + 2 HCl
Si(OC2H5)4 → SiO2 + byproducts

CVD source materials are typically gases, such as silane and nitrogen, but can also be liquids: There are now a larger variety of liquid sources used in the semiconductor, FPD and PV manufacturing processes.

CVD Sources

The graph above shows the different possible states of matter. There are two ways to get from a liquid to a gaseous state. The first method involves increasing the temperature while holding the pressure steady, as indicated by the arrow with the broken line. This method is commonly used in everyday settings—to boil water and convert it to steam, for example. Heating a liquid takes time, however, which makes rapid vaporization difficult. On the other hand, one can also heat the liquid in advance and then abruptly reduce the pressure, as illustrated by the arrow with the solid line. The pressure in the vaporization section of the injector can be reduced instantaneously, and this makes it possible to vaporize a liquid source instantaneously.

Wafer level packaging (WLP) using fan-out technology is an attractive platform for achieving low-cost low-profile package solutions for smart-phones and tablets, which require cost-effective, high-density interconnects in small form-factor packaging.

It was originally introduced by Infineon in the fall of 2007. Called eWLB, or embedded wafer-level ball grid array technology, it enables all operations to be performed highly parallel at wafer level. In August of 2008, STMicroelectronics, STATS ChipPAC, and Infineon signed an agreement to jointly develop the next-generation eWLB, based on Infineon’s first-generation technology.

Assembled directly on a silicon wafer, the approach is unconstrained by die size, providing the design flexibility to accommodate an unlimited number of interconnects between the package and the application board for maximum connection density, finer line/spacing, improved electrical and thermal performance and small package dimensions to meet the relentless form factor requirements and performance demands of the mobile market.

STATS ChipPAC’s eWLB high volume manufacturing process, for example, today includes automated wafer reconstitution (including wafer-level molding), redistribution using thin film technology, solder ball mount, package singulation and testing. Incoming wafers in both 200mm and 300mm diameters can be supported.

According to a recent report from Yole Développement, the fan-out WLP (FOWLP) market will reach almost $200M in 2015, with 30% CAGR in the coming years. Yole analysts say FOWLP started volume commercialization in 2009/2010 and started promisingly, with an initial push by Intel Mobile. However, it was limited to a narrow range of applications, essentially single die packages for cell phone baseband chips. In 2012 big fabless wireless/mobile players started slowly volume production after qualifying the technology.

The movement of charge carriers perpendicular to an electric driving field – even without a magnetic field – constitutes one of the most intriguing properties of carriers in solids. This anomalous velocity is at the origin of fascinating physical phenomena – with the spin Hall effect and the anomalous Hall effect being two prominent examples – and might be important for future spintronic applications or even new quantum computers. At the Physikalisch-Technische Bundesansstalt (PTB), the German National Metrology Institute, researchers have now succeeded in detecting the anomalous velocity in a semiconductor made of GaAs with a sub-picosecond time resolution. On the one hand, this work gives new insight into the microscopic origins of the anomalous velocity. On the other hand, it opens a new area of research for studying important physical effects on ultrafast time scales. The results have been published in the present issue of the renowned journal Physical Review Letters.

The anomalous velocity has different microscopic origins; one typically distinguishes between intrinsic and extrinsic contributions. The intrinsic contribution depends on the intrinsic properties of the solid (i.e. on the so-called Berry curvature), while the extrinsic contribution is caused by carrier scattering. Despite intensive investigations of the anomalous velocity in the past years, no simple technique has been developed which would enable the distinction between intrinsic and extrinsic contributions in a straightforward way. Moreover, the anomalous velocity has not yet been studied on ultrafast time scales on which factors such as coherent effects might significantly influence the anomalous velocity.

At PTB, the anomalous velocity has now, for the first time, been detected with sub-picosecond time resolution. For this purpose a semiconductor made of GaAs was excited by means of an optical femtosecond laser and a pulsed high-frequency electric field. While the optical laser pulse excites carriers with a particular spin direction, the high-frequency field accelerates these carriers. During this process, the carriers gain not only a velocity parallel to the electric field, but also the anomalous velocity perpendicular to it. This velocity was detected by a time-resolved study of the electromagnetic radiation emitted from the sample.

The PTB researchers have shown that the time-resolved detection of the anomalous velocity is very important for its further understanding. On the one hand, such investigations enable the distinction between intrinsic and extrinsic contributions, since these contributions have different time-domain shapes. On the other hand, it is now possible to investigate the dependence of the anomalous velocity on the momentum and energy of the carriers involved which, in turn, allows new studies of other important physical phenomena.

Topological insulators are materials that let electric current flow across their surface while keeping it from passing it through their bulk. This exotic property makes topological insulators very promising for electricity with less energy loss, spintronics, and perhaps even quantum computing. EPFL scientists have now identified a new class of topological insulators, and have discovered its first representative material, which could propel topological insulators into applications. The work, which was carried out within the framework of the EPFL-led NCCR Marvel project, is published in Nature Materials.

The technological promise of topological insulators has led to an intense search for optimal natural and man-made materials with such properties. Such research combines theoretical work that predicts what properties the structure of a particular material would have. The “candidate” materials that are identified with computer simulations are then passed for experimental examination to see if their topological insulating properties match the theoretical predictions.

This is what the lab of Oleg Yazyev at EPFL’s Institute of Theoretical Physics has accomplished, working with experimentalist colleagues from around the world. By theoretically testing potential candidates from the database of previously described materials, the team has identified a material, described as a “crystalline phase” of bismuth iodide, as the first of a new class of topological insulators.

What makes this material particularly exciting is the fact that its atomic structure does not resemble any other topological insulator known to date, which makes its properties very different as well.

One clear advantage of bismuth iodide is that its structure is more ordered than that of previously known topological insulators, and with fewer natural defects. In order to have an insulating interior, a material must have as few defects in its structure as possible.

“What we want is to pass current across the surface but not the interior,” explains Oleg Yazyev. “In theory, this sounds like an easy task, but in practice you’ll always have defects. So you need to find a new material with as few of them as possible.” The study shows that even these early samples of bismuth iodide appear to be very clean with very small concentration of structural imperfections.

After characterizing bismuth iodide with theoretical tools, the scientists tested it experimentally with an array of methods. The main evidence came from a direct experimental technique called “angle-resolved photoemission spectroscopy.” This method allows researchers to “see” electronic states on the surface of a solid material, and has become a key technique for proving the topological nature of electronic states at the surface.

The measurements, carried out at the Lawrence Berkeley National Lab, proved to be fully consistent with the theoretical predictions made by Gabriel Autès, a postdoc at Yazyev’s lab and lead author of the study. The actual electron structure calculations were performed at the Swiss National Supercomputing Centre, while data analysis included a number of scientists from EPFL and other institutions.

“This study began as theory and went through the entire chain of experimental verification,” says Yazyev. “For us is a very important collaborative effort.” His lab is now exploring further the properties of bismuth iodide, as well materials with similar structures. Meanwhile, other labs are joining the effort to support the theory behind the new class of topological insulators and propagate the experimental efforts.

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Date: December 16, 2015 at 12:00 p.m. ET

Free to attend

Length: Approximately one hour

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NAND Flash has become the non-volatile memory of choice for smart phones, tablets and solid state drives. The success of NAND in these markets has been driven by a relentless improvement in cost per bit by continually shrinking lithographic features for 2D planar NAND. This lithography driven model for 2D NAND is now breaking down and 3D has entered the market as the NAND solution of the future. In the first segment of the Webinar we will discuss how NAND flash has gotten to where it is today and the current technical limitations. This will set the stage for the second segment addressing 3D NAND.

Flash memory has revolutionized the world of solid-state data storage, mainly because of the advent of NAND technology. Started in multimedia applications for the consumer market (cell phones, audio players, digicam, USB sticks…) the technology has recently migrated also in the laptop and tablets market as well as in enterprise storage and server farms where it has become an indispensable component in the memory hierarchy of large storage systems. Especially the latter is a major growth market, which will propel Flash into the Terabit era.

However, from the technical point of view, this requires a major change in how these memories are being fabricated. The floating gate concept which has been the old ‘work horse’ for the entire nonvolatile memory market since the 60s until today, has finally run out of steam because of major physical limitations with respect to the device electrostatics. Therefore, the industry has been looking for alternatives for many years (Phase Change memory, Spin-based Magnetic memory, Ferroelectric memory, Resistance RAM, micromechanical memory, nanocrystal memory, TANOS, etc). Finally, the winner concept turns out to be the 3D or vertical NAND concept which is based on the stacking of vertical gate-all-around (GAA) devices with a nitride charge trapping layer. While the other ‘emerging’ memory types mentioned above are narrowed down to other application areas such as embedded memories and storage class memories (SCM), the 3D NAND has created a new roadmap which is no longer solely linked to the lithography roadmap but rather to a combination of parameters such as cell diameter, vertical cell pitch, numbers of cells in a stack and the number of bits per cell.

This presentation will discuss this (r)evolution as well as its major scaling limitations.

Speakers:

jan van houdtProf. Dr. Jan Van Houdt, IEEE Fellow

Jan Van Houdt received a MSc degree in Electrical and Mechanical Engineering and a PhD from the University of Leuven. During his PhD work, he invented the HIMOS™ Flash memory, which he transferred to several industrial production lines. In 1999 he became responsible for Flash memory at imec and as such was the driving force behind the expansion of imec’s Memory Program. Today he is Chief Scientist in the Process Technology unit of imec. He has published more than 250 papers in international journals and accumulated more than 200 conference contributions (incl. 35 invitations and 5 best paper awards). He has filed more than 50 patents and served on the program and organizing committees of 10 major semiconductor conferences. In 2014 he received the title of IEEE Fellow for his contributions to Flash memory devices. Recently, he was appointed a part-time professor in Electrical Engineering and Nanotechnology at the University of Leuven.

ScottJ crop 72dpiScott Jones, Founder and President, IC Knowledge

Scotten (Scott) W. Jones has nearly 30 years of experience in the semiconductor and MEMS industries, 18 of those in senior management positions. He holds a BS in Physics from the University of Rhode Island, has published dozens of papers, books and book length reports and holds two patents. His career focus has been on manufacturing and process technology. Scott’s responsibilities have included manufacturing, engineering, IT, technology development, finance and accounting. Scott has built or upgraded several wafers fabs and has extensive experience in manufacturing execution systems, cost modeling, IP licensing agreements, outsourcing and foundry relationships. Scott’s management positions have included Vice President and Co-General Manager of a Semiconductor Division, Vice President of Operations at a Semiconductor Company and Vice Presidents of Engineering and Vice President of Operations at a MEMS Company. Scott is a senior member of the IEEE and is a lifetime member of Strathmore’s Who’s Who. In addition to serving as President of IC Knowledge, he also serves as a Director of the Georgetown Education Foundation.

Sponsored by Air Products

Air Products has been a leading global supplier of high-purity gases, chemicals, and delivery systems to the electronics industry for over 40 years. We serve all major segments of the industry with a unique combination of offerings, experience, and commitment.  We’re advancing materials science. We’re advancing semiconductors. We’re advancing mobility. What can we help you advance?  www.airproducts.com/advancing

Cryogenic Vacuum Pumps


December 16, 2015

Cryopumps are commonly cooled by compressed helium, though they may also use dry ice, liquid nitrogen, or stand-alone versions may include a built-in cryocooler. Baffles are often attached to the cold head to expand the surface area available for condensation, but these also increase the radiative heat uptake of the cryopump. Over time, the surface eventually saturates with condensate and thus the pumping speed gradually drops to zero. It will hold the trapped gases as long as it remains cold, but it will not condense fresh gases from leaks or backstreaming until it is regenerated. Saturation happens very quickly in low vacuums, so cryopumps are usually only used in high or ultrahigh vacuum systems.

The cryopump provides fast, clean pumping of all gases in the 10−3 to 10−9 Torr range. The cryopump operates on the principle that gases can be condensed and held at extremely low vapor pressures, achieving high speeds and throughputs. The cold head consists of a two-stage cold head cylinder (part of the vacuum vessel) and a drive unit displacer assembly. These together produce closed-cycle refrigeration at temperatures that range from 60 to 80K for the first-stage cold station to 10 to 20K for the second-stage cold station, typically.

Regeneration of a cryopump is the process of evaporating the trapped gases. During a regeneration cycle, the cryopump is warmed to room temperature or higher, allowing trapped gases to change from a solid state to a gaseous state and thereby be released from the cryopump through a pressure relief valve into the atmosphere.

Most production equipment utilizing a cryopump have a means to isolate the cryopump from the vacuum chamber so regeneration takes place without exposing the vacuum system to released gasses such as water vapor. Water vapor is the hardest natural element to remove from vacuum chamber walls upon exposure to the atmosphere due to monolayer formation and hydrogen bonding. Adding heat to the dry nitrogen purge-gas will speed the warm-up and reduce the regeneration time.

According to the newly released “Global Semiconductor Packaging Materials Outlook — 2015/2016 Edition,” the $18 billion semiconductor packaging materials will undergo steady single-digit unit volume growth for many material segments through 2019, including laminate substrates, IC leadframes, underfill, and copper wire. Segments such as wafer-level packaging (WLP) dielectrics will experience stronger unit volume growth over the same timeframe. The new report by SEMI and TechSearch International covers laminate substrates, leadframes, bonding wire, mold compounds, underfill materials, liquid encapsulants, die attach materials, solder balls, wafer level package dielectrics, and thermal interface materials.

Packaging materials are a key enabler to increasing the functionality of thinner, smaller packages consumed in smart phones and other mobile products. Many options are currently available to meet form factor requirements for mobile products such as stacked-die chip scale package (CSP), land grid array (LGA) and fine pitch ball grid array (FBGA) packages, package-on-package (PoP), wafer-level package (WLP), Quad Flat No-lead (QFN) and other packages, using both wirebond and flip chip interconnects.

Key observations include:

  • FO-WLP is emerging as a disruptive technology, changing the demand for the types of packaging materials used in the industry
  • Need for WLP dielectric materials for multi-layer redistribution layers
  • New materials for laminate substrates and underfill to pitch decreasing pitch and bump height trends in flip chip packaging
  • Improved mold compounds for warpage control and package reliability
  • For QFN packaging, cost optimization through enhanced designs and reduced plating area; higher lead counts (routable); improved power dissipation
  • Continued growth in copper and silver wire
  • Materials and processes compatible with tighter tolerances for higher density leadframes and substrate packaging, and for compact multi-die system-in-package (SiP) configurations

Constrained industry growth and the trend towards lower-cost electronics have reshaped the packaging material supplier landscape. Changes in material sets, the emergence of new package types, and cost reduction pressures have resulted in recent consolidation in various material segments. In addition, materials consumption in some segments is declining given the changes in package form factors and the trend towards smaller, thinner packaging (see Figure).

metal compound consump

Source: SEMI and TechSearch International, Global Semiconductor Packaging Materials Outlook 2015/2016 Edition

The findings in the report are based on over 150 in-depth interviews conducted with semiconductor manufacturers, fabless semiconductor companies, packaging subcontractors, and packaging materials suppliers throughout the world. The report covers details about the industry growth and trends for the various material segments. Information includes market size, regional data, unit trends, and market share. It includes previously unpublished data on revenue, unit shipments and market shares for each packaging material segment; a five-year forecast of revenue and units from 2015 to 2019; supplier rankings (for key segments) and listing (including new players); and an analysis of regional market trends and size. All of the information was derived from the SEMI Global Packaging Materials Outlook from 2015 to 2019 produced by SEMI and TechSearch International.