Yearly Archives: 2015

Gases


December 11, 2015

A variety of gases are used in semiconductor manufacturing for process reactions in chemical vapor deposition, etching, ion implantation and many other processes. They are also used for such diverse purposes as chamber cleaning and purging. Generally speaking, gases are classified as processes gases for the first set of applications and bulk gases for the second. Bulk gases are hydrogen, helium and nitrogen, for example, which can be produced on-site through air separation plants. Process gases are typically supplied in the familiar gas tanks, or sometimes gas tanker trailers if the volume required is high enough. In some parts of the world, underground piping is used to supply multiple fabs

Aside for the gas type, the most common concern is the purity of the gas. Purity is often discussed in the “number of nines” level of purity. Gases that are 99.999% pure, for example, are “five nines” purity, gases that are 99.9999% pure are “six nines” purity and so on. Alternatively, trance contaminants are measured in parts per million (ppm), parts per billion (ppb) or even parts per trillion (ppt). Higher levels of purity are, of course, more difficult to produce and are therefore more costly. They are also more difficult to measure accurately. An ongoing challenge in the semiconductor industry is that gas users — IC manufacturers — tend to specify the highest level of purity available, but it’s often unknown if that higher level of purity actually provides any kind of benefit to device performance or yield. Indeed, sometimes trace impurities have proved to have some kind of beneficial effect and removing them can actually decrease performance.

Another important aspect — some would say the most important aspect — is safety. Gases can be toxic, carcinogenic, flammable, pyrophoric, corrosive and generally hazardous. A silane leak, for example, could result in a pocket of silane in a corner of the fab, which could explode. Arsine and phosphine, commonly used in ion implantation, are deadly in ppb and ppt, respectively. Fortunately, the semiconductor industry has an excellent safety record and danger to fab personnel is minimal — as long as established safety protocols are closely followed. This include storing gas cylinders in well monitored gas cabinets.

Chemical Vapor Deposition


December 11, 2015

Chemical vapor deposition (CVD) is used to produce high-purity thin films. In a typical CVD process, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Frequently, volatile byproducts are also produced, which are removed by gas flow through the reaction chamber.

Microfabrication processes widely use CVD to deposit materials in various forms, including: monocrystalline, polycrystalline, amorphous, and epitaxial. These materials include: silicon, carbon fiber, filaments, carbon nanotubes, SiO2, silicon-germanium, tungsten, silicon carbide, silicon nitride, silicon oxynitride, titanium nitride, and various high-k dielectrics. The CVD process is also used to produce synthetic diamonds.

Applications include shallow-trench isolation, pre-metal dielectric, inter-metal dielectric, and passivation. CVD processes are also important in strain engineering that uses compressive or tensile stress films to enhance transistor performance through improved conductivity.

Additional Reading

Taking 2D materials from lab to fab, and to technology

New materials require new approaches

Deposition equipment market witnesses a year of significant change

Wafer Inspection


December 11, 2015

Wafers need to be inspected at many stages throughout the manufacturing process. Particles and defects need to be detected and classified. Features need to be measured in both the x, y and z direction (critical dimensions and film thickness, for example). Film stoichiometry needs to be measured. Wafer warpage and bow must be evaluated and compensated for. Film stress (either tensile or compressive) is another important measurand as is dopant concentration, adhesion, and dozens if not hundred of other parameters. Variations across the wafer, within each die and die-to-die are also important.

Wafer inspection — also called metrology — is mostly used for process control, to make sure processes are not drifting out of control, As such, measurements are made after each process step — or more infrequently if at all possible since there is a cost associated with every inspection step in terms of capital equipment required, reduced throughput and added particles from increased handling.

Of course, more advanced characterization techniques are also needed for process development and failure analysis.

New inspection challenges include the need to measure more complex device structures such as those found in FinFETs and 3D NAND. The industry is also pushing a wide array of new materials into production, which brings a new set of challenges since each type of material has unique properties when it comes to reflection, refraction, adhesion, stress, etc.

The push to smaller dimensions and thinner films means smaller defects and variations become more important, which often pushes the accuracy, resolution and repeatability limits of today’s measurement tools.

The most common type of wafer inspection tool is the optical microscope. Although still used today for macro inspection, the very small dimension on today’s wafers can only be measured by more advanced means, most notably the scanning electron microscope and the transmission electron microscope. Other commonly used tools include ellipsometers to measure film thickness.

For failure analysis, even more sophisticated surface analysis tools are required, including  ESCA, Auger, EDAX, and Rutherford Backscattering (RBS), among many others.

Atomic Layer Deposition


December 11, 2015

There are four main segments in the thin-layer deposition equipment market – atomic layer deposition (ALD), chemical vapor deposition (CVD), epitaxy, and physical vapor deposition (PVD), also known as sputtering. Although CVD equipment represents the largest equipment type, ALD represents the fastest growing equipment category.

ALD is a technique capable of depositing a variety of thin film materials from the vapor phase. As device requirements push toward smaller and more spatially demanding structures, ALD has demonstrated potential advantages over alternative deposition methods, such CVD and PVD due to its conformality and control over materials thickness and composition. These desirable characteristics originate from the cyclic, self-saturating nature of ALD processes [1].

‪Layers are formed during reaction cycles by alternately pulsing precursors and reactants and purging with inert gas in between each pulse. Each atomic layer formed by this sequential process is a result of saturated surface-controlled reactions. For example, a metal precursor pulse of trimethylaluminum (Al(CH3)3) followed by an oxygen reactant pulse (H2O vapor) results in the formation of a layer of aluminum oxide, a metal oxide compound that can be used as a high-k dielectric.

Building devices atom by atom enables very precise control over the process. Because the ALD process is self-limiting, it results in films with a precise thickness and conformality, even over varied surface topographies. It can be applied to produce different oxides, nitrides or other compounds. ALD provides excellent surface control and can produce thin, uniform and pinhole-free films over large areas by single or tailored multiple layer deposition. Nanolaminates or stacked layers of different materials can also be produced, in a straightforward manner, in the ALD reactor. ​

According to new report by Global Industry Analysts, Inc., the global market for thin layer deposition equipment in semiconductor applications is projected to reach US$13.6 billion by 2020, driven by expanding electronics industry and parallel growth in demand for semiconductor solutions.

In terms of R&D, metal ALD has been challenging because of lack of suitable chemistry and nucleation problems. The development of processes for platinum group metals was a success but need for good industrial processes for many other metals still exists. Metal sulfides are old ALD materials and in industrial use in electroluminescent display production but ALD of selenides and tellurides has been much less studied. The need of chalcogenides in phase change materials and development of alkyl silyl precursors for selenium and tellurium has improved the situation. There is still a need to develop new ALD processes for microelectronics, low-k materials, 2D materials and oxides for transparent TFTs, according to Markku Leskelä, University of Helsinki, Finland.

In addition to applications in microelectronics there are many emerging areas where ALD has been introduced. One important area is energy technology materials. ALD films are used in silicon solar cells as passivation layers and they are extensively studied in many other areas such as dye sensitized solar cells, lithium ion batteries, supercapacitors and fuel cells. Indicative for these and many other applications is the use of known – mostly oxide –processes for protection. Li ion batteries make an exception and new materials and processes have been developed for lithium compounds. Research is also underway to adapt ALD processes to high-throughput roll-to-roll production for printed/flexible electronics.

Key players in the ALD deposition arena include Applied Materials Inc., ASM International N.V., Jusung Engineering Co. Ltd., Lam Research Corporation, Oxford Instruments, Picosun, Tokyo Electron Limited, ULVAC Technologies Inc., Ultratech/Cambridge Nanotech and Veeco Instruments Inc., among others.

The American Vacuum Society hosts an annual conference on Atomic Layer Deposition dedicated to the science and technology of atomic layer controlled deposition of thin films.

References

  1. http://www.sciencedirect.com/science/article/pii/S1369702114001436

Suggested additional reading

Atomic layer deposition goes mainstream in 22nm logic technologies

Successful industrialization of high-density 3D integrated silicon capacitors for ultra-miniaturized electronic components

Particle Atomic Layer Deposition

JVST A – Most Read Atomic Layer Deposition Articles Published in 2014

Chemical mechanical planarization (CMP) is a critical process technology step in the semiconductor wafer fabrication process. In this process step, the top surface of the wafer is polished or planarized to create a flat surface.

The CMP tool is comprised a rotating platen, slurry, pad, holding ring, brush, and pad conditioner. The mechanical element of this system applies downward pressure to a wafer surface, while the chemical reaction increases the material removal rate. The value chain of the CMP market consists of different players, including semiconductor material suppliers, CMP integrated solution providers, semiconductor wafer suppliers, semiconductor device manufacturers, slurry & pad manufacturers, technology solution providers, and CMP equipment manufacturers.

While CMP is still used for its traditional polishing applications for interlayer dielectrics, it’s also finding employment in more advanced applications, such as bulk oxide polishing, shallow trench isolation, “stop on poly” isolation, and polishing of various dielectrics in advanced transistor designs.

According to a recent market research report published by MarketsandMarkets, the global CMP market is expected to reach $4.94 Billion by 2020, at an estimated CAGR of 6.83% from 2015 to 2020.

Though the CMP market is at the mature stage, it still continues to evolve depending on the end users. The industry is being forced to adopt much innovation in process technologies and applications; as a result, different CMP processes have been evolved with technology nodes and newer applications such as MEMS, advanced packaging, and advanced substrates.

Applied Materials, Inc. (U.S.) and Ebara Corporation (Japan) are the major CMP equipment suppliers. Phoenix-based Entrepix offers unique CMP foundry services.

CMP includes consumable products, polishing pads and slurries. This CMP consumables market is dominated by major market players such as Cabot Microelectronics Corporation (U.S.), Fujimi Incorporated (Japan), and Dow Electronic Materials (U.S.).

Success in CMP lies in optimizing the many process variables. In addition to wafer variables such as film type and pattern density, CMP variables include: time, pressure (force applied to the wafer and pad), velocity, temperature, slurry feed rate, polishing motion, slurry chemistry and pH potential, slurry particle size, pad elasticity, pad hardness and pad condition method. An optimized CMP process also depends on removal rates of the film being planarized, adhesion stability of the film, minimal defects such as scratchs or pits, minimal corrosion (in the case of Cu), and the adhesion of organic or inorganic surface residues formed during the CMP process.

With alternate channel materials on the horizon for future logic transistor, III-V materials such as gallium-arsenide (GaAs), gallium-indium-phosphide (GaInP), and indium-phosphide (InP) are now in R&D which leads to questions regarding direct process costs as well as indirect EHS costs. Much of the concern involves the possible reaction and release of toxic hydrides such as arsine, and phosphine. SEMATECH worked with imec to monitor hydrides produced during CMP processes for high-mobility compound semiconductors.

Suggested Additional Reading:

Chemical Mechanical Planarization: Historical Review and Future Direction

Northern California Chapter of American Vacuum Society: CMP Users Group

CMP Technology Evolving to Engineer Surfaces

Reduced defectivity and cost of ownership of copper CMP cleans

Safe CMP slurries for future IC materials

The rule of three

Using a new procedure researchers at the Technical University of Munich (TUM) and the Ludwig Maximillians University of Munich (LMU) can now produce extremely thin and robust, yet highly porous semiconductor layers. A very promising material – for small, light-weight, flexible solar cells, for example, or electrodes improving the performance of rechargeable batteries.

Filled with suitable organic polymers the highly porous germanium nanofilm becomes a hybrid solar cell. Because the germanium nanostructure forms an inverse opal-structure, the material shimmers like opal. Credit: Andreas Battenberg / TUM

Filled with suitable organic polymers the highly porous germanium nanofilm becomes a hybrid solar cell. Because the germanium nanostructure forms an inverse opal-structure, the material shimmers like opal. Credit: Andreas Battenberg / TUM

The coating on the wafer that Professor Thomas Fässler, chair of Inorganic Chemistry with a Focus on Novel Materials at TU Munich, holds in his hands shimmers like an opal. And it has amazing properties: It is hard as a crystal, exceptionally thin and – since it is highly porous – light as a feather.

By integrating suitable organic polymers into the pores of the material, the scientists can custom tailor the electrical properties of the ensuing hybrid material. The design not only saves space, it also creates large interface surfaces that improve overall effectiveness.

“You can imagine our raw material as a porous scaffold with a structure akin to a honeycomb. The walls comprise inorganic, semiconducting germanium, which can produce and store electric charges. Since the honeycomb walls are extremely thin, charges can flow along short paths,” explains Fässler.

The new design: bottom-up instead of top-down

But, to transform brittle, hard germanium into a flexible and porous layer the researchers had to apply a few tricks. Traditionally, etching processes are used to structure the surface of germanium. However, this top-down approach is difficult to control on an atomic level. The new procedure solves this problem.

Together with his team, Fässler established a synthesis methodology to fabricate the desired structures very precisely and reproducibly. The raw material is germanium with atoms arranged in clusters of nine. Since these clusters are electrically charged, they repel each other as long as they are dissolved. Netting only takes place when the solvent is evaporated.

This can be easily achieved by applying heat of 500 °C or it can be chemically induced, by adding germanium chloride, for example. By using other chlorides like phosphorous chloride the germanium structures can be easily doped. This allows the researchers to directly adjust the properties of the resulting nanomaterials in a very targeted manner.

Tiny synthetic beads as nanotemplates

To give the germanium clusters the desired porous structure, the LMU researcher Dr. Dina Fattakhova-Rohlfing has developed a methodology to enable nanostructuring: Tiny polymer beads form three-dimensional templates in an initial step.

In the next step, the germanium-cluster solution fills the gaps between the beads. As soon as stable germanium networks have formed on the surface of the tiny beads, the templates are removed by applying heat. What remains is the highly porous nanofilm.

The deployed polymer beads have a diameter of 50 to 200 nanometers and form an opal structure. The germanium scaffold that emerges on the surface acts as a negative mold – an inverse opal structure is formed. Thus, the nanolayers shimmer like an opal.

“The porous germanium alone has unique optical and electrical properties that many energy relevant applications can profit from,” says LMU researcher Dr. Dina Fattakhova-Rohlfing, who, in collaboration with Fässler, developed the material. “Beyond that, we can fill the pores with a wide variety of functional materials, thereby creating a broad range of novel hybrid materials.”

Nanolayers pave the road to portable photovoltaic solutions

“When combined with polymers, porous germanium structures are suitable for the development of a new generation of stable, extremely light-weight and flexible solar cells that can charge mobile phones, cameras and laptops while on the road,” explains the physicist Peter Müller-Buschbaum, professor of functional materials at TU Munich.

Manufacturers around the world are on the lookout for light-weight and robust materials to use in portable solar cells. To date they have used primarily organic compounds, which are sensitive and have relatively short lifetimes. Heat and light decompose the polymers and cause the performance to degrade. Here, the thin but robust germanium hybrid layers provide a real alternative.

Nanolayers for new battery systems

Next, the researchers want to use the new technology to manufacture highly porous silicon layers. The layers are currently being tested as anodes for rechargeable batteries. They could conceivably replace the graphite layers currently used in batteries to improve their capacity.

Light and electricity dance a complicated tango in devices like LEDs, solar cells and sensors. A new anti-reflection coating developed by engineers at the University of Illinois at Urbana Champaign, in collaboration with researchers at the University of Massachusetts at Lowell, lets light through without hampering the flow of electricity, a step that could increase efficiency in such devices.

An array of nanopillars etched by thin layer of grate-patterned metal creates a nonreflective surface that could improve electronic device performance. Credit: Image courtesy of Daniel Wasserman

The coating is a specially engraved, nanostructured thin film that allows more light through than a flat surface, yet also provides electrical access to the underlying material – a crucial combination for optoelectronics, devices that convert electricity to light or vice versa. The researchers, led by U. of I. electrical and computer engineering professor Daniel Wasserman, published their findings in the journal Advanced Materials.

“The ability to improve both electrical and optical access to a material is an important step towards higher-efficiency optoelectronic devices,” said Wasserman, a member of the Micro and Nano Technology Laboratory at Illinois.

At the interface between two materials, such as a semiconductor and air, some light is always reflected, Wasserman said. This limits the efficiency of optoelectronic devices. If light is emitted in a semiconductor, some fraction of this light will never escape the semiconductor material. Alternatively, for a sensor or solar cell, some fraction of light will never make it to the detector to be collected and turned into an electrical signal. Researchers use a model called Fresnel’s equations to describe the reflection and transmission at the interface between two materials.

“It has been long known that structuring the surface of a material can increase light transmission,” said study co-author Viktor Podolskiy, a professor at the University of Massachusetts at Lowell. “Among such structures, one of the more interesting is similar to structures found in nature, and is referred to as a ‘moth-eye’ pattern: tiny nanopillars which can ‘beat’ the Fresnel equations at certain wavelengths and angles.”

Although such patterned surfaces aid in light transmission, they hinder electrical transmission, creating a barrier to the underlying electrical material.

“In most cases, the addition of a conducting material to the surface results in absorption and reflection, both of which will degrade device performance,” Wasserman said.

The Illinois and Massachusetts team used a patented method of metal-assisted chemical etching, MacEtch, developed at Illinois by Xiuling Li, U. of I. professor of electrical and computer engineering and co-author of the new paper. The researchers used MacEtch to engrave a patterned metal film into a semiconductor to create an array of tiny nanopillars rising above the metal film. The combination of these “moth-eye” nanopillars and the metal film created a partially coated material that outperformed the untreated semiconductor.

“The nanopillars enhance the optical transmission while the metal film offers electrical contact. Remarkably, we can improve our optical transmission and electrical access simultaneously,” said Runyu Liu, a graduate researcher at Illinois and a co-lead author of the work along with Illinois graduate researcher Xiang Zhao and Massachusetts graduate researcher Christopher Roberts.

The researchers demonstrated that their technique, which results in metal covering roughly half of the surface, can transmit about 90 percent of light to or from the surface. For comparison, the bare, unpatterned surface with no metal can only transmit 70 percent of the light and has no electrical contact.

The researchers also demonstrated their ability to tune the material’s optical properties by adjusting the metal film’s dimensions and how deeply it etches into the semiconductor.

“We are looking to integrate these nanostructured films with optoelectronic devices to demonstrate that we can simultaneously improve both the optical and electronic properties of devices operating at wavelengths from the visible all the way to the far infrared,” Wasserman said.

Defining and exploiting value proposition is an essential part of wearable technology’s journey from early adopters into mass markets, and sensor platforms enable the key value proposition in most wearable devices today. This is why made-for-wearable sensors are being developed around the world, and this is why IDTechEx Research finds that made-for-wearable sensors will represent 42% of all sensors in wearable devices in 2026, up from a measly 7% in 2015.

There will be a $5.5 billion market for sensors used in wearable technology applications by 2025, according to IDTechEx’s best-selling research report on the topic. With detailed coverage of the 15 most prominent sensor types in wearables today, this report gives a thorough overview of the technology, challenges and opportunities behind one of the key components behind the success of wearable technology.

Fig 1. First and second wave wearable sensors. Source: IDTechEx Research report "Wearable Sensors 2015-2025: Market Forecasts, Technologies, Players" (www.IDTechEx.com/wtsensors)

Fig 1. First and second wave wearable sensors. Source: IDTechEx Research report “Wearable Sensors 2015-2025: Market Forecasts, Technologies, Players” (www.IDTechEx.com/wtsensors)

Overcoming the barriers to adoptions

However, key hurdles must be surpassed in order for these sensor technologies to realize their full potential and penetrate key vertical markets. Healthcare is perhaps the best example, where regulatory processes and liability issues remain extremely prominent. Leading doctors admit that those who fail to adopt of technology in the form of digital health or otherwise will “fall by the way side” as advances occur. However, until all of the parties (device manufacturers, physicians, insurance companies, patients, and the lawyers of all the above) understand a clear system of liability, this remains a significant barrier to adoption.

New sensor technologies unlock new markets

Wearable sensor systems have already begun to unlock new markets. The textile and electronics industry has started to merge together around e-textiles. In the earliest products reaching the market, advances in low-energy communication can be paired with new made-for-wearable sensor types based on textiles and inks that are increasingly washable, comfortable and reliable. The current commercial focus here is on high value sport and fitness applications in the short term, but this will spread to wider industries including healthcare, home textiles, and industrial spaces in the next 2-5 years.

The IDTechEx report concludes that these sensor types will climb to huge volumes in the coming decade. As the number of wearable devices and the number of sensors per device both increase rapidly, sensors used to detect motion (stretching, deformation, etc.), force and pressure will be one of the largest winners, growing at 40% CAGR. The technology landscape here is in a period of divergence. Introduction of stretchable and washable inks, electroactive polymers, textile electrodes and printed piezoelectric sensors add to traditional techniques like inductive sensors using conductive elastomers or otherwise.

This broad technology landscape is a challenge for product designers. With many different materials come different requirements for connector types, electrical specifications, data algorithms and more. It will take some time for clear winners to emerge, and many large companies are still hedging their bets.

Fig 2. Technology landscape. Source: IDTechEx Research report "Wearable Sensors 2015-2025: Market Forecasts, Technologies, Players" (www.IDTechEx.com/wtsensors)

Fig 2. Technology landscape. Source: IDTechEx Research report “Wearable Sensors 2015-2025: Market Forecasts, Technologies, Players” (www.IDTechEx.com/wtsensors)

Sensor fusion

In 2015, half of all wearable sensors are based on MEMS technologies. Inertial measurement units (IMUs) are found in every smartwatch and fitness tracker, making the most of mature MEMS components that are reliable, familiar and cheap.

However, the challenge here is in turning raw data into useful, or ‘actionable’ data. Sensor fusion is the process of combining sensor outputs from multiple sensors to gain greater total insight. The most common example is using individual xyz acceleration and rotation data (e.g. from a 6-axis IMU) into motion data. This in turn can be used to count steps, differentiate between activity types, and so on. It is here that MEMS IMUs see more use cases. For example, they are used alongside optical sensors to manage motion artefacts experienced in optical heart rate monitoring. This was a far more traditional use of such components in physiological analytics, and now the wearable technology industry is beginning to come full circle.

To learn more about the trends with IMUs, stretch and pressure sensors, and all of the other prominent and emerging sensor types used in wearable technology today and in the future, see IDTechEx’s comprehensive report: Wearable Sensors 2015-2025: Market Forecasts, Technologies, Players.

At this week’s IEEE IEDM conference, nano-electronics research center imec demonstrates record enhancement of novel InGaAs Gate-All-Around (GAA) channel devices integrated on 300mm Silicon and explores emerging tunnel devices based on optimization of the same III-V compound semiconductor.

III-V-on-Si GAA devices with a record peak transconductance at 0.5V has been achieved by optimizing both the channel epitaxy quality and the gate-channel passivation. In search of device technologies beyond FinFETs and GAA-nanowires for sub-0.5V operations, imec investigates InGaAs Tunnel-FET (TFETs). Homo-junction III-V TFETs achieving a record ON-state current (ION) and superior subthreshold swing have been demonstrated. These results increase the knowledge on the impact of defectivity and channel optimization on device operations, and pave the way to advanced logic devices based on III-V-On-Si for high performance or ultra-low power applications.

Imec’s R&D program on advanced logic scaling is targeting the new and mounting challenges for performance, power, cost, and density scaling for future process technologies. One of the directions that imec is following, looks into beyond-Si solutions, such as integrating high-mobility materials into the channels of CMOS devices to increase their performance, and the integration challenges of these materials with silicon. Gate-All-Around Nanowire (GAA NW) FETs have been proven to offer significantly better short-channel electrostatics, and quantum-well FinFETs (with SiGe, Ge, or III-V channels) achieving high carrier mobility, are interesting concepts to increase device performance. Tunnel FETs, on the other hand, offering a steeper than 60mV/dec subthreshold swing, are a promising option for ultra-low power applications.

At IEDM, imec presented gate-all-around InGaAs Nanowire FETs (Lg=50nm) that performed at an average peak transconductance (gm) of 2200µS/µm with a SSSAT of 110mV/dec. Imec succeeded in increasing the performance by gate stack engineering using a novel gate stack ALD inter-layer (IL) material developed by ASM, and high pressure annealing. The novel IL/HfO2 stack achieved a 2.2 times higher gm for a device with a gate length (Lg) of 50nm, compared to the reference Al2O3/HfO2 stack.

Imec also presented a planar InGaAs homo-junction TFET with 70 percent Indium (In) content. The increase of In content from 53 to 70 percent in a 8nm channel, was found to significantly boost the performance of the device. A record ON-state current (ION) of 4µA/µm (IOFF = 100pA/µm, Vdd = 0.5V and Vd = 0.3V) with a minimum subthreshold swing (SSmin) of 60mV/dec at 300k was obtained for a planar homo-junction TFET device. It was also shown that subthreshold swing and transconductance in TFET devices were more immune to positive bias temperature instability (PBTI) compared to MOSFET devices.

“Imec’s R&D enables Moore’s Law beyond the 5nm technology node through 3 approaches. First, we are tackling the technology challenges to extend silicon CMOS devices towards smaller nodes. At the same time, we research into disruptive heterogeneous solutions for beyond-silicon CMOS devices to increase performance and introduce new functionalities. Lastly, imec pursues emerging beyond-CMOS devices and systems such as spintronics to investigate further functional scaling beyond device-density-driven scaling,” stated Aaron Thean, vice president and director of imec’s advanced logic R&D program. “Boosting the performance of advanced compound semiconductor logic devices is extremely important, and these results support the quest of the semiconductor industry to find solutions that enable 5nm technology nodes and beyond.”

“ASM and imec have a long history of R&D collaboration using many of ASM’s products and advanced deposition and thermal processes,” says Ivo Raaijmakers, ASM CTO and Director of R&D. “As a leader in ALD, we are glad to see this breakthrough new ALD material now demonstrated in imec’s high mobility devices and presented at IEDM 2015.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Panasonic, Qualcomm, Samsung, SK Hynix, Sony and TSMC.

TEM of complete gate-all-around InGaAs Nanowire FET and HRTEM of the gatestack

TEM of complete gate-all-around InGaAs Nanowire FET and HRTEM of the gatestack

At this week’s IEEE IEDM conference, nano-electronics research center imec showed for the first time the integration of high mobility InGaAs as a channel material for 3D vertical NAND memory devices formed in the plug (holes) with the diameter down to 45nm. The new channel material improves transconductance (gm) and read current which is crucial to enable further VNAND cost reduction by adding additional layers in 3D vertical architecture.

Non-volatile 3D NAND flash memory technology is used to overcome the scaling issues in conventional planar NAND flash memory technology, suffering from severe cell to cell interferences and read noise due to aggressively scaled dimensions. However, current 3D NAND devices, featuring a poly-Si channel, are characterized by drive current that will linearly decrease with the number of memory layers, which is not sustainable for long-term scaling. This is because the conduction in the poly-silicon channel material is ruled by grain size distribution and hampered by scattering at the grain boundaries and charged defects.

To boost the drive current in the channel, imec replaced the poly-Si channel material with InGaAs through a gate first-channel last approach. The channel was formed by metal organic vapor phase epitaxy (MOVPE) showing good III-V growth selectivity to silicon and holes filling properties down to 45nm. The resulting III-V devices proved to outperform the poly-Si devices in terms of on-state current (ION) and transconductance (gm), without degrading memory characteristics such as programming, erase and endurance.

“We are extremely pleased with these results, as they provide critical knowledge of Flash memory operations with a III-V channel as well as of the III-V interface with the memory stack,” stated An Steegen, Senior Vice president Process Technology at imec. “While these results are shown on full channels, they are an important stepping stone to develop industry-compatible macaroni-type III V channels.”

Imec’s research into advanced memory is performed in cooperation with imec’s key partners in its core CMOS programs including Samsung, Micron-Intel, Toshiba-Sandisk, SK Hynix, TSMC, GlobalFoundries.

Typical ID-VG. In0.6Ga0.4As presents improved ID-VG characteristic. Ion/Ioff ratio of 3 order of magnitude is sufficient for typical NAND operation

Typical ID-VG. In0.6Ga0.4As presents improved ID-VG characteristic. Ion/Ioff ratio of 3 order of magnitude is sufficient for typical NAND operation