Yearly Archives: 2015

Due to the further scaling and increasing complexity of transistors, the boundaries between back-end-of-line and front-end-of-line reliability research are gradually fading. Imec’s team leaders Kristof Croes and Dimitri Linten give their vision on the future of reliability research.

In April 2015, the 53rd edition of the IEEE International Reliability Physics Symposium (IRPS) took place, a top conference where experts in reliability of micro- and nanoelectronics meet. With 16 contributions as either an author or a co-author, imec was prominently present.

Dimitri Linten: “Our contributions to conferences such as IRPS highlight the unique role that imec plays in the field of reliability. And they show the importance of reliability research at imec for the development of new transistor and memory concepts. As scaling continues, a whole range of new technology options is being researched. New materials and architectures with often unknown failure mechanisms are being introduced. Reliability is one of the factors that determine which concept will finally have a chance. For example, one of the options is to replace silicon in the transistor’s channel by germanium or a III/V material since these materials provide a higher charge carrier mobility. But until now, these materials pose important challenges to the reliability of the transistors that are made of these materials. Or, researchers look at introducing either air gaps or ultralow-k materials as spacers between the transistor’s gate and drain in order to keep the capacity as low as possible. The integration of all these new materials is important, but their reliability is crucial as well: reliability before performance.”

Front of line Fig 1

Kristof Croes: “10 years ago, reliability was tested only in a final stage of a technology development. But due to the ever decreasing reliability margins, the reliability is now being tested from the very beginning. And this starts with an understanding of the physics behind the failure, for which we often collaborate with universities. Once we understand the failure of e.g. new materials, we can model our findings and predict the lifetime of the device.”

Front-end-of-line vs back-end-of-line

Traditionally, CMOS process engineers classify the semiconductor process in two main parts: the front-end-of-line (FEOL) and the back-end-of-line (BEOL). The FEOL comprises all the process steps that are related to the transistor itself, including the gate of the transistor. The BEOL comprises all subsequent process steps. In the BEOL, the various transistors are being interconnected through metal lines. The same classification is being used in reliability research. Consequently, FEOL and BEOL reliability is tested independently.

Kristof Croes: “This historical separation is being applied at imec as well, where reliability research within the process technology division is distributed among several groups. One group looks into the reliability of FEOL and memory chips. Another group investigates the BEOL reliability and chip packaging interaction. Today, in BEOL processes, electromigration (the movement of metal atoms as a result of an electric current), stress migration, time dependent dielectric breakdown (TDDB) and thermomechanical stress are the main failure mechanisms. We also look into 3D structures, where the impact and reliability of through-Si vias are important issues. In a 3D-stacked structure, for some applications, the Si wafer needs to be thinned down to about 5 micrometer. And this impacts the reliability. And there are thermal and thermo-mechanical influences related to the assembly of materials with completely different mechanical properties. All these failure mechanisms in the BEOL will become increasingly important for future technology nodes.”

Dimitri Linten: “We look into the time dependent breakdown (TDDB) of the gate stack, and into stress-induced leakage current (SILC) and hot carrier stress (HC). The bias temperature instability (BTI) is important as well, as it causes a shift of the threshold voltage (VT) of the transistor during the lifetime of the circuit. We also investigate memory elements, by testing and modelling the retention and endurance of the memories. ESD or electrostatic discharge is still one of the main important failure mechanisms at the level of the final ICs in a certain technology. In order to intercept the current that is released during an electrostatic discharge, protecting ESD structures are implemented in the FEOL.”

Front of line Fig 2

FEOL and BEOL reliability: fading boundaries

As the dimensions of the transistor shrink, the impact of the FEOL on the BEOL reliability – and vice versa – increases. Kristof Croes: “A well-known example is self-heating in FinFETs. In planar CMOS processes, the heat that is released during the transistor’s operation is dissipated mainly through the Si substrate. But in a FinFET architecture, we have to take into account a higher thermal coupling towards the metal intercon- nects. The FinFETs warm up and heat the metal lines. And this impacts the reliability of the BEOL structure. In 3D technology, we thin down wafers with TSVs. After opening the TSVs, we can stack them on top of another wafer. The integration of the TSVs, the thinning and stacking of the wafers influence both the FEOL and the BEOL performance and reliability.”

Dimitri Linten: “Also the introduction of new architectures brings the reliability of FEOL and BEOL closer to each other. Think about vertical nanowires, potential successors of the FinFET because they promise a better electro- static channel control. One of the challenges in terms of reliability is to provide these structures with an ESD protection. While in more conventional structures, the FEOL is most sensitive to electrostatic discharge, the impact of electrostatic discharge on the BEOL becomes critical in vertical nanowires. In these 3D structures, we have to connect all the vertical nanowires through local interconnects and interconnects that will be located very close to each other. And these interconnects will put other requirements to the ESD protection circuit than we are used to. A possible solution is to consider a 3D stacking of ESD protection circuits on top of the transistor architecture.”

Another consequence of further scaling is an increase in the variability of the transistor parameters. In FEOL, variability is a well-known phenomenon.

Dimitri Linten: “Time dependent variability of BTI is a relatively new challenge for reliability research. For large transistors – the older generations – BTI translates into an average shift of the circuit’s threshold voltage of e.g. 50mV, the spec for BTI. But upon further scaling, there is no average shift anymore. Instead, there will be a static distribution of shifts. The variability becomes time dependent and the lifetime of the circuits will be spread. The imec FEOL reliability group is a world leader in this domain: we have developed a defect centric BTI model that has been adopted by market leaders in the semiconductor industry. On time dependent BTI, we closely collaborate with the design group in order to develop methodologies that take into account the time dependence.”

Kristof Croes: “Also in BEOL, variability becomes increasingly important. Think about via misalignment or line edge roughness of increasingly smaller metal lines. These issues degrade the reliability and the lifetime of the BEOL. To deal with the increasing variability, a powerful statistical toolbox is required. And this toolbox can be deployed for BEOL as well as for FEOL reliability research.”

Front of line Fig 3

When BEOL meets FEOL reliability

As dimensions are shrinking, the boundaries between FEOL and BEOL reliability are gradually fading.

Kristof Croes: “We are convinced that we should optimally attune the activities and tools used for reliability research. We have to bring the people from BEOL and FEOL reliability closer together. And we want to unite the researchers outside these groups that work on reliability. Reliability is a field of expertise and sharing problems often provides part of the solution. For future technology nodes and for develop- ments beyond scaling, this will increase the operational efficiency of reliability research. To strengthen this idea, we will organize an internal workshop at imec on September 4, with the help of our predecessors and colleagues Guido Groeseneken and Ingrid De Wolf. This will help our researchers to gain more insight into each other’s work and into the tools they use. Hopefully, this idea will be adopted outside of imec as well.”

Additional reading

Technical program of the 2015 IRPS conference with abstracts (http://www.irps.org/program/technical-program/15-program.pdf)

“New test allows to visualize in real-time crack formation of BEOL,” March issue of imec magazine (http://magazine.imec.be/data/57/ reader/reader.html#preferred/1/package/57/pub/63/page/2)

Feed-forward can be applied for controlling overlay error by using Coherent Gradient Sensing (CGS) data to reveal correlations between displacement variation and overlay variation.

BY DOUG ANBERG and DAVID M. OWEN, Ultratech, San Jose, CA

As the semiconductor industry is fast approaching 10nm design rules, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge requiring overlay control to a few nanometers. There are many factors that impact the overlay budget that can be broadly categorized as those arising from the reticle, the lithography tool and wafer processing. Typically, overlay budget components associated with the reticle and lithography tool can be characterized and are relatively stable. However, as published elsewhere, process-based sources of surface displacement can contribute to the lithography overlay budget, independent of the lithography process (e.g., etch, anneal, CMP). Wafer-shape measurement can be implemented to characterize process-induced displacements. The displacement information can then be used to monitor specific processes for excursions or be modeled in terms of parameters that can be fed-forward to correct the lithography process for each wafer or lot.

The implementation of displacement feed-forward for overlay control requires several components, including: a) a system capable of making comprehensive surface displacement measurements at high throughput, b) a characterization and understanding of the relationship between displacement and overlay and the corresponding displacement variability, c) a method or system to integrate the displacement information with the lithography control system. The Coherent Gradient Sensing (CGS)technique facilitates the generation of high-density displacement maps (>3 million points on 300mm wafers) such that distortions and stresses induced shot-by-shot and process-by-process can be tracked in detail. This article will demonstrate how feed forward can be applied for controlling overlay error by using CGS data to reveal correlations between displacement variation and overlay variation.

High-speed, full-wafer data collection

Historically, patterned wafer surface inspection was limited to monitoring topography variations within the die area and across the wafer with the use of point-by-point measurements with low throughput, typically limiting measurements to off-line process development. Surface inspection of patterned wafers involving transparent films (e.g. SiO2 deposited films) was typically further limited to contact techniques such as stylus profilometry.

With CGS interferometry, a high-resolution front-surface topography map of a full 300 mm patterned wafer can be obtained for product wafers with an inspection time of a few seconds. Transparent films can typically be measured successfully without opaque capping layers due to the self-referencing attribute of the CGS interferometer. Essentially, CGS technology compares the relative heights of two points on the wafer surface that are separated by a fixed distance. Physically, the change in height over a fixed distance provides slope or tilt information and the fringes in a CGS interference pattern are contours of constant slope. In order to reconstruct the shape of the surface under investigation, interference data in two orthogonal directions must be collected. The slope data derived from the interference patterns is integrated numerically to generate the surface shape or topography. In-plane surface displacements in the x- and y-directions can then be computed from the surface topography using fundamentals of plate theory (FIGURE 1).

Fig 1-a Fig 1-b Fig 1-c

FIGURE 1. Example of the analysis of the uniform and non-uniform stress components of the displacement field: (a) total displacement computed from the x-direction slope, (b) uniform stress component of the displacement field determined from the best-fit plane to the data in (a), (c) non- uniform stress component of the displacement field.

To best utilize the capabilities of CGS technology for determining stress-induced displacement impacting critical layer overlay budgets, a “Post minus Pre” inspection strategy is typically employed, where two measurements of a wafer are taken: one prior to the process step or module of interest (the pre-process map), and a second measurement is taken on the same wafer after completing the process step or module (the post-process map). The pre-process topography map is then mathematically subtracted from the post-process topography map, providing detailed, high resolution information about the topography variation in the process step or module of interest. A series of topography maps illustrating the “Post minus Pre” process is shown in FIGURE 2.

FIGURE 2. Example of “Post minus Pre” topography CGS measurement.

FIGURE 2. Example of “Post minus Pre” topography CGS measurement.

The surface displacements directly impact the relative position of all points on the wafer surface, leading to potential alignment errors across the wafer at the lithography step. By measuring the evolution of process-induced stresses and displacement across multiple steps in a process flow, the overlay error due to the accumulated stress changes from those process steps can be evaluated, and the cumulative displacement can be calculated. The displacement error can then be fed forward to the lithography tool for improved overlay correction during the exposure process.

In the simplest implementation of this approach, the pre-process or reference measurement would be made following the prior lithography step, whereas the post- processing measurement would be made just before the lithography step of interest. In this manner, the total displacement induced between two lithography steps can be characterized and provided to the lithography system for overlay correction.

Stress and displacement process fingerprinting

By using CGS-based inspection to generate full-wafer topography, displacement and stress, detailed information can be provided for both off-line process monitoring (SPC), or in-line, real-time monitoring (APC) of process steps with significant process induced stress and displacement. A key consequence of the monitoring flexibility afforded by the measurement is the ability to characterize and compare within- wafer displacement and stress fingerprints of individual process chambers in a manufacturing line.

Target-based overlay metrology systems have historically been used as the only metrology tool to measure overlay error at critical lithography layers. Overlay data from the target-based overlay tools is collected after the wafer exposure step and is fed-backward to correct for the measured overlay error for subsequent wafers. As process- induced displacement errors are becoming a significant percentage of the layer-to-layer overlay budget, this post processing feed-back approach for overlay correction may not be sufficient to meet critical layer overlay specifications. Furthermore, overlay errors are often larger near the edge of the wafer where traditional overlay metrology target densities are typically low, providing only limited data for overlay correction.

The implementation of displacement feed-forward overlay correction can be
used to account for wafer-to-wafer and within-wafer distortions prior to lithography. The displacements can be characterized using an appropriate model and the model coefficients, or correctables, can be provided to the lithography tool for adjustment and control on a wafer-by-wafer basis. As shown in FIGURE 3, the CGS technique has the additional advantage of providing high-data density near the edge of the wafer (typically > 75,000 data points beyond 145 mm, sub-sampled in the Fig. 3 vector map for clarity), such that more accurate corrections can be determined where the overlay errors tend to be largest. As a result, lithography rework can be reduced and productivity increased. Case studies have revealed that a significant improvement in overlay can be achieved using this approach.

FIGURE 3. Vector displacement map showing process-induced edge distortion.

FIGURE 3. Vector displacement map showing process-induced edge distortion.

For each critical lithography step, a correlation is typically generated by comparing the traditional overlay measurement tool results to the surface displacement measured by the CGS measurement tool. Recognizing that displacement is only one component of the total overlay measurement, correlation of overlay to displacement requires effort to model or characterize the non-displacement components of the measured overlay. As a result, the appropriate correlation is derived by comparing total overlay to displacement plus the non-displacement overlay sources.

FIGURE 4 shows plots of total overlay versus displacement plus modeled non-displacement overlay sources for multiple locations on a single wafer processed in a leading-edge device flow. Figure 4a shows the x-direction data, whereas Fig. 4b shows the y-direction data. The data is presented in arbitrary units, however the same reference value in nanometers was used to normalize each set of data. The displacement data was evaluated at the same locations as the overlay target positions. For both the x-direction and y-direction data, the point-to-point correlation indicates good correlation with the correlation coefficients of 0.70 and 0.76, respec- tively. The RMS of the residuals of the linear fit to each data set are on the order of 1.5 to 2.0 nm.

Fig 4a

Fig 4b

FIGURE 4. Within-wafer (point-to-point) correlation of conventional overlay data and displacement data for the (a) x-direction and (b) y-direction.

FIGURE 5 similarly shows the wafer-to-wafer variation for overlay and displacement for the x-direction (Fig. 5a) and y-direction (Fig. 5b). The data in Fig. 5 are from multiple lots for the same lithography process evaluated to generate the data in Fig. 4. As with the point-to-point data, the wafer-to-wafer data shows strong correlation with correlation coefficients of 0.94 and 0.90 for the x-direction and y-direction, respectively.

Fig 5a Fig 5b

FIGURE 5.Wafer-level correlation between conventional overlay, |mean| + 3 sigma and displacement, |mean| + 3 sigma for a leading-edge process in the (a) x-direction and (b) y-direction.

The data in Figs. 4 and 5 illustrate key points regarding the correlation of overlay to displacement. First, the inherent variability of an advanced lithography process is typically on the order of 1 to 2nm. As a result, it is reasonable to conclude that the most of the scatter shown in Fig. 4 is likely associated with the variability in non-displacement sources of overlay variation. Second, the modeling or empirical characterization of non-displacement overlay sources is useful to the extent to which those non-displacement sources are constant. Consequently, if such modeling is part of the displacement feed-forward scheme in an effort to predict overlay, the model must account for known variations in the lithography process. A simple example is varia- tions in overlay performance due to differences between lithography chucks.

Displacement feed forward

It has been shown elsewhere that stress induced displacement can account for a significant fraction of the overlay error for certain critical layers at the 40nm node and below. It is therefore critical to develop the tools necessary for utilizing the measured displacement data for real-time in-line feed forward overlay correction to the scanner. One approach to this solution is to develop a system that allows the user to define the level of correction to be applied to the scanner for each lot, wafer or within-wafer zone.

FIGURE 6 shows a simplified schematic for a combined displacement feed-forward and image placement error feed-back approach. Once the process induced displacement for a specific set of process steps has been measured and correlated to overlay error, the measured displacement can be “fed forward” to the scanner in combination with traditional image placement error feedback techniques to further improve critical layer scanner overlay results. This approach is currently being implemented in leading-edge memory fabs to further reduce overlay errors on critical lithography levels and improve overall device yield.

Summary

The measurement of process-induced surface displacement can be an effective part of the overlay control strategy for critical layers at leading edge process nodes. CGS technology provides a method to comprehensively measure these displacements at any point in the process flow. Using a full-wafer interferometer, this system measures the patterned wafer surface in a few seconds and provides a map with up to 3,000,000 data points. This enables 100% in-line monitoring of individual wafers for in-situ stress and process induced surface displacement measurements. Its self-referencing interferometer allows the inspection to be made on any type of surface or films stack, and does not require a measurement target. This capability is currently being employed in numerous leading-edge memory and logic processes.

DOUG ANBERG currently serves as Ultratech’s Vice President of Advanced Lithography Applications; DAVID M. OWEN has been the Chief Technologist for Surface Inspection at Ultratech since 2006. Prior to joining Ultratech, Dr. Owen spent nearly a decade as a research scientist at the California Institute of Technology (Caltech) in Pasadena, and was the Founder and Chief Technology Officer for Oraxion Diagnostics.

Worldwide semiconductor fab equipment capital expenditure growth (new and used) for 2015 is expected to be 0.5 percent (total capex of US$35.8 billion), increasing another 2.6 percent (to a total of $36.7 billion) in 2016, according to the latest update of the quarterly SEMI World Fab Forecast report.

SEMI reports that in 2015, Korea outspent all other countries ($9.0 billion) on front-end semiconductor fab equipment, and is expected to drop to second place in 2016 as Taiwan takes over with the largest capex spending at $8.3 billion. In 2015, Americas ranked third in overall regional capex spending with about $5.6 billion and is forecast to increase only slightly to (5.1 percent) in 2016.

fab equipment spending 2016

In 2015, 80 to 90 percent of fab equipment spending went to 300mm fabs, while only 10 percent was for 200mm or smaller.  SEMI’’s recently published “Global 200mm Fab Outlook” provides more detail about past and future 200mm activities.

Examining fab equipment spending by product type, Memory accounts for the largest share in 2015 and 2016.  While 2015’s spending was dominated by DRAM, the SEMI World Fab Forecast reports that 2016 will be dominated by Flash, mainly 3D-related architectures.  Capacity for 3D-NAND will continue to surge. SEMI’’s report tracks 10 major 3D producing facilities, with a capacity expansion of 47 percent in 2015 and 86 percent in 2016.

The Foundry segment is next in terms of the largest share of fab equipment spending in 2015 and 2016.  In general, the foundry segment shows steadier, more predictable spending patterns than other device product segments. Coming in third place in fab equipment spending, MPU had lower spending in 2015.  Logic spending was very strong in 2015, with 90 percent growth, driven by SONY’s CMOS image sensors.

Throughout 2015, SEMI anticipates that there will be 1,167 facilities worldwide investing in semiconductor equipment in 2016, including 56 future facilities across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities. For further details, please reference to the latest edition of SEMI’s World Fab Forecast report.

At this week’s IEEE International Electron Devices Meeting 2015, nano-electronics research center imec presented breakthrough results to increase performance and improve reliability of deeply scaled silicon CMOS logic devices.

Continued transistor scaling has resulted in increased transistor performance and transistor densities for the last 50 years. With transistor scaling reaching the critical limits of atomic dimensions, imec’s R&D program on advanced logic scaling targets the new and mounting challenges for performance, power, cost, and density scaling to future process technologies. Imec is looking into extending silicon CMOS technology by tackling the detrimental impact of parasitics on device performance and reliability, and by introducing novel architectures such as gate-all-around nanowires, that are considered to improve short channel control.

One of the achievements is a record low contact resistivity of 1.5 Ωcm2 for n-Si that was realized by combing dynamic surface anneal (DSA) to enhance P activation in highly-doped Si:P, with Ge pre-amorphisation and Ti silicidation. Imec also presented a decreased access resistance in NMOS Si bulk finFETs by applying extension doping by phosphorus doped silicate glass (PSG) to achieve damage free and uniform sidewall doping of the fin. Finally, imec introduced junction-less high-k metal-gate-all-around nanowires to improve on- and off-state hot carrier reliability.

“I am extremely proud with the record number of 23 papers that we present at this year’s IEDM2015,” stated Luc Van den hove, President and CEO at imec. “Our presence rewards and confirms our leading position in advanced semiconductor R&D. As much as 10 of the presented papers concerned the different aspects of our advanced logic program. Next to our research efforts to extend silicon CMOS technology into 7nm technology node and beyond. We are looking into beyond silicon CMOS, integrating high mobility materials to increase the channel mobility, and explore new concepts beyond silicon such as spintronics and 2D materials.”

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, Panasonic, Qualcomm, Samsung, SK Hynix, Sony and TSMC.

Cross-section of JL nanowires with or without an acceptor type interface, cut along the middle of the gate. The electrostatic potential is asymmetric when a trap is introduced; the squeezed channel improves the electrostatics and the subthreshold slope.

Cross-section of JL nanowires with or without an acceptor type interface, cut along the middle of the gate. The electrostatic potential is asymmetric when a trap is introduced; the squeezed channel improves the electrostatics and the subthreshold slope.

Beyond economic limits due to litho limitations, the inherent need for a physical barrier puts an electrical limit on the ability to scale.

BY ED KORCZYNSKI, Senior Technical Editor

On-chip interconnects for ICs have evolved to meet different exacting needs, and the most advanced chips require multiple levels of copper (Cu) metal lines and via connections between transistors. When scaling Cu lines to the finest dimensions possible to interconnect local transistors in advanced manufacturing nodes, there are economic limits due to lithography technology. Also, the inherent need for a physical barrier to surround Cu and prevent poisonous out-diffusion imposes an electrical limit on the ability to scale. Best practices today include an explicit hierarchy of dimensions and a stacking-order for on-chip interconnects: local between nearby transistors, global between functional blocks, as well as input/output (I/O) and power/ ground connections. With advanced logic chips having >12 levels of on-chip copper metallization, only the bottom-most are at the tightest pitch. Table1 (courtesy of imec) shows the hierarchy of interconnect signals for a 14nm-node finFET logic chip, and the tightest pitch is 42nm as used for the vertical gate contacts as well as for the metal-1 (M1) and metal-2 (M2) levels. The last published International Technology Roadmap for Semiconductors (ITRS) chapter for Interconnects that included detailed tables of on-chip metal specifications was published in 2012. In the ITRS 2012 Interconnect chapter Table 2 on microprocessor (MPU) requirements, the “Intermediate Wires” specification for Metal 2 (M2) is the same as for Metal 1 (M1) level and shows 32nm half-pitch is manufacturable, which is used with MPU physical gate lengths of 22nm.

interconnects table

FIGURE 1 shows the fraction of the intermediate wire volume that is Cu depending on the thickness of the barrier for succeeding generations of high-performance (HP) MPUs. Note that in the SEM cross-section on the right that the 10nm of Cu is only 50% of the line thickness, and that such a line would be extremely susceptible to current-crowding and premature circuit failure due to electro-migration (EM).

interconnects 1

In minimally-scaled Cu wiring, resistivity increases arise due to electron scattering from the sidewalls and grain boundaries. Tricky process integration involving electro-chemical deposition (ECD) of the Cu along with careful thermal annealing is already being used to grow large columnar grains across the trench—resembling bamboo when cut in cross-section—to minimize the volume of grain-boundaries. Forming columnar lines of single Cu grains after ECD requires control of barrier atomic-layer deposition (ALD) parameters, along with chemical-mechanical planarization (CMP) and rapid-thermal annealing (RTA) processes.

When engineering materials, first-order parameters to be controlled include composition and uniformity, while second-order parameters include internal structure such as crystal orientation or average crystal grain-size in multi-crystalline structures. In general, it is more difficult and far more expensive to control second-order parameters in manufacturing, and when engineering at the atomic scale it is yet more difficult to control third- order parameters such as grain boundary orientation.

Since the industry must control third-order parameters to continue using Cu metal, there has been ongoing R&D of non-metallic materials that could be integrated into ICs as on-chip conductors. Superconductors have been found that can exhibit zero resistance to electric current flow, but only when they are frozen to extremely low temper- atures such that phonon vibrations within their lattices settle out. Recently, a team of six Japanese research groups tested nearly 1000 materials over a four year period and found no superconductors with critical temperatures (Tc) above the 298°K of room temperature.

The rapid increase in resistivity when Cu lines are scaled to minimal dimensions motivates the search for “ballistic” conductors which are immune from electron scattering effects. While R&D into graphene and Carbon Nano-Tubes (CNT) as on-chip conductors continues, there are inherent issues with integrating any such technologies into high-volume manufacturing (HVM) to achieve superior performance compared to legacy Cu. The ITRS 2012 Interconnects chapter summarizes the issues:

Ballistic transport in one dimensional systems, such as silicides, carbon nano tubes, nanowires, graphene nanoribbons or topological insulators offers potential solutions. While ballistic transport has many advantages in narrow dimensions, most of these options incur fundamental, quantized resistances associated with any conversions of transport media, such as from Cu to CNTs. In addition to the quantum resistance, the technological problems of utilizing an additional conduction medium with its interface, substrate and integration issues, pose substantial barriers to the imple- mentation of ballistic transport media.

Imec recently published preliminary “7nm-node” finFET specifications for logic ICs having 14nm gate lengths, with expectation that delays in the implementation of EUV lithography call for use of multiple-patterning using 193-immersion (193i). M1 layer patterning at 18nm half-pitch can be done with self-aligned double- patterning (SADP) technology, while Litho-Etch-Litho- Etch (LELE) patterning with two masks allows for 24nm half-pitch patterning of more arbitrary 2D shapes for easier routing. Going to tighter half-pitches will require Litho-Etch-Litho-Etch-Litho-Etch (LELELE) with three masks, or self-aligned quadruple patterning (SAQP) schemes, which is why the number of metal levels for logic continues to increase with each successive node.

In memory chips with regular bit arrays for storage and orthogonal bit:word architectures, leading 3D architectures use similar metal interconnect half-pitches. FIGURE 2 shows a new 3D stacked NAND Flashmemoryarchitecturethatwill be shown at the 2015 IEEE International Electron Device Meeting (IEDM) in presentation 3.2, “A Novel Double-Density, Single-Gate Vertical Channel (SGVC) 3D NAND Flash That Is Tolerant to Deep Vertical Etching CD Variation and Possesses Robust Read-disturb Immunity,” by Hang-Ting Lue et al. of Macronix.

interconnects 2

The Metal Level 2 Bit Line (ML2 BL) half-pitch of ~25nm in parallel lines in this 3D NAND structure can be formed with SADP litho. Since SADP has been used in HVM of 2D NAND cells, presumably the complex SADP integrated process flow has already been established. Imec has shown ability to reach 18nm half-pitch with SADP 193i, so this new 3D NAND structure might be able to be shrunk by a “half-node” without having to re-engineer the ML2 BL fab process flow.

Even if the lithographic cost of scaling metal lines to <18nm half-pitch could be managed, the Cu barrier provides a functional limit as shown in Fig. 1. Assuming that Cu multi-level interconnects will be current-limited and will require ~3nm barriers—to prevent out-diffusion from the line as well as EM-induced diffusion within the line—the industry is already considering atomic limits. The barrier would be ~1/3 of 18nm, ~1/2 of 12nm, and ~2/3 of 9nm wide Cu lines.

It is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating.

BY KEITH BEST, Rudolph Technologies, Wilmington, MA, and PHILLIP HOLMES, TEL NEXX, Billerica, MA

Recent years have seen rapid development in the area of advanced packaging. In general, advanced packaging processes are concerned with the interconnection of multiple chips in a single package to provide increased functionality and performance in a smaller volume. System Scaling Technology — the combination of front-end, middle-end and back-end to advance microelectronic systems—utilizes many different advanced packaging approaches, one of which is known as 2.5D packaging. The term “2.5D packaging” has not always been used consistently in literature. The definition used for the purpose of this paper can be summarized as follows: a 2.5D package utilizes an interposer between multiple silicon die and a system-in-package (SiP) substrate, where this interposer has through vias connecting the metallization layers on its front and back surfaces (FIGURE 1).

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

FIGURE 1. A 2.5D IC/SiP using an interposer and through vias.

 

The development of these new packaging schemes is being driven primarily by the rapid growth in mobile handheld devices such as smartphones. Often, the manufacturing processes used are adaptations of well-established front-end processes. A number of different approaches are in development or already in production, including wafer-level chip scale packaging, copper pillar bumps on through silicon vias (TSVs), fan-out wafer level processing, and many more. Of particular interest is the replacement of solder bumps by fine pitch copper pillar bumps, which has been the subject of many new system- in-package designs. Here we investigate the lithography and plating of copper pillars, with focus on heights in excess of 100μm and diameters of 25μm, in anticipation of future SiP requirements.

The increase in the number of I/O channels required by multi-chip system designs has exceeded the density and pitch capabilities that traditional solder bump processes can deliver, so that an alternative connection scheme is required. For interposers, the key enabling technology has been the development of fine pitch copper pillar bumps to provide the high-density interconnection between the interposer and the die. Copper pillar bumps provide a number of advantages over the solder bumps they are supplanting. They can deliver finer pitches, 40μm and less have been demonstrated. They also provide superior electromigration performance in applications where high current-carrying capacity is required. However, lithography and electroplating for fine pitch copper pillar bumps can be particularly challenging. The pillars are electroplated into openings in a thick layer of photoresist which exceeds the capability of most front-end tools. Typically, today’s copper pillars range from 30-50μm in height, with height to width aspect ratios from 1:1 to around 2:1 Here we describe the lithography, resist, and electroplating systems and processes required to create 5:1 aspect ratio copper pillars with heights in excess of 100μm.

Photoresist

A negative tone photoresist (JSR THB-151N) was chosen for this work. Its acrylate groups cross-link on exposure and are developed in industry standard 2.38% TMAH developer. The photoresist was spun to a thickness of 120μm on 300mm silicon wafers with an under bump metallization (UBM) prepared seed layer. To reach the 120μm photoresist film thickness, two coatings of photoresist were required, soft baked at 130C, 300secs and 130C, 360secs respectively. After coating, the photo- resist film was allowed to rehydrate for one hour prior to exposure on a wafer stepper (Rudolph Technologies’ JetStep System).

Lithography

We used a customized test reticle that included a wide range of sizes and pitches to expose the wafer. When processing a thick photoresist, well-controlled sidewall angles are a critical requirement, especially when electroplating tall copper pillars. Most front-end tools have high numerical aperture (NA) lenses with low depth of focus (DOF) that prevent adequate exposure of thick films with sufficient image contrast to meet the sidewall angle and resolution requirements. Mask aligners also struggle with high aspect ratio imaging, not because of their NA, but because they are unable to provide the necessary focus offset required to expose the film at high resolution, ultimately limiting their aspect ratio and sidewall angle control. Although photoresist sidewall angles are primarily a function of the photoresist material and its processing (pre-bake, post-bake, developing, etc.), the exposure system plays an important role. Accurate focus control across the wafer or substrate is required to achieve consistent and accurate CD control with straight and perpendicular sidewalls.

The lithography stepper employed in this study refocuses for each exposure to ensure optimal focal plane height on advanced packaging substrates that are frequently warped by film stress and thermal cycling. The system’s 0.1 NA provides a large depth of focus to maintain image integrity and CD control through thick films. The stepper lens is achromatized and the installed “filter wheel” provides a choice of illumination wavelengths to expose the photoresist layers: “broadband” ghi (350-450nm), gh (390 to 450nm) or i-line (365nm). This study, with a photoresist thickness of 120μm, required high energy illumination of >1000 mJ/cm<sup>2</sup>, so broadband illumi- nation (g,h,i wavelengths) was employed to maintain high throughput.

The coated wafers were exposed using a focus exposure matrix wafer layout which provided a large number of programmed focus and exposure conditions at a fixed stepping distance to enable quick and efficient character- ization of the lithography process window for any pillar CD. After exposure, the wafers were developed for a total time of 180 secs, using 6 puddles in 2.38% TMAH. A number of wafers were processed in this way to provide images of the resist structures prior to the electroplating process. The SEM micrograph in FIGURE 2 shows a cross section of the photoresist via mold structures, the CD limit appears to be 25μm with this process, since the via is not open to the seed metal beyond this resolution.

lithography 2

It is interesting to note how the sidewall angle of the photoresist changes with decreasing CD suggesting that the plating will generate a “pedestal” type of copper pillar base at larger CDs, becoming progressively more vertical at smaller CDs. However, upon closer inspection of the smallest CDs, a slight “footing” can be observed at the base of the via (FIGURE 3), and this could result in slight undercut of the final copper pillar. The footing effect was most likely the result of our unoptimized develop process.

lithography 3

Electroplating

After the lithography processing, the wafers were sent to TEL NEXX for electroplating. The plating process employed the TEL NEXX Stratus P300 System, a fully automated electrochemical deposition system for advanced wafer-level packaging applications. The system deposits thick metal layers for wafer bumping, redistribution layers, TSVs, integrated passives, and MEMS.

In this study, we used a methanesulfonic acid copper chemistry with organic additives. The bath composition, operating temperature and current waveform were optimized for high speed copper plating into very thick resist features with flat bump profiles. After plating the photoresist was stripped using an immersion bath with EKC162 solution at 60 degrees. To preserve the profile of the photoresist mold the seed layer was not etched. The final copper pillar structures exhibit the inverse photo- resist mold profile (FIGURE 4).

lithography 4

The electroplating process successfully deposited copper in the photoresist via “molds” that were open to the copper seed material, producing good quality copper pillars with a final minimum copper pillar CD of 20μm, indicating a process bias of 5μm. This bias enabled the final copper pillar to reach a 6:1 aspect ratio as shown in FIGURE 5.

lithography 5

The final copper pillars exhibit excellent sidewall angle, 90 degrees for the smaller CDs. The profiles correlate well with the profiles observed in the photoresist SEM cross sections. The change in profile at the base of the photoresist for the smaller CDs did result in a slight undercut of the final copper pillar. The removal of this photoresist foot could be achieved by either increasing the de-scum time or modifying the develop recipe. The larger copper pillars tended to flare out slightly at the base (FIGURE 6) compensating for any undercut. This will benefit the structure during the removal of the copper seed layer.

lithography 6

The rheology of the copper pillar surface is very important for bonding reliability and the uniform plating of Sn solder, which was not performed during this particular study since it was not the primary objective. FIGURE 7 shows the flat top surface of a copper pillar which is free of voids and defects.

lithography 7

For advanced packaging applications, precise copper pillar height control is essential, and lithography CD control plays an important part in the plating process since CD variation directly affects plated height. The electroplating rate is proportional to current per unit area, i.e. the open area at the bottom of the photoresist openings at the beginning of the process, and the area of the evolving metal surface during deposition. Variation in CD or sidewall angle across the wafer will result in a corresponding change in copper pillar height. For example, in the case of copper pillar features a 5% change in CD can cause a 10% change in plated height.

Conclusion

The results of this study prove that it is possible to fabricate copper pillars more than 100μm in height, with aspect ratios up to 6:1, using advanced packaging stepper lithography in conjunction with electroplating. As advanced packaging requirements continue to evolve, the ability to create smaller copper pillar CDs at finer pitches in thick films will provide increased I/O density opportunities for SiP designers. Furthermore, it is clear that achieving high yield and reliability in the final package requires precise CD control throughout the entire photoresist profile to ensure consistent copper pillar height.

KEITH BEST is director applications engineering at Rudolph Technologies, Wilmington, MA. PHILLIP HOLMES is director of technology at TEL NEXX, Billerica, MA

Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance.

BY JAIMAL WILLIAMSON, Texas Instruments, Dallas, TX

Managing an organization in an orderly and disciplined manner is known as “running a tight ship.” This mentality and discipline cannot be understated with build-up substrate supplier capability and manufacturing tolerances as it relates reliability and margin in a flip chip ball grid array (FCBGA) device. Build-up substrate technology is the backbone for flip chip packaging due to its ability to bridge high density interconnects and functionality enabling improved electrical performance in tandem with the semiconductor chip. Alternating metal and dielectric layers build up the substrate into the final composite structure. The range of thicknesses of the aforementioned metal and dielectric layers are dependent on associated substrate manufacturer design rules, which can have an impact on board level reliability (BLR). Having a keen awareness of substrate supplier design rules can aid not only troubleshooting, but improve understanding of reliability margin from a chip to package interaction standpoint for any array of commercial and automotive FCBGA applications.

Influence of copper and dielectric layers on reliability

To better understand the thickness variation impact of bottommost substrate copper (Cu) metal (15 +/- 5μm) and dielectric (30 +/-6μm) layers as it relates to strain energy density of BGA solder joint at die shadow area and package corner, a 3×3 factorial design of experiments (DoE) approach (FIGURE 1) was pursued. Through the use of finite elemental modeling, outputs of the study included both strain energy density under -40°C to 125°C and 0°C to 100°C BLR temperature cycle conditions and changes in coefficient of thermal expansion (CTE) as Cu metal and dielectric thicknesses varied. For the remainder of the article, results from the more stringent -40°C to 125°C BLR temperature cycle condition will be discussed.

FIGURE 1. 3x3 factorial DoE.

FIGURE 1. 3×3 factorial DoE.

Rationale of the study was based on a striking difference in BLR performance from two FCBGA daisy chain test vehicles having an identical substrate design, but manufactured at two different substrate suppliers (noted as supplier A and B in this article). The FCBGA daisy chain test vehicle comprises the following package attributes (see FIGURE 2 for a side view example):
• 40mm x 40mm body size
• 8-layer build-up stack (3/2/3)
• 400μm core thickness
• 1mm BGA pitch

FIGURE 2. Example of FCBGA package.

FIGURE 2. Example of FCBGA package.

Weibull analysis was generated from empirical BLR results at 5 percent and 63.2 percent cycles to failure. Specifically, at 5 percent cycles to failure supplier A exhibits ~25 percent reduced BGA solder joint fatigue life than counterparts from supplier B (as illustrated in FIGURES 3 and 4).

FIGURE 3. Weibull plot of supplier A.

FIGURE 3. Weibull plot of supplier A.

FIGURE 4. Weibull plot of supplier B.

FIGURE 4. Weibull plot of supplier B.

In a similar study focusing on component level reliability (CLR), it was observed that bottommost substrate Cu layer thickness can impact stress underneath die shadow area. For these reasons, a more detailed examination was done to measure bottommost substrate Cu layer thickness from daisy chain units of suppliers A and B. Based on package construction analysis, supplier A was found to target the nominal value of 15μm; whereas supplier B targeted the high end of specification at 20μm. These Cu thickness differences would play a significant role in the BLR results.

Stress modeling results

Outputs of the finite elemental modeling are revealed in FIGURE 5 based on inputs from the aforementioned 3×3 factorial DoE illustrated in Fig. 1. Based on the combi- nation of various Cu and dielectric layer thicknesses evaluated, thicker dielectric and Cu layers yield higher macroscopic CTE values. This is an expected trend based on CTE material properties of Cu and dielectric layers in relation to the substrate core material. Simulation results confirmed CTE in ascending order is: dielectric layer > Cu layer > substrate core. Comparing Weibull analysis from supplier A and B (figures 3 and 4), DoE legs 4 and 6 match best, respectively, to the empirical BLR results. In addition, DoE legs 4 and 6 align with the bottommost substrate Cu layer thickness values from the aforemen- tioned package construction analysis measurements. It is noted that based on modeling results, an approximately 2 percent change in CTE can swing the cycles to failure at 63.2 percent by ~11 percent. DoE leg 4 focuses on nominal Cu thickness of 15μm; whereas leg 6 focuses on the high end of the Cu thickness tolerance at 20μm. Dielectric thickness is nominal value of 30μm in both DoE cases. Improved BLR performance from supplier B is attributed to the thicker Cu providing a better CTE match to the BLR test board.

FIGURE 5. Finite elemental modeling results.

FIGURE 5. Finite elemental modeling results.

Use of JMP for statistical perspective

As a supplemental tool for data interpretation, JMP statistical analysis was performed to illustrate how nominal and extreme values of the metal and dielectric layer thickness specification affect FCBGA BLR performance. Analyzing the strain energy data outputs, the model fit well to the predicted values as shown in FIGURE 6. Similarly, CTE correlated well with predicted values as illustrated in FIGURE 7. Use of the prediction profiler function, as illustrated in FIGURE 8, shows CTE is proportional to increase in metal and dielectric thickness, which correlates with the stress modeling results.

FIGURE 6. JMP model of SED predicted vs. actual.

FIGURE 6. JMP model of SED predicted vs. actual.

FIGURE 7. JMP model of CTE predicted vs. actual.

FIGURE 7. JMP model of CTE predicted vs. actual.

FIGURE 8. CTE prediction as a function of metal and dielectric thickness

FIGURE 8. CTE prediction as a function of metal and dielectric thickness

Summary

Subtleties in thicknesses between the alternating Cu metal and dielectric layers within a build-up substrate can impact BLR performance. Two identical daisy chain substrate designs manufactured by different suppliers were compared head to head. A detailed package construction analysis revealed differences in bottommost Cu thickness layer within the substrate. This Cu thickness delta between the two substrate designs caused a change in CTE with supplier B (higher value) than supplier A due to thicker copper. Finite element modeling demon- strated relatively small macroscopic changes in CTE on the order of less than 2 percent can affect cycles to failure by 11 percent.

The key takeaway found from the head to head evaluation was supplier A producing a more stable process as it was able to meet the center point of the Cu thickness specification as compared to supplier B, which was off target. However, in essence, supplier A lost the head to head BLR comparative study with supplier B as its accuracy in meeting the Cu thickness target caused reduced solder joint fatigue life. The typical corrective action would be to work with supplier B to establish better tolerance control in their Cu plating process to stabilize Cu thickness at the center or nominal value like supplier A. However, the lesson learned was to tailor and control the Cu thickness at the higher end of the specification to improve reliability performance. Typically, in any setting the criteria of success is to hit the bullseye or target, which supplier A achieved. Conversely, supplier B missed this mark with results that were skewed to the right. Ironically, because of the skewed results off-target reliability margin was obtained. In reflection of these findings, the adage “success is in the eyes of the beholder” has never been more poignant.

JAIMAL WILLIAMSON is a packaging engineer responsible for development and qualification of Embedding Processing FCBGA devices within Texas Instruments’ Worldwide Semiconductor Packaging group.

CEA-Leti today announced it has developed two techniques to induce local strain in FD-SOI processes for next-generation FD-SOI circuits that will produce more speed at the same, or lower, power consumption, and improve performance.

The local-strain solutions are dual-strained technologies: compressive SiGe for PFETs and tensile Si for NFETs. In addition to clearing the path to improved performance in FD-SOI technology, they preserve its excellent electrostatic integrity and its in situ performance tunability, due to back biasing.

The two techniques Leti developed can induce local stress as high as 1.6 GPa in the MOSFETs channel.

The first relies on strain transfer from a relaxed SiGe layer on top of SOI film. In a recent paper in the ECS Journal of Solid State Science and Technology, Leti researcher Sylvain Maitrejean described how with this technique he was able to boost the short-channel electron mobility by more than 20 percent compared to unstrained reference. This shows significant promise for enhancing the on-state currents of CMOS transistors and thus for improving the circuit’s speed.

The second technique is closer to strain memorization methods and relies on the ability of the BOX to creep under high-temperature annealing. At SSDM 2015 in Japan, Leti researchers showed that with this local-stress technique they can turn regular unstrained SOI structures into tensile strained Si (sSOI), for NFET areas. Moreover, this “BOX-creep” process also can also be applied to compressive strain creation, as presented at the 2015 Silicon Nanoelectronics Workshop (SNW) conference.

Strained channels enable an increase in the on-state current of CMOS transistors. As a result, the corresponding IC circuits can deliver more speed at the same power, or reduced consumed power and longer battery life at the same performance.

They also have been proven to be an effective way to increase performance of n and p MOSFET transistors via mobility enhancement of electrons and holes. These kinds of techniques enable boosting of the carrier transport in the CMOS channels, and thus increasing the on-state currents. Beginning with the 90nm node, this strain option has been one of the main approaches of the microelectronics industry for improving the IC speed in bulk transistors. While it was not necessary at the 28nm node for FD-SOI, it becomes mandatory beyond the 22/20nm node.

“Leti has continuously focused on improving and fine-tuning FD-SOI technology’s inherent advantages, since pioneering the technology 20 years ago,” said Maud Vinet, head of Leti’s Advanced CMOS Laboratory. “These two new techniques broaden the capabilities of Leti’s FD-SOI platform for next-generation devices, and further position the technology to be a vital part of the Internet of Things and electronics products of the future.”

SSDM 2015: Stress profile from 2D Raman extractions for Si MESAs after BOX creep process with 50nm thick SiN

SSDM 2015: Stress profile from 2D Raman extractions for Si MESAs after BOX creep process with 50nm thick SiN

NXP Semiconductors N.V. and Freescale Semiconductor, Ltd. announced the completion of the merger pursuant to the terms of the previously announced merger agreement from March 2015. The merger has created a high performance mixed signal semiconductor industry leader, with combined revenue of over $10 billion. The merged entity will continue operations as NXP Semiconductors N.V. and has become the market leader in automotive semiconductor solutions and in general purpose microcontroller (MCU) products.

“Through this merger we have created an industry powerhouse focused on the high growth opportunities in the Smarter World, capitalizing on the emerging opportunities offered by the accelerating demand for connectivity, processing and security. Today’s formation of the new NXP is a transformative step on our journey to become the industry leader in high performance mixed signal solutions,” said Rick Clemmer, NXP Chief Executive Officer. “This merger enables us to deliver more complete solutions to our customers as we are emerging as the leader in the Secure Connections – and the supporting infrastructure – for the Smarter World domain. As a result, we reiterate today that we fully expect to continue to significantly out-grow the overall market, drive world-class profitability and generate even more cash, allowing us to continue creating significant value for NXP’s shareholders.”

As previously announced, the transaction is expected to be accretive to NXP non-GAAP earnings in 2016, and NXP anticipates achieving cost savings of $200 million in 2016 with a clear path to $500 million of annual cost synergies.

NXP also today announced the closing of the divestiture of its RF Power business to Jianguang Asset Management Co. Ltd (“JAC Capital”), after receiving official confirmation that JAC Capital has deposited the required funds at its bank in China to pay the purchase price. The cash proceeds for the sale will be received later this month following the required regulatory filings for cross-border transfers of funds from China. NXP has obtained bridge financing until the funds are received.

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NXP-Freescale merger to result in world’s eighth largest chip maker

Freescale and NXP agree to $40 Billion merger

Historic era of consolidation for chip makers

CEA-Leti today announced preliminary steps for demonstrating a quantum bit, or qubit, the building block of quantum information, in a process utilizing a silicon-on-insulator (SOI) CMOS platform.

While the leading solid-state-based approach today for treating quantum information uses superconducting qubits, there are several potential alternatives. These include semiconductor spin qubits, historically demonstrated in III-V materials, but with limited “lifetime” due to coupling between the electron spin and the nuclear spins of the III-V elements.

Only in recent years has the prospect of using nuclear spin-free, isotopically purified silicon-28, the most-common isotope, made silicon an especially attractive candidate for hosting electron spin qubits with a long quantum coherence time. The main challenge now is defining an elementary cell compatible with circuit upscaling to hundreds of qubits and more.

Leti and its long-time research partner Inac, a fundamental research division of CEA, are investigating a silicon-on-insulator (SOI) technology for quantum computing with proven scalability, since it was originally developed for CMOS VLSI circuits. In this approach, quantum dots are created beneath the gates of n-type (respectively p-type) field effect transistors, which are designed to operate in the “few-electron” (respectively “few-hole”) regime at cryogenic temperatures (below 0.1 K).

Leti and Inac have developed a process for mastering control of the operation of both types of devices using Leti’s SOI nanowire FET technology. Their teams have demonstrated the co-integration and successful operation of quantum objects with conventional CMOS control electronics (standard ring oscillators) on 300mm SOI substrates.

“This technology has acquired a certain degree of robustness, and we aim at using it with very minor modifications to demonstrate qubits co-integrated with their control electronics,” said Louis Hutin, scientific staff. “This co-integration success represents a critical asset for the eventual design of a quantum computer.”