Yearly Archives: 2015

CEA-Leti today announced it has signed an agreement with Keysight Technologies, a device-modeling software supplier, to adapt Leti’s UTSOI extraction flow methodology within Keysight’s device modeling solutions for high-volume SPICE model generation.

The simulation of the Leti-UTSOI compact model, which is the first complete compact model dedicated to Ultra-Thin Body and Box and Independent Double Gate MOSFETs, is currently available in Keysight’s modeling and simulation tools. This agreement expands the collaboration to include the extraction flow and will enable device-modeling engineers to efficiently create Leti-UTSOI model cards for use in Process Design Kits (PDKs).

“This collaboration between Leti and Keysight will strengthen the global FD-SOI ecosystem by providing an automatic extraction flow for building model cards associated with the Leti-UTSOI models, which are already available in all the major SPICE simulators,” said Marie Semeria, Leti’s CEO. “This professional, automatic extraction-flow solution will address designers’ needs as they weigh FD-SOI’s benefits over competing solutions for the 28nm technology node and below.”

“Keysight’s modeling solutions provide both automation and flexibility for device modeling,” said Todd Cutler, general manager of Keysight EEsof EDA. “The addition of a Leti-UTSOI modeling technology will further expand our offering in CMOS modeling. We have been collaborating with Leti on many projects, and we are pleased to extend our relationship to improve access to the Leti-UTSOI.”

One of the greatest challenges in the evolution of electronics has been to reduce power consumption during transistor switching operation. In a study recently reported in Nature, engineers at University of California, Santa Barbara, in collaboration with Rice University, have demonstrated a new transistor that switches at only 0.1 volts and reduces power dissipation by over 90% compared to state-of-the-art silicon transistors (MOSFETs).

MOSFETs have been the building blocks of everyday electronic products since the 1970s. However, to sustain the ever-growing need for increased transistor densities, miniaturization of MOSFETs has given rise to a power dissipation challenge due to the fundamental limitations of their turn-on characteristics.

“The steepness of a transistor’s turn-on is characterized by a parameter known as the subthreshold swing, which cannot be lowered below a certain level in MOSFETs,” explained Kaustav Banerjee, Professor of Electrical and Computer Engineering at UC Santa Barbara. A minimum gate voltage change of 60 millivolts at room temperature is required to change the current by a factor of ten in MOSFETs. In essence, the existing state of transistor technology limits the energy efficiency potential of digital circuits in general.

The research group of Professor Kaustav Banerjee at UC Santa Barbara took a new approach to subverting this fundamental limitation. They employed the quantum mechanical phenomenon of band-to-band tunneling to design a tunnel field effect transistor (TFET) with sub-60mV per decade of subthreshold swing.

“We restructured the transistor’s source to channel junction to filter out high energy electrons that can diffuse over the source/channel barrier even in the off state, thereby making the off state current negligibly small,” explained Banerjee. At UCSB, Banerjee’s Nanoelectronics Research Lab includes Deblina Sarkar, Xuejun Xie, Wei Liu, Wei Cao, Jiahao Kang, and Stephan Kraemer, as well as Yongji Gong and Pulickel Ajayan of Rice University.

Banerjee and his colleagues are motivated by a global electronics industry that loses billions of dollars each year to the impact of power dissipation on chip cost and reliability. “This translates into lower battery lifetime in personal devices like cell phones and laptops, and massive power consumption of servers in large data centers,” adds Banerjee, pointing out the global scale of this energy demand.

An industry that relies on conventional semiconductors such as silicon or III-V compound semiconductors as the channel material for TFETs, Banerjee explains, “faces limitations because these materials have high density of surface states, which increase leakage current and degrade the subthreshold swing.”

The TFET designed by the UCSB team overcame this challenge in a few ways, most significant being the use of a layered two-dimensional (2D) material called molybdenum disulphide (MoS¬2). As the current-carrying channel placed over a highly doped germanium (Ge) as the source electrode, MoS2 offers an ideal surface and thickness of only 1.3nm. The resulting vertical heterostructure provides a unique source-channel junction that is strain-free, has a low barrier for current-carrying electrons to tunnel through from Ge to MoS¬2 through an ultra-thin (~0.34nm) van der Waals gap, and a large tunneling area.

“The crux of our idea is to combine 3D and 2D materials in a unique heterostructure, to achieve the best of both worlds. The matured doping technology of 3D structures is married to the ultra-thin nature and pristine interfaces of 2D layers to obtain an efficient quantum-mechanical tunneling barrier, which can be easily tuned by the gate,” commented Deblina Sarkar, lead author of the paper and PhD student in Banerjee’s lab.

“We have engineered what is, at present, the thinnest-channel subthermionic transistor ever made,” said Banerjee. Their atomically-thin and layered semiconducting channel tunnel FET (or ATLAS-TFET) is the only planar architecture TFET to achieve subthermionic subthreshold swing (~30 millivolts/decade at room temperature) over four decades of drain current, and the only one in any architecture to achieve so at an ultra-low drain-source voltage of 0.1V.

Ajayan, co-author and professor of chemical and biomolecular engineering at Rice University, commented, “This is a remarkable example showing the uniqueness of 2D atomic layered materials that enables device performance which conventional materials will not be able to achieve. This is perhaps the first breakthrough in a series of novel devices that people will now aspire to build using 2D materials.”

“The work is a significant step forward in the search for a low voltage logic transistor. The demonstration of sub-thermal operation over four orders of magnitude is impressive, and the on-current also advances the state-of-the-art. There is still a long ways to go, but this work demonstrates the potential of 2D materials to realize the long-sought, low-voltage device,” commented Mark Lundstrom, professor of electrical and computer engineering at Purdue University.

“We have demonstrated how to achieve the most important metric of steep subthreshold swing that meets ITRS requirements. Our transistor can be utilized for a number of low-power applications including arenas where the steep subthreshold swing is the main requirement, such as biosensors or gas sensors. With improved performance, the range of applications of this transistor can be further expanded,” explained Wei Cao, a PhD student in Banerjee’s group and a co-author of the article.

“This work represents an important step of bringing 2D materials closer to real applications in electronics. The use of 2D materials in tunneling transistors started only recently, and this paper gives the whole field yet another strong boost in improving the characteristics of such devices even further,” commented Dr. Konstantin Novoselov, a professor of physics at University of Manchester. Novoselov was co-recipient of the 2010 Nobel Prize in Physics, awarded for the discovery of graphene.

“When I first heard Banerjee’s idea of using 2D materials for designing inter-band tunneling transistors in 2012, I recognized its merit and immense potential for ultra-low power electronics. I am pleased to see that his vision has been realized,” commented James Hwang, professor of electrical engineering at Lehigh University, who was then the AFOSR program manager responsible for funding this research.

The Semiconductor Industry Association (SIA) announced worldwide sales of semiconductors reached $29.0 billion for the month of October 2015, 1.9 percent higher than the previous month’s total of $28.4 billion and 2.5 percent lower than the October 2014 total of $29.7 billion. The Americas market posted 3.9 percent growth compared to last month, leading all regions. All monthly sales numbers are compiled by the World Semiconductor Trade Statistics (WSTS) organization and represent a three-month moving average. Additionally, a new WSTS industry forecast projects slight market growth for the next three years.

“Global semiconductor sales have shown signs of stabilizing in recent months, with October marking the third straight month of month-to-month growth,” said John Neuffer, president and CEO, Semiconductor Industry Association. “Year-to-date sales are narrowly ahead of where they were through the same time last year, and slight growth is projected for next year and beyond.”

Month-to-month sales increased across all regional markets: the Americas (3.9 percent), China (1.6 percent), Europe (1.2 percent), Japan (0.4 percent), and Asia Pacific/All Other (1.7 percent). Compared to October 2014, sales were up in China (5.7 percent), but down in the Americas (-5.6 percent), Europe (-9.4), Japan (-10.5 percent), and Asia Pacific/All Other (-2.4 percent).

Additionally, SIA endorsed the WSTS Autumn 2015 global semiconductor sales forecast, which projects the industry’s worldwide sales will reach $336.4 billion in 2015, a 0.2 percent increase from the 2014 sales total. WSTS projects year-to-year increases for 2015 in Asia Pacific (3.9 percent), with decreases projected for the Americas (-0.6 percent), Europe (-8.2 percent), and Japan (-10.3 percent).

Beyond 2015, the global market is expected to grow at a modest pace. WSTS forecasts 1.4 percent growth globally for 2016 ($341.0 billion in total sales) and 3.1 percent growth for 2017 ($351.6 billion). WSTS tabulates its semi-annual industry forecast by convening an extensive group of global semiconductor companies that provide accurate and timely indicators of semiconductor trends.

October 2015

Billions

Month-to-Month Sales                               

Market

Last Month

Current Month

% Change

Americas

5.82

6.05

3.9%

Europe

2.87

2.90

1.2%

Japan

2.69

2.70

0.4%

China

8.45

8.58

1.6%

Asia Pacific/All Other

8.58

8.72

1.7%

Total

28.41

28.96

1.9%

Year-to-Year Sales                          

Market

Last Year

Current Month

% Change

Americas

6.41

6.05

-5.6%

Europe

3.21

2.90

-9.4%

Japan

3.01

2.70

-10.5%

China

8.12

8.58

5.7%

Asia Pacific/All Other

8.94

8.72

-2.4%

Total

29.68

28.96

-2.5%

Three-Month-Moving Average Sales

Market

May/Jun/Jul

Aug/Sept/Oct

% Change

Americas

5.51

6.05

9.7%

Europe

2.83

2.90

2.5%

Japan

2.63

2.70

2.3%

China

8.18

8.58

5.0%

Asia Pacific/All Other

8.71

8.72

0.2%

Total

27.87

28.96

3.9%

Imec, the nano electronics research center and Coventor, a supplier of semiconductor process development tools, today announced the expansion of a joint development project to explore process variation issues in 7nm semiconductor technology.

For over a year, the joint team has been using Coventor’s semiconductor process modeling platform, SEMulator3D, to perform predictive modeling of semiconductor fabrication processes and to proactively analyze process variation issues in 7nm semiconductor technology.  The collaboration has now been expanded beyond logic-only devices to include 3D NAND Flash, STT-MRAM, and other device types.

“Leveraging Coventor’s technical expertise and its SEMulator3D platform has enabled us to solve real-world semiconductor integration and processing problems at the 7nm node,” said An Steegen, senior vice president of process technology at imec.   “Our joint collaboration is helping the entire semiconductor industry lower the risks associated with moving to the latest process technologies by providing customers with proven, tested process development platforms and advancing the availability, yield and cost of next-generation semiconductor technology.”

A highlight of the collaboration has been a massive process simulation experiment to explore the effect of process variability in 7nm BEOL (back end of line) fabrication processes.   Researchers used SEMulator3D to simulate an entire window of process variability, which would have required more than one million actual semiconductor wafers if conventional testing methods were used. This experiment was made possible by the robust virtual fabrication environment of SEMulator3D using a fully codified 7nm process flow, along with the ability to support parallel distributed computing and a novel algorithm for submitting variation cases to the simulator.  With these powerful tools, the team was able to produce key findings that will help advance 7nm semiconductor technology.

“We have worked with imec to accelerate the state of the art in semiconductor process technology useful in a broad range of next-generation devices such as Logic, 3D NAND Flash, STT-MRAM, and others,” said David Fried, Chief Technical Officer at Coventor. “By providing our customers with a comprehensive virtual fabrication environment, plus our combined expertise, Coventor and imec are reducing the time and cost associated with moving to these emerging semiconductor nodes.”

A new method for building “drawbridges” between metal nanoparticles may allow electronics makers to build full-color displays using light-scattering nanoparticles that are similar to the gold materials that medieval artisans used to create red stained-glass.

“Wouldn’t it be interesting if we could create stained-glass windows that changed colors at the flip of a switch?” said Christy Landes, associate professor of chemistry at Rice and the lead researcher on a new study about the drawbridge method that appears this week in the open-access journal Science Advances.

The research by Landes and other experts at Rice University’s Smalley-Curl Institute could allow engineers to use standard electrical switching techniques to construct color displays from pairs of nanoparticles that scatter different colors of light.

For centuries, stained-glass makers have tapped the light-scattering properties of tiny gold nanoparticles to produce glass with rich red tones. Similar types of materials could increasingly find use in modern electronics as manufacturers work to make smaller, faster and more energy-efficient components that operate at optical frequencies.

Though metal nanoparticles scatter bright light, researchers have found it difficult to coax them to produce dramatically different colors, Landes said.

Rice’s new drawbridge method for color switching incorporates metal nanoparticles that absorb light energy and convert it into plasmons, waves of electrons that flow like a fluid across a particle’s surface. Each plasmon scatters and absorbs a characteristic frequency of light, and even minor changes in the wave-like sloshing of a plasmon shift that frequency. The greater the change in plasmonic frequency, the greater the difference between the colors observed.

“Engineers hoping to make a display from optically active nanoparticles need to be able to switch the color,” Landes said. “That type of switching has proven very difficult to achieve with nanoparticles. People have achieved moderate success using various plasmon-coupling schemes in particle assemblies. What we’ve shown though is variation of the coupling mechanism itself, which can be used to produce huge color changes both rapidly and reversibly.”

To demonstrate the method, Landes and study lead author Chad Byers, a graduate student in her lab, anchored pairs of gold nanoparticles to a glass surface covered with indium tin oxide (ITO), the same conductor that’s used in many smartphone screens. By sealing the particles in a chamber filled with a saltwater electrolyte and a silver electrode, Byers and Landes were able form a device with a complete circuit. They then showed they could apply a small voltage to the ITO to electroplate silver onto the surface of the gold particles. In that process, the particles were first coated with a thin layer of silver chloride. By later applying a negative voltage, the researchers caused a conductive silver “drawbridge” to form. Reversing the voltage caused the bridge to withdraw.

“The great thing about these chemical bridges is that we can create and eliminate them simply by applying or reversing a voltage,” Landes said. “This is the first method yet demonstrated to produce dramatic, reversible color changes for devices built from light-activated nanoparticles.”

Byers said his research into the plasmonic behavior of gold dimers began about two years ago.

“We were pursuing the idea that we could make significant changes in optical properties of individual particles simply by altering charge density,” he said. “Theory predicts that colors can be changed just by adding or removing electrons, and we wanted to see if we could do that reversibly, simply by turning a voltage on or off.”

The experiments worked. The color shift was observed and reversible, but the change in the color was minute.

“It wasn’t going to get anybody excited about any sort of switchable display applications,” Landes said.

But she and Byers also noticed that their results differed from the theoretical predictions.

Landes said that was because the predictions were based upon using an inert electrode made of a metal like palladium that isn’t subject to oxidation. But silver is not inert. It reacts easily with oxygen in air or water to form a coat of unsightly silver oxide. This oxidizing layer can also form from silver chloride, and Landes said that is what was occurring when the silver counter electrode was used in Byers’ first experiments.

“It was an imperfection that was throwing off our results, but rather than run away from it, we decided to use it to our advantage,” Landes said.

Rice plasmonics pioneer and study co-author Naomi Halas, director of the Smalley-Curl Institute, said the new research shows how plasmonic components could be used to produce electronically switchable color-displays.

“Gold nanoparticles are particularly attractive for display purposes,” said Halas, Rice’s Stanley C. Moore Professor of Electrical and Computer Engineering and professor of chemistry, bioengineering, physics and astronomy, and materials science and nanoengineering. “Depending upon their shape, they can produce a variety of specific colors. They are also extremely stable, and even though gold is expensive, very little is needed to produce an extremely bright color.”

In designing, testing and analyzing the follow-up experiments on dimers, Landes and Byers engaged with a brain trust of Rice plasmonics experts that included Halas, physicist and engineer Peter Nordlander, chemist Stephan Link, materials scientist Emilie Ringe and their students, as well as Paul Mulvaney of the University of Melbourne in Australia.

Together, the team confirmed the composition and spacing of the dimers and showed how metal drawbridges could be used to induce large color shifts based on voltage inputs.

Nordlander and Hui Zhang, the two theorists in the group, examined the device’s “plasmonic coupling,” the interacting dance that plasmons engage in when they are in close contact. For instance, plasmonic dimers are known to act as light-activated capacitors, and prior research has shown that connecting dimers with nanowire bridges brings about a new state of resonance known as a “charge-transfer plasmon,” which has its own distinct optical signature.

“The electrochemical bridging of the interparticle gap enables a fully reversible transition between two plasmonic coupling regimes, one capacitive and the other conductive,” Nordlander said. “The shift between these regimes is evident from the dynamic evolution of the charge transfer plasmon.”

Halas said the method provides plasmonic researchers with a valuable tool for precisely controlling the gaps between dimers and other multiparticle plasmonic configurations.

“In an applied sense, gap control is important for the development of active plasmonic devices like switches and modulators, but it is also an important tool for basic scientists who are conducting curiosity-driven research in the emerging field of quantum plasmonics.”

National Institute of Standards and Technology (NIST) researchers are seeing the light, but in an altogether different way. And how they are doing it just might be the semiconductor industry’s ticket for extending its use of optical microscopes to measure computer chip features that are approaching 10 nanometers, tiny fractions of the wavelength of light.

Using a novel microscope that combines standard through-the-lens viewing with a technique called scatterfield imaging, the NIST team accurately measured patterned features on a silicon wafer that were 30 times smaller than the wavelength of light (450 nanometers) used to examine them. They report that measurements of the etched lines–as thin as 16 nanometers wide–on the SEMATECH-fabricated wafer were accurate to one nanometer. With the technique, they spotted variations in feature dimensions amounting to differences of a few atoms.

Measurements were confirmed by those made with an atomic force microscope, which achieves sub-nanometer resolution, but is considered too slow for online quality-control measurements. Combined with earlier results, the NIST researchers write, the new proof-of-concept study* suggests that the innovative optical approach could be a “realistic solution to a very challenging problem” facing chip makers and others aiming to harness advances in nanotechnology. All need the means for “nondestructive measurement of nanometer-scale structures with sub-nanometer sensitivity while still having high throughput.

“Light-based, or optical, microscopes can’t “see” features smaller than the wavelength of light, at least not in the crisp detail necessary for making accurate measurements. However, light does scatter when it strikes so-called subwavelength features and patterned arrangements of such features. “Historically, we would ignore this scattered light because it did not yield sufficient resolution,” explains Richard Silver, the physicist who initiated NIST’s scatterfield imaging effort. “Now we know it contains helpful information that provides signatures telling us something about where the light came from.”

With scatterfield imaging, Silver and colleagues methodically illuminate a sample with polarized light from different angles. From this collection of scattered light–nothing more than a sea of wiggly lines to the untrained eye–the NIST team can extract characteristics of the bounced lightwaves that, together, reveal the geometry of features on the specimen.

Light-scattering data are gathered in slices, which together image the volume of scattered light above and into the sample. These slices are analyzed and reconstructed to create a three-dimensional representation. The process is akin to a CT scan, except that the slices are collections of interfering waves, not cross-sectional pictures.

“It’s the ensemble of data that tells us what we’re after,” says project leader Bryan Barnes.” We may not be able see the lines on the wafer, but we can tell you what you need to know about them–their size, their shape, their spacing.”

Scatterfield imaging has critical prerequisites that must be met before it can yield useful data for high-accuracy measurements of exceedingly small features. Key steps entail detailed evaluation of the path light takes as it beams through lenses, apertures and other system elements before reaching the sample. The path traversed by light scattering from the specimen undergoes the same level of scrutiny. Fortunately, scatterfield imaging lends itself to thorough characterization of both sequences of optical devices, according to the researchers. These preliminary steps are akin to error mapping so that recognized sources of inaccuracy are factored out of the data.

The method also benefits from a little advance intelligence–the as-designed arrangement of circuit lines on a chip, down to the size of individual features. Knowing what is expected to be the result of the complex chip-making process sets up a classic matchup of theory vs. experiment.

The NIST researchers can use standard equations to simulate light scattering from an ideal, defect-free pattern and, in fact, any variation thereof. Using wave analysis software they developed, the team has assembled an indexed library of light-scattering reference models. So once a specimen is scanned, the team relies on computers to compare their real-world data to models and to find close matches.

From there, succeeding rounds of analysis homes in on the remaining differences, reducing them until the only ones that remain are due to variations in geometry such as irregularities in the height, width, or shape of a line.

Measurement results achieved with the NIST approach might be said to cast light itself in an entirely new light. Their new study, the researchers say, shows that once disregarded scattered light “contains a wealth of accessible optical information.”

Next steps include extending the technique to even shorter wavelengths of light, down to ultraviolet, or 193 nanometers. The aim is to accurately measure features as small as 5 nanometers.

This work is part of a larger NIST effort to supply measurement tools that enable the semiconductor industry to continue doubling the number of devices on a chip about every two years and to help other industries make products with nanoscale features. Recently, NIST and Intel researchers reported using an X-ray technique to accurately measure features on a silicon chip to within fractions of a nanometer.

Scientists and engineers are engaged in a global race to make new materials that are as thin, light and strong as possible. These properties can be achieved by designing materials at the atomic level, but they are only useful if they can leave the carefully controlled conditions of a lab.

Researchers at the University of Pennsylvania have now created the thinnest plates that can be picked up and manipulated by hand.

Even though they are less than 100 nanometers thick, the researchers’ plates are strong enough to be picked up by hand and retain their shape after being bent and squeezed. Credit: University of Pennsylvania

Despite being thousands of times thinner than a sheet of paper and hundreds of times thinner than household cling wrap or aluminum foil, their corrugated plates of aluminum oxide spring back to their original shape after being bent and twisted.

Like cling wrap, comparably thin materials immediately curl up on themselves and get stuck in deformed shapes if they are not stretched on a frame or backed by another material.

Being able to stay in shape without additional support would allow this material, and others designed on its principles, to be used in aviation and other structural applications where low weight is at a premium.

The study was led by Igor Bargatin, the Class of 1965 Term Assistant Professor of Mechanical Engineering and Applied Mechanics in Penn’s School of Engineering and Applied Science, along with lab member Keivan Davami, a postdoctoral scholar, and Prashant Purohit, an associate professor of mechanical engineering. Bargatin lab members John Cortes and Chen Lin, both graduate students; Lin Zhao, a former student in Engineering’s nanotechnology master’s program; and Eric Lu and Drew Lilley, undergraduate students in the Vagelos Integrated Program in Energy Research, also contributed to the research.

They published their findings in the journal Nature Communications.

“Materials on the nanoscale are often much stronger than you’d expect, but they can be hard to use on the macroscale” Bargatin said. “We’ve essentially created a freestanding plate that has nanoscale thickness but is big enough to be handled by hand. That hasn’t been done before.”

Graphene, which can be as thin as a single atom of carbon, has been the poster-child for ultra-thin materials since it’s discovery won the Nobel Prize in Physics in 2010. Graphene is prized for its electrical properties, but its mechanical strength is also very appealing, especially if it could stand on its own. However, graphene and other atomically thin films typically need to be stretched like a canvas in a frame, or even mounted on a backing, to prevent them from curling or clumping up on their own.

“The problem is that frames are heavy, making it impossible to use the intrinsically low weight of these ultra-thin films,” Bargatin said. “Our idea was to use corrugation instead of a frame. That means the structures we make are no longer completely planar, instead, they have a three-dimensional shape that looks like a honeycomb, but they are flat and contiguous and completely freestanding.”

“It’s like an egg carton, but on the nanoscale,” said Purohit.

The researchers’ plates are between 25 and 100 nanometers thick and are made of aluminum oxide, which is deposited one atomic layer at a time to achieve precise control of thickness and their distinctive honeycomb shape.

“Aluminum oxide is actually a ceramic, so something that is ordinarily pretty brittle,” Bargatin said. “You would expect it, from daily experience, to crack very easily. But the plates bend, twist, deform and recover their shape in such a way that you would think they are made out of plastic. The first time we saw it, I could hardly believe it.”

Once finished, the plates’ corrugation provides enhanced stiffness. When held from one end, similarly thin films would readily bend or sag, while the honeycomb plates remain rigid. This guards against the common flaw in un-patterned thin films, where they curl up on themselves.

This ease of deformation is tied to another behavior that makes ultra-thin films hard to use outside controlled conditions: they have the tendency to conform to the shape of any surface and stick to it due to Van der Waals forces. Once stuck, they are hard to remove without damaging them.

Totally flat films are also particularly susceptible to tears or cracks, which can quickly propagate across the entire material.

“If a crack appears in our plates, however, it doesn’t go all the way through the structure,” Davami said. “It usually stops when it gets to one of the vertical walls of the corrugation.”

The corrugated pattern of the plates is an example of a relatively new field of research: mechanical metamaterials. Like their electromagnetic counterparts, mechanical metamaterials achieve otherwise impossible properties from the careful arrangement of nanoscale features. In mechanical metamaterials’ case, these properties are things like stiffness and strength, rather than their ability to manipulate electromagnetic waves.

Other existing examples of mechanical metamaterials include “nanotrusses,” which are exceptionally lightweight and robust three-dimensional scaffolds made out of nanoscale tubes. The Penn researchers’ plates take the concept of mechanical metamaterials a step further, using corrugation to achieve similar robustness in a plate form and without the holes found in lattice structures.

That combination of traits could be used to make wings for insect-inspired flying robots, or in other applications where the combination of ultra-low thickness and mechanical robustness is critical.

“The wings of insects are a few microns thick, and can’t thinner because they’re made of cells,” Bargatin said. “The thinnest man-made wing material I know of is made by depositing a Mylar film on a frame, and it’s about half a micron thick. Our plates can be ten or more times thinner than that, and don’t need a frame at all. As a result, they weigh as little as than a tenth of a gram per square meter.”

The Semiconductor Industry Association (SIA), representing U.S. leadership in semiconductor manufacturing, design, and research, today announced the SIA Board of Directors has elected Dr. Necip Sayiner, President, CEO and Director of Intersil, as its 2016 Chair and Tunç Doluca, President and CEO of Maxim Integrated, as its 2016 Vice Chair.

“We are thrilled to welcome Necip Sayiner as SIA’s 2016 Chair,” said John Neuffer, SIA President and CEO. “Necip has a proven record of leadership, a strong technical background, and a firm command of the challenges facing our industry – attributes that will serve him well as SIA Chair in the year ahead.”

Dr. Sayiner joined Intersil as President, CEO and Director in March 2013. Prior to joining Intersil, he served as President, CEO and Director of Silicon Laboratories from September 2005 to April 2012. Sayiner held various other leadership positions at Agere Systems Inc., which included Executive Vice President and General Manager, Enterprise and Networking Division from August 2004 to September 2005; and Vice President and General Manager, Networking ICs Division from March 2002 to August 2004. Dr. Sayiner holds a B.S. in Electrical Engineering and Physics from Bosphorus University in Turkey, an M.S. in Engineering from Southern Illinois University, and a Ph.D. in Electrical Engineering from the University of Pennsylvania.

“The semiconductor industry is the foundation of the U.S. tech sector and an important element of a healthy economy,” said Sayiner. “I look forward to helping advance policies in the year ahead that strengthen our industry by promoting innovation, growth, and open markets.”

Tunç Doluca joined Maxim in 1984 as a Member of Technical Staff and was named the company’s Vice President of R&D in 1993. In 2007, Tunç became the second CEO in the company’s history. During his tenure as CEO, Maxim reorganized product development around end markets and completed nine strategic acquisitions. He oversaw the transition of Maxim’s manufacturing to a more flexible hybrid production model and improved overall manufacturing execution. Tunç was born in Ankara, Turkey, and he holds a BSEE degree from Iowa State University and an MSEE degree from the University of California, Santa Barbara.

“For more than 30 years, Tunç Doluca has been an outstanding leader for Maxim and a devoted champion for our industry,” said Neuffer. “We look forward to putting his skills and experience to use as 2016 SIA Vice Chair.”

“I’m excited to take on a leadership role for SIA in support of the U.S. semiconductor industry,” said Doluca. “We face tremendous opportunities and unprecedented challenges in the coming year, and I look forward to getting to work to help move our industry forward.”

“Advanced packaging will reach 44% of packaging services and a revenue of US$ 30 billion by 2020,” Yole Développement (Yole) announced. Overall, the main advanced packaging market is the mobile sector with end products such as smartphones and tablets. Other high volume applications include servers, PC, game stations, external HDD/USB and more.

According to Yole’s latest advanced packaging report entitled “Status of the Advanced Packaging Industry” (2015 Edition), emerging applications are coming from the IoT world, with wearables and home appliances (connected home) solutions already penetrating the market. Other early stage IoT investments have been also made in smart cities, connected cars, industrial devices, medical applications…

In parallel, the Chinese companies play an important role in the advanced packaging market growth: “At Yole, we see an increased activity of Chinese capital in the advanced packaging industry,” explains Andrej Ivankovic, Technology & Market Analyst, Advanced Packaging & Semiconductor Manufacturing at Yole. “The objective of the semiconductor transformation in China is to decrease external dependency and set up a complete internal supply chain that can serve domestic and international customers.”

In this context, what would be the evolution of the advanced packaging industry? What will be the status of the supply chain by 2020? Which packaging technologies will be the most critical tomorrow and after? With the emergence of IoT applications, the development of local Chinese industry and numerous M&A coming from the overall semiconductor industry and the direct impact on the advanced packaging supply chain. Yole’s advanced packaging analysts offer you insight into the new advanced packaging world.

“Status of the Advanced Packaging Industry” report (2015 edition) released by Yole, the “More than Moore” market research and strategy consulting company, provides an high added-value market overview of the industrial landscape; under this new report, Yole’s advanced packaging team proposes a comprehensive analysis of the technology trends and also assesses the future development of the advanced packaging market.

packaging industry graph

This analysis confirms the market positioning of Yole and highlights the knowledge and deep understanding of the company within this industrial field.

According to Yole’s estimates, advanced packaging services revenue will increase by US$9.8 billion from 2014 to 2020 at a CAGR of 7%, in majority due to high volume adoption of Fan-Out WLP, 2.5D/3D and evolution and growth of Fan-In WLP and flip-chip. Advanced packages currently account for 38% of all packaging services or US$ 20.2 billion and are expected to grow share to 44% and US$ 30 billion by 2020.

The mobile sector remains the main advanced packaging market with smartphones and tablets as end products. Other high volume applications include servers, PC, game stations, HDD/USB, WiFi hardware, base stations, TVs and set top boxes. The scent of IoT is spreading with first products already on the market in the form of wearables and smart home appliances. Further early stage investments are made in sectors such as smart cities, connected cars, various industrial devices and medical applications.

The flip-chip platform represents a large mature market and leads in packaging services revenue and wafer count. Fan-In WLP leads in unit count due to small size compared to demanded volume. Adoption of wafer level packages continues. Teardowns performed by Yole and its sister company, System Plus Consulting on 3 high end smartphones (more info on i-micronews.com, reports section or click here directly for iPhone 6+, Samsung Galaxy S6 as well as the Huawei Ascend Mate 7 analysis, that will be available soon) indicated a high penetration rate of WLP, 30% on average. Fan-Out WLP is expected to make a major breakthrough within the next year, likely led by TSMC inFO PoP and followed by other Fan-Out multi die solutions. Long term, a bright future lies ahead for wafer level packages with respect to IoT requirements as they are well position to answer related cost, form and functional integration demands. When it comes to advanced feature sizes, a competitive sub 10 µm / 10 µm arena is established where organic wafer level packages aggressively compete with advanced organic flip-chip substrates and 2.5D / 3D Si/glass interposers.

As WLP pin counts grow, thicknesses and overall cost decrease, the evolution of Fan-In WLP and in particular a breakthrough of Fan-Out WLP are expected to result in a takeover of a part of the flip-chip market. With the breakthrough of Fan-Out WLP, the packaging landscape might drastically change, with an IDM and foundry leading all packaging services by wafer count.

The full advanced packaging analysis is today available; in the report Yole’s analysts present revenue, wafer and unit forecasts per advanced packaging platform and production breakdown by device type such as analog/mixed signal, wireless/RF, logic and memory, CMOS image sensors, MEMS, LED and LCD display drivers.

Engineers at Oregon State University have made a fundamental breakthrough in understanding the physics of photonic “sintering,” which could lead to many new advances in solar cells, flexible electronics, various types of sensors and other high-tech products printed onto something as simple as a sheet of paper or plastic.

Sintering is the fusing of nanoparticles to form a solid, functional thin-film that can be used for many purposes, and the process could have considerable value for new technologies.

Photonic sintering has the possible advantage of higher speed and lower cost, compared to other technologies for nanoparticle sintering.

In the new research, OSU experts discovered that previous approaches to understand and control photonic sintering had been based on a flawed view of the basic physics involved, which had led to a gross overestimation of product quality and process efficiency.

Based on the new perspective of this process, which has been outlined in Nature Scientific Reports, researchers now believe they can create high quality products at much lower temperatures, at least twice as fast and with 10 times more energy efficiency.

Removing constraints on production temperatures, speed and cost, the researchers say, should allow the creation of many new high-tech products printed onto substrates as cheap as paper or plastic wrap.

“Photonic sintering is one way to deposit nanoparticles in a controlled way and then join them together, and it’s been of significant interest,” said Rajiv Malhotra, an assistant professor of mechanical engineering in the OSU College of Engineering. “Until now, however, we didn’t really understand the underlying physics of what was going on. It was thought, for instance, that temperature change and the degree of fusion weren’t related – but in fact that matters a lot.”

With the concepts outlined in the new study, the door is open to precise control of temperature with smaller nanoparticle sizes. This allows increased speed of the process and high quality production at temperatures at least two times lower than before. An inherent “self-damping” effect was identified that has a major impact on obtaining the desired quality of the finished film.

“Lower temperature is a real key,” Malhotra said. “To lower costs, we want to print these nanotech products on things like paper and plastic, which would burn or melt at higher temperatures. We now know that is possible, and how to do it. We should be able to create production processes that are both fast and cheap, without a loss of quality.”

Products that could evolve from the research, Malhotra said, include solar cells, gas sensors, radiofrequency identification tags, and a wide range of flexible electronics. Wearable biomedical sensors could emerge, along with new sensing devices for environmental applications.

In this technology, light from a xenon lamp can be broadcast over comparatively large areas to fuse nanoparticles into functional thin films, much faster than with conventional thermal methods. It should be possible to scale up the process to large manufacturing levels for industrial use.

This advance was made possible by a four-year, $1.5 million National Science Foundation Scalable Nanomanufacturing Grant, which focuses on transcending the scientific barriers to industry-level production of nanomaterials. Collaborators at OSU include Chih-hung Chang, Alan Wang and Greg Herman.

OSU researchers will work with two manufacturers in private industry to create a proof-of-concept facility in the laboratory, as the next step in bringing this technology toward commercial production.