Greater process control essential to enable future scaling

Richard Gottscho, Ph.D., Executive Vice President, Global Products, Lam Research Corp.

2016 looks to be an exciting year as several key inflection technologies – including multiple patterning, FinFET, and 3D NAND – continue to move into high-volume manufacturing worldwide. While these inflections enable the continuation of Moore’s Law, the increasing number of steps and overall complexity add significantly to the challenge of reducing process-induced variation.

At the 10 nm node and below, edge placement error (EPE) is becoming a significant limitation to continued scaling. Historically, the degree of EPE was largely determined by misalignment in lithography overlay. Today, EPE can be dominated by other process components, and variations from both lithography and non-lithography steps are pushing EPE beyond the allowable design specifications. This is exacerbated by the adoption of multiple patterning techniques such as litho-etch-litho-etch. One way to reduce overlay errors is to decrease the mask count, for example, by advancing to next-generation EUV lithography. With or without EUV, improved on-product overlay can be achieved by reducing line edge roughness through etching- and deposition-induced smoothing.

Another contributor to EPE in multi-patterning comes from pitch walking. This is particularly challenging in self-aligned patterning schemes, where several deposition and etch process steps are used to define the line/space patterns. In this case, the critical dimension (CD) is defined not only by lithography, but also by core etch, spacer deposition, spacer etch, and wet clean process steps used to double or quadruple the density. To improve CD uniformity and minimize pitch walking, advanced process and process control solutions such as atomic layer deposition (ALD) and die-scale fine-tuning to correct for incoming pattern variation are being adopted in volume manufacturing.

Increased complexity is evident not only in multiple patterning, but also in device architectures that are migrating from 2D to 3D. In a FinFET, for example, the channel area is defined not only by fin width and length, but also by fin height. Precise control of CDs in all directions is vital to FinFET device performance. There will also be an increasing need for precision atomic layer etching (ALE) to minimize damage, reduce roughness, and increase selectivity.

In the case of 3D NAND, vertical stacking of memory cells poses its own process control challenges. Achieving uniform formation of the memory cells from top to bottom of the multi-layered film stack requires stringent control during film stack deposition, hardmask deposition, hardmask open etches, and the memory hole etch itself. Currently, 3D NAND devices with up to 48 layers are in volume manufacturing. With applications such as SSDs now adopting 3D NAND technology, enabling next-generation structures with up to ~100 layers is putting more pressure on equipment suppliers and device manufacturers to minimize variations and defects through advanced process control.

As the industry embraces the benefits offered by inflection technologies – lower power, higher density, and more functionality – chipmakers are facing mounting challenges imposed by increased complexity and cost. Next-generation non-volatile memories, alternative interconnect strategies, new channel materials, and new device architectures such as nanowires will further increase complexity and demand even greater control of unit processes as well as the interaction between those processes. Finding solutions to improve process control, reduce variation, and reduce cost is essential for the industry to continue scaling.