BY PHIL GARROU, Contributing Editor
The 12th annual International Wafer Level Packaging Conference (IWLPC) was held in San Jose in October. The technical focus consisted of 1) fan-out WLCSP, 2) 2.5 and 3D IC packaging, and 3) MEMS. This conference is becoming a major player in the exhibition end of the packaging business this year having 65 booths set up in San Jose. Here’s a review of the news in these areas.
DECA
Cost, yield and reliability issues have effectively limited the widespread adoption of FOWLP. Placing singulated chips on the carrier to form the molded panel requires high placement accuracy. Any misplacements can lead to pattern overlay diffi- culties in the buildup process on the reconstituted panel. The requirement for high placement accuracy restricts throughput at the pick-and-place operation, leading to high process costs. During the molding operation and mold cure, die drift or movement can occur. This die drift can further complicate pattern overlay matching in the buildup process on the panel and can result in yield loss when the drift is excessive.
In the DECA process die with preformed Cu studs are placed face-up on a carrier, using a high speed pick and place tool. The front and sides of the die are then covered with mold compound using compression molding. The molded panel is debonded from the carrier, and the front surface is ground to reveal the Cu studs. A high speed optical scanner is used to determine the actual position of every die on the panel. This information is fed into a proprietary Adaptive Patterning design tool, which adjusts the fan-out unit design for each package on the panel to match actual die locations. Finally, the design files for each panel are imported to a lithography machine which uses the design data to dynamically apply a custom, Adaptive Pattern to each panel during the fan-out build-up process. Adaptive Patterning works by dynamically adjusting one or more build-up layers to accurately connect to the Cu studs protruding through the mold compound for each individual die in the molded panel.
SPTS – Plasma dicing
Plasma dicing is attracting significant interest within the semiconductor industry as a viable alternative to conven- tional singulation methods using saw blades or lasers. Plasma dicing promises benefits such as increasing wafer throughput, die per wafer and die yields (due to low damage processing). For small die, in particular, where the time required for a high number of mechanical slices in “series” can be substantial, a “parallel” process such as plasma dicing which etches all dicing lanes simultaneously, can significantly increase wafer throughput.
Maximum benefits are gained when plasma dicing is “designed in” from the beginning. With dicing lanes defined by photolithography, these lanes can be narrower than the width of a dicing blade, saving valuable silicon real-estate which can be used to increase the number of die per wafer. Also, the designer can make sure that dicing lanes are free from metals and other layers which can hinder plasma etching. This is often quoted as the prime challenge which prevents implementing plasma dicing in an existing production scheme.
IMEC/KLA-Tencor
IMEC/KLA-Tencor shared their results on investigations to determine the best way to insure μbump presence and co-planarity. μbump dimensions are being scaled down to 20 μm pitch (10 μm in width and 8 μm high). For die-to-die and die-to-wafer stacking, the need for highly accurate and repeatable measurement of μbumps at both die-level and wafer- level is a must for this technology to become a viable industrial option. Bump co-planarity is defined as the difference between the heights of the tallest and the shortest μbump within a die.
A failure to properly characterize the co-planarity of each die and detect defects of interest such as damaged, missing or mis-located bumps can lead to the wrongful classification of the die as suitable for assembly. This may have a number of yield-affecting consequences during stacking, such as open and short circuits, die cracking and thermal sinks. As the number of die in a typical die stack increases, a single falsely classified die will affect the entire product.
One of the challenges in constituting a meaningful subset for measurement is to define a population of μbumps which is large enough to be statistically significant and to select μbumps from areas in the die which will represent height range and copla- narity of the full die.