Monthly Archives: April 2016

By Ed Korczynski, Senior Technical Editor

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

“Mix and Match” has long been a mantra for lithographers in the deep-sub-wavelength era of IC device manufacturing. In general, forming patterns with resolution at minimum pitch as small as 1/4 the wavelength of light can be done using off-axis illumination (OAI) through reticle enhancement techniques (RET) on masks, using optical proximity correction (OPC) perhaps derived from inverse lithography technology (ILT). Lithographers can form 40-45nm wide lines and spaces at the same half-pitch using 193nm light (from ArF lasers) in a single exposure.

Figure 1 shows that application-specific tri-layer photoresists are used to reach the minimum resolution of 193nm-immersion (193i) steppers in a single exposure. Tighter half-pitch features can be created using all manner of multi-patterning processes, including Litho-Etch-Litho-Etch (LELE or LE2) using two masks for a single layer or Self-Aligned Double Patterning (SADP) using sidewall spacers to accomplish pitch-splitting. SADP has been used in high volume manufacturing (HVM) of logic and memory ICs for many years now, and Self-Aligned Quadruple Patterning (SAQP) has been used in at least one leading memory fab.

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

FIGURE 1. Basic tri-layer resist (TLR) technology uses thin Photoresist over silicon-containing Hard-Mask over Spin-On Carbon (SOC), for patterning critical layers of advanced ICs. (Source: Brewer Science)

Next-Generation Lithography (NGL) generally refers to any post-optical technology with at least some unique niche patterning capability of interest to IC fabs: Extreme Ultra-Violet (EUV), Directed Self-Assembly (DSA), and Nano-Imprint Lithography (NIL). Though proponents of each NGL have dutifully shown capabilities for targeted mask layers for logic or memory, the capabilities of ArF dry and immersion (ArFi) scanners to process >250 wafers/ hour with high uptime dominates the economics of HVM lithography.

The world’s leading lithographers gather each year in San Jose, California at SPIE’s Advanced Lithography conference to discuss how to extend optical lithography. So of all the NGL technologies, which will win out in the end?

It is looking most likely that the answer is “all of the above.” EUV and NIL could be used for single layers. For other unique patterning application, ArF/ArFi steppers will be used to create a basic grid/template which will be cut/trimmed using one of the available NGL. Each mask layer in an advanced fab will need application-specific patterning integration, and one of the rare commonalities between all integrated litho modules is the overwhelming need to improve pattern overlay performance.

Naga Chandrasekaran, Micron Corp. vice president of Process R&D, provided a fantastic overview of the patterning requirements for advanced memory chips in a presentation during Nikon’s LithoVision technical symposium held February 21st in San Jose, California prior to the start of SPIE-AL. While resolution improvements are always desired, in the mix-and-match era the greatest challenges involve pattern overlay issues.

“In high volume manufacturing, every nanometer variation translates into yield loss, so what is the best overlay that we can deliver as a holistic solution not just considering stepper resolution?” asks Chandrasekaran.

“We should talk about cost per nanometer overlay improvement.”

Extreme Ultra-Violet (EUV)

As touted by ASML at SPIE-AL, the brightness and stability and availability of tin-plasma EUV sources continues to improve to 200W in the lab “for one hour, with full dose control,” according to Michael Lercel, ASML’s director of strategic marketing. ASML’s new TWINSCAN NXE:3350B EUVL scanners are now being shipped with 125W power sources, and Intel and Samsung Electronics reported run their EUV power sources at 80W over extended periods.

During Nikon’s LithoVision event, Mark Phillips, Intel Fellow and Director of Lithography Technology Development for Logic, summarized recent progress of EUVL technology: ~500 wafers-per-day is now standard, and ~1000 wafer-per-day can sometimes happen. However, since grids can be made with ArFi for 1/3 the cost of EUVL even assuming best productivity for the latter, ArFi multi-patterning will continue to be used for most layers.

“Resolution is not the only challenge,” reminded Phillips. “Total edge-placement-error in patterning is the biggest challenge to device scaling, and this limit comes before the device physics limit.”

Directed Self-Assembly (DSA)

DSA seems most suited for patterning the periodic 2D arrays used in memory chips such as DRAMs. “Virtual fabrication using directed self-assembly for process optimization in a 14nm DRAM node” was the title of a presentation at SPIE-AL by researchers from Coventor in which DSA compared favorably to SAQP.

Imec presented electrical results of DSA-formed vias, providing insight on DSA processing variations altering device results. In an exclusive interview with Solid State Technology and SemiMD, imec’s Advanced Patterning Department Director Greg McIntyre reminds us that DSA could save one mask in the patterning of vias which can all be combined into doublets/triplets, since two masks would otherwise be needed to use 193i to do LELE for such a via array. “There have been a lot of patterning tricks developed over the last few years to be able to reduce variability another few nanometers. So all sorts of self-alignments.”

While DSA can be used for shrinking vias that are not doubled/tripled, there are commercially proven spin-on shrink materials that cost much less to use as shown by Kaveri Jain and Scott Light from Micron in their SPIE-AL presentation, “Fundamental characterization of shrink techniques on negative-tone development based dense contact holes.” Chemical shrink processes primarily require control over times, temperatures, and ambients inside a litho track tool to be able repeatably shrink contact hole diameters by 15-25 nm.

Nano-Imprint Litho (NIL)

For advanced IC fab applications, the many different options for NIL technology have been narrowed to just one for IC HVM. The step-and-pattern technology that had been developed and trademarked as “Jet and Flash Imprint Lithography” or “J-FIL” by, has been commercialized for HVM by Canon NanoTechnologies, formerly known as Molecular Imprints (http://cnt.canon.com/). Canon shows improvements in the NIL mask-replication process, since each production mask will need to be replicated from a written master. To use NIL in HVM, mask image placement errors from replication will have to be reduced to ~1nm, while the currently available replication tool is reportedly capable of 2-3nm (3 sigma).

Figure 2 shows normalized costs modeled to produce 15nm half-pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. Key to throughput is fast filling of the 26mmx33mm mold nano-cavities by the liquid resist, and proper jetting of resist drops over a thin adhesion layer enables filling times less than 1 second.

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

FIGURE 2. Relative estimated costs to pattern 15nm half- pitch lines/spaces for different lithography technologies, assuming 125 wph for a single EUV stepper and 60 wph for a cluster of 4 NIL tools. (Source: Canon)

Researchers from Toshiba and SK Hynix described evaluation results of a long-run defect test of NIL using the Canon FPA-1100 NZ2 pilot production tool, capable of 10 wafers per hour and 8nm overlay, in a presentation at SPIE-AL titled, “NIL defect performance toward high- volume mass production.” The team categorized defects that must be minimized into fundamentally different categories—template, non-filling, separation-related, and pattern collapse—and determined parallel paths to defect reduction to allow for using NIL in HVM of memory chips with <20nm half-pitch features.

By Debra Vogler, SEMI

The demand for smartphones and other portable devices that need efficient power management is driving the analog IC market. Additionally, growth is fueled by the Internet of Things (IoT) and the MEMS/sensors devices that enable it. To explore the supply chain opportunities within the analog sector, including MEMS/sensors, SEMI introduced the Analog and New Frontiers Program at SEMICON West 2016. This program — part of the Extended Supply Chain Forum — will feature four, hour-long sessions, each focusing on a different supply chain challenge or area of interest within the analog sector. One of the featured speakers will be Dr. Peter Hartwell, senior director of Advanced Technology at InvenSense. Dr. Hartwell’s pre-show interview provides a provocative look at supply chain challenges facing MEMS/sensors manufacturers.

Perhaps the most significant challenge facing manufacturers of MEMS/sensors is commoditization of sensors and where the profits end up. “The windfall is going to the people enabling the applications at the top,” Hartwell told SEMI. “Especially with mobile devices and IoT.” He pointed out that if there isn’t a way for value capture at the lowest levels – i.e., the companies that enable the systems and devices that create the IoT experience – he predicts a plateau of innovation. “We won’t have the resources to push technology forward, so as a sensor company, we are trying to find ways to move further up the value chain to extract some of that value.”

Moving up the value chain, however, requires sensor companies to become more aware of system considerations. Design convergence is one way to accomplish this. “We think of design convergence as SiPs (System in Package) or SoCs (System on a Chip),” said Hartwell. “We start to put together our sensors with other capabilities, whether that means having processing power in our package or looking at different kinds of sensors that come together.”

He speculates about a time when there will be a single-chip IoT device, i.e., a one-chip device comprising sensors, storage, radio, power management, and perhaps even energy harvesting. “Maybe that’s where the convergence goes.” Still, in the end, the challenge becomes how the industry gets the money back to the bottom of the supply chain. “We’re inching up towards where that money is by building those systems and understanding what it takes to make them.”

The fabless model for MEMS/sensors

Aside from the commoditization conundrum, Hartwell sees another supply chain opportunity arising if the industry embraces a truly fabless business model. Such a model would be based on companies that only design the devices with the process kits arising from different companies. The fundamental question with that scenario, Hartwell notes, is how the various MEMS/sensors houses differentiate themselves.

Hartwell noted that InvenSense embraces the fabless model — the company has a Shuttle program with its foundry partners, TSMC and GLOBALFOUNDRIES. The InvenSense Shuttle gives MEMS developers the opportunity to fabricate their designs on the patented InvenSense Fabrication MEMS-CMOS integrated platform. Though competitors are not able to take part in the Shuttle program, it is available to universities and start-up partner companies. That said, Hartwell noted that the company keeps its ‘cards pretty close to the vest.’ So the challenge is how to open up that model while retaining differentiation when fabs and foundries tend to want to wring out cost from process development by using as much standardization as possible.

“The million dollar question,” said Hartwell, “is could we ever get to the point where the foundry tells the sensor companies what to do — the EDA companies would love to see this happen because it would lead to standardization of design tools and simulators.”

Opportunities for test and the digital interface

Test and packaging are two more opportunity areas for the supply chain. Hartwell pointed out that most MEMS/sensors companies do their own testing using their own test infrastructure. “It’s one differentiator that we haven’t been willing to give up,” said Hartwell. “So this is an opportunity for someone to come in and turn over the apple cart.”

With the proliferation of sensors that need to interface with a multi-chip system comes the challenge of having to connect using more and more pins. And though the industry has solutions for a digital interface to the sensor world, additional work needs to focus on making that interface robust. Hartwell explained that multiple interrupts and digital lines are needed and it gets complicated when you have five, six, or seven sensors in a system. “There are just not enough pins,” said Hartwell. “So we’re seeing a change in the wiring and the interface will have to be something new to solve the integration problem, which has become nontrivial.” He further observed that IoT is driven by four attributes: size, cost, power, and performance. “To get to the promise of IoT, it will take breakthroughs to get to a trillion sensors. You will have to reduce size, cost, power and performance, and some of those by one or two orders of magnitude.”

Wringing out costs with packaging (or, “no” package)

Hartwell minces no words when it comes to tackling size and cost in MEMS: packaging is MEMS. “This is the biggest opportunity to take out size and cost,” Hartwell told SEMI. “The influence of packaging on the transducer can’t be ignored. Packaging hurts the size, it hurts performance, and it’s something for which I don’t want to pay. It’s a huge opportunity for a shift.”

For Hartwell, the crux of the challenge is how to take a single piece of silicon that has a 6-axis sensor system, and then test it, trim it, ship it, and put it into whatever system it’s going into without changing its trim. While chip-scale packaging could be the opportunity the MEMS industry needs, he wants to keep the options open for other ways to break the paradigm.

What’s clear is that ample business opportunities exist for the supply chain within the MEMS/sensors sector to get rid of cost and size, address the test challenge, get rid of the package, and finally, new ways to handle and assemble parts.

To learn more, attend the Analog and New Frontiers Forum (part of the Extended Supply Chain Forum) at SEMICON West. The forum will be held on Wednesday, July 13, in four, hour-long sessions on the Keynote Stage, North Hall, Moscone Center. Check the SEMICON West 2016 website for more details and a list of confirmed speakers for each of the sessions.

Research and Markets’ recent report, “Global Semiconductor Packaging Materials Market 2016-2020”, expects the global semiconductor packaging materials market to grow at a CAGR of 4.79% during the period of 2016-2020.

The report covers the present market and the growth prospects of the global semiconductor packaging materials market for the period 2016-2020. To calculate the market size and geographical segmentation, the report considers the revenue generated from the sales of different types of packaging based on the type of material, which can be broadly classified as either leadframe based or laminate substrate based.

Market Challenges, Drivers and Trends

The semiconductor industry is facing many changes in technology, including the introduction of 3D ICs, including 3D NAND, FinFETs, and stacked dies. The increase in demand for multifunctional and high-performance ICs in electronic devices is driving the need for regular technological upgrades. 3D ICs are an ideal solution to meet the growing demand for smaller and higher-performance ICs in the consumer electronics segment. 3D NAND is another technology that provides a large memory storage area in minimal space; this technology will likely capture 54.82% of the total NAND market by the end of 2020.

According to the report, the demand for polymer adhesive wafer bonding equipment is rising due to the increasing adoption of advanced packaging applications like TSV, 2.5D and 3D ICs, stacked die packaging, and MEMS packaging. Polymer adhesive wafer bonding equipment provides reliable thinning and backside processing of the stacked dies. In addition, it lowers the cost of TSV (through-silicon via) integration. The rising demand for polymer adhesive wafer bonding equipment will, therefore, have a moderately high impact on the market for semiconductor devices as this equipment supports 3D packaging, which is the future of the semiconductor packaging and assembly industry.

Further, the report states that the currency fluctuation in countries such as China and Japan negatively affects the growth of semiconductor packaging materials market

Cypress CEO to step down


April 28, 2016

Cypress Semiconductor Corp. (NASDAQ:  CY) today announced that its CEO, T.J. Rodgers, will step down this week and that a search—both internal and external—would be launched to replace him.  In the interim, daily operational activities will be taken over by an Office of the CEO comprised of four current Cypress EVPs: Hassane El-Khoury (EVP, Programmable Systems Division), Dana Nazarian (EVP, Memory Products Division), Joe Rauschmayer (EVP, Manufacturing) and Thad Trent (CFO).  Rodgers will remain on the Cypress Board and become a project leader working on key technical projects.

Rodgers said, “This March, Valeta and I celebrated my 68th birthday in Mexico.  Upon reflection, while I am still passionately interested in Element 14, silicon, I have always planned not to be spending most of my time in the last decade of my career immersed in the details of the operations, including those of the 7,000-person company that Cypress has become.  And, to be completely candid, the board and even the executive staff have urged me to bring new blood into operations.  Thus, the first-quarter 2016 report, my 120th as Cypress’s CEO, will be my last.  More importantly to me, I will now be able to work full time on the technology that has fascinated me since my mother first kindled my interest in electronics when I was a fifth-grader.”

Rodgers continued, “I have always reserved about 30 percent of my time to work on technology and one key project.  This activity adds value to the company and remains of high interest to me at this stage of my career.  In the future, Cypress management will be able to assign a key project to me and count on it getting done right.”

Active matrix organic light-emitting diode (AMOLED) displays are rising fast, thanks to lowering costs, wider use in end-market consumer electronics devices and the ramp-up of new manufacturing capacities.  While liquid crystal display (LCD) technology is still the dominant technology in the display industry, AMOLED display shipments will grow 40 percent, year over year, to reach 395 million units in 2016. AMOLED display revenue is expected to increase by 25 percent, to reach $15 billion in 2016, according to IHS Inc. (NYSE: IHS), a global source of critical information and insight.

“AMOLED is becoming the shiniest spot in the flat-panel display industry,” said David Hsieh, senior director, displays at IHS Technology. “AMOLED has a simpler structure than LCD, as well as a thinner and lighter form factor, better color saturation, greater contrast ratio, faster response time and easier integration with touch functions. In addition, AMOLED is formed on a polymer base substrate, allowing it to be flexible, bendable and even foldable. The organic electro-luminescence materials can be formed using a soluble printing process, which means AMOLED has the potential to be produced at a very low cost.”

Many of the obstacles to AMOLED development, such as production inefficiencies, yield-rate management issues, higher investment costs and a short lifetime for light emitting materials, were also resolved in 2015, improving the production. OLED has started to find its niche in many applications, especially in smartphones, smartwatches, automotive displays, home appliances, near-eye virtual reality (VR) devices and televisions. “Improvements in production and lowering costs are attracting more device makers to install AMOLED displays in their products,” Hsieh said.

For example, Samsung Electronics has been using AMOLED as an important differentiator in its proprietary Galaxy smartphones. Since the second half of 2015, more smartphone brands — especially manufacturers in China — have installed AMOLED displays in their devices, such as Google, Microsoft, Meizhu, Blackberry, Huawei, HTC, ZTE, Oppo and Coolpad. The 5-inch high-definition (HD), 5.5-inch full high definition (FHD), 5.5-inch and 6-inch wide quad high definition (WQHD) will be the major AMOLED smartphone display driving forces in 2016.

AMOLED penetration in smartphone displays is expected to rise from 17 percent in 2015 to 21 percent this year. Apple is reported to be considering AMOLED as a display source for its new iPhone in late 2017, replacing the current low-temperature polysilicon (LTPS) thin-film transistor (TFT) LCD display. “If Apple actually starts using AMOLED displays, the transition will be viewed as a milestone in flexible form factor development,” Hsieh said.

AMOLED_Chart_LG_IHS

According to the IHS OLED Display Market Tracker, OLED TV shipments will further expand in 2016, thanks to process improvements and production efficiency enhancements, as well as improvements in organic light emitting materials layers. In fact, LG Display is already expanding its AMOLED TV panels to 65 inches with ultra-high definition (UHD), which will bring AMOLED into the high-end TV segment. IHS expects OLED TV display shipments will grow 125 percent, year over year, to reach 900,000 units in 2016.

Tablet and notebook PCs is another important venue for AMOLED, for its slim and light form factor, and high resolution. We expect to see 8-inch and 9.7-inch quad extended graphics array (QXGA) displays and 12-inch AMOLED panels begin to emerge in the mobile PC arena this year. Many PC brands are planning to use AMOLED in notebook PCs and two-in-one convertible mobile PC models beginning in 2016. AMOLED mobile PC panels are expected to grow 63 percent year over year, to reach to 8.6 million units in 2016.

AMOLED is also leading other display technologies when it comes to response time and power consumption, which is extremely useful in near-eye display devices, including VR and augmented reality (AR) devices. AMOLED display and OLED on silicon projection displays, which are both used in near-eye displays are forecast to grow 119 percent, year over year, to reach 3.6 million units in 2016.

“The central information display in cars will also feature AMOLED within the next couple of years,” Hsieh said, “AMOLED displays provide features that are useful in automotive display applications, because of their high contrast ratio, flexible and curved form factors as well as better color gamut. Aside from these applications, AMOLED also presents great opportunities for industrial applications, home appliances, digital signage and broadcasting.”

AMOLED, as a rapidly emerging display technology, will be a key theme in the coming SID Display Week 2016 Business Track, which is co-organized by IHS and the Society for Information Display. For more information, visit SID Display Week.

A group of scientists from ITMO University in Saint Petersburg has put forward a new approach to effective manipulation of light at the nanoscale based on hybrid metal-dielectric nanoantennas. The new technology promises to bring about a new platform for ultradense optical data recording and pave the way to high throughput fabrication of a wide range of optical nanodevices capable of localizing, enhancing and manipulating light at the nanoscale. The results of the study were published in Advanced Materials.

Selective laser exposure to create hybrid nanostructures. Credit: ITMO University

Selective laser exposure to create hybrid nanostructures. Credit: ITMO University

Nanoantenna is a device that converts freely propagating light into localized light – compressed into several tens of nanometers. The localization enables scientists to effectively control light at the nanoscale. This is one of the reasons why nanoantennas may become the fundamental building blocks of future optical computers that rely on photons instead of electrons to process and transmit information. This inevitable replacement of the information carrier is related to the fact that photons surpass electrons by several orders of magnitude in terms of information capacity, require less energy, rule out circuit heating and ensure high velocity data exchange.

Until recently, the production of planar arrays of hybrid nanoantennas for light manipulation was considered an extremely painstaking process. A solution to this problem was found by researchers from ITMO University in collaboration with colleagues from Saint Petersburg Academic University and Joint Institute for High Temperatures in Moscow. The research group has for the first time developed a technique for creating such arrays of hybrid nanoantennas and for high-accuracy adjustment of individual nanoantennas within the array. The achievement was made possible by subsequently combining two production stages: lithography and precise exposure of thenanoantenna to a femtosecond laser – ultrashort impulse laser.

The practical application of hybrid nanoantennas lies, in particular, within the field of ultradense data recording. Modern optical drives can record information with density around 10 Gbit/inch2, which equals to the size of a single pixel of a few hundred nanometers. Although such dimensions are comparable to the size of the nanoantennas, the scientists propose to additionally control their color in the visible spectrum. This procedure leads to the addition of yet another ‘dimension’ for data recording, which immediately increases the entire data storage capacity of the system.

Apart from ultradense data recording, the selective modification of hybrid nanoantennas can help create new designs of hybrid metasurfaces, waveguides and compact sensors for environmental monitoring. In the nearest future, the research group plans to focus on the development of such specific applications of their hybrid nanoantennas.

The nanoantennas are made of two components: a truncated silicon cone with a thin golden disk located on top. The researchers demonstrated that, thanks to nanoscale laser reshaping, it is possible to precisely modify the shape of the golden particle without affecting the silicon cone. The change in the shape of the golden particle results in changing optical properties of the nanoantenna as a whole due to different degrees of resonance overlap between the silicon and golden nanoparticles.

“Our method opens a possibility to gradually switch the optical properties of nanoantennas by means of selective laser melting of the golden particles. Depending on the intensity of the laser beam the golden particle will either remain disc-shaped, convert into a cup or become a globe. Such precise manipulation allows us to obtain a functional hybrid nanostructure with desired properties in the flicker of a second,” comments Sergey Makarov, one of the authors of the paper and researcher at the Department of Nanophotonics and Metamaterials of ITMO University.

Contrary to conventional heat-induced fabrication of nanoantennas, the new method raises the possibility of adjusting individual nanoantennas within the array and exerting precise control over overall optical properties of the hybrid nanostructures.

“Our concept of asymmetric hybrid nanoantennas unifies two approaches that were previously thought to be mutually exclusive: plasmonics and all-dielectric nanophotonics. Our hybrid nanostructures inherited the advantages of both approaches – localization and enhancement of light at the nanoscale, low optical losses and the ability to control the scattering power pattern. In turn, the use of laser reshaping helps us precisely and quickly change the optical properties of such structures and perhaps even record information with extremely high density,” concludes Dmitry Zuev, lead author of the study and researcher at the Department of Nanophotonics and Metamaterials of ITMO University.

Researchers from the University of Illinois at Urbana-Champaign have developed a one-step, facile method to pattern graphene by using stencil mask and oxygen plasma reactive-ion etching, and subsequent polymer-free direct transfer to flexible substrates.

Graphene, a two-dimensional carbon allotrope, has received immense scientific and technological interest. Combining exceptional mechanical properties, superior carrier mobility, high thermal conductivity, hydrophobicity, and potentially low manufacturing cost, graphene provides a superior base material for next generation bioelectrical, electromechanical, optoelectronic, and thermal management applications.

“Significant progress has been made in the direct synthesis of large-area, uniform, high quality graphene films using chemical vapor deposition (CVD) with various precursors and catalyst substrates,” explained SungWoo Nam, an assistant professor of mechanical science and engineering at Illinois. “However, to date, the infrastructure requirements on post-synthesis processing–patterning and transfer–for creating interconnects, transistor channels, or device terminals have slowed the implementation of graphene in a wider range of applications.”

“In conjunction with the recent evolution of additive and subtractive manufacturing techniques such as 3D printing and computer numerical control milling, we developed a simple and scalable graphene patterning technique using a stencil mask fabricated via a laser cutter,” stated Keong Yong, a graduate student and first author of the paper, “Rapid Stencil Mask Fabrication Enabled One-Step Polymer-Free Graphene Patterning and Direct Transfer for Flexible Graphene Devices appearing in Scientific Reports.

“Our approach to patterning graphene is based on a shadow mask technique that has been employed for contact metal deposition,” Yong added. “Not only are these stencil masks easily and rapidly manufactured for iterative rapid prototyping, they are also reusable, enabling cost-effective pattern replication. And since our approach involves neither a polymeric transfer layer nor organic solvents, we are able to obtain contamination-free graphene patterns directly on various flexible substrates.”

Nam stated that this approach demonstrates a new possibility to overcome limitations imposed by existing post-synthesis processes to achieve graphene micro-patterning. Yong envisions this facile approach to graphene patterning sets forth transformative changes in “do It yourself” (DIY) graphene-based device development for broad applications including flexible circuits/devices and wearable electronics.

“This method allows rapid design iterations and pattern replications, and the polymer-free patterning technique promotes graphene of cleaner quality than other fabrication techniques,” Nam said. “We have shown that graphene can be patterned into varying geometrical shapes and sizes, and we have explored various substrates for the direct transfer of the patterned graphene.”

Cypress Semiconductor Corp. (Nasdaq:  CY) and Broadcom Limited (Nasdaq:  AVGO) today announced the signing of a definitive agreement under which Cypress will acquire Broadcom’s Wireless Internet of Things (IoT) business and related assets in an all-cash transaction valued at $550 million. Under the terms of the deal, Cypress will acquire Broadcom’s Wi-Fi, Bluetooth and Zigbee IoT product lines and intellectual property, along with its WICED brand and developer ecosystem. Broadcom’s IoT business unit, which employs approximately 430 people worldwide, generated $189 million in revenue during the last twelve months. The acquisition strengthens Cypress’s position in key embedded systems markets, such as automotive and industrial, and establishes it as a leader in the high-growth consumer IoT market, a segment that includes wearable electronics and home automation solutions.

The transaction, which has been approved by the board of directors of Cypress and Broadcom, is expected to close in the third calendar quarter of 2016, subject to customary conditions and regulatory approvals. Cypress expects the transaction to be accretive within a year of closing and to improve its gross margin, earnings and long-term revenue potential.

“Cypress is a significant player in the IoT today because of our ultra-low-power PSoC programmable system-on-chip technology, but we’ve only been able to pair it with generic radios so far. Now we have the highly regarded Broadcom IoT business—Wi-Fi, Bluetooth and Zigbee RF technologies—that will transform us into a force in IoT and provide us with new market opportunities as well,” Cypress President and CEO T.J. Rodgers said. “What we bring to the party is over 30,000 customers worldwide who need advanced, ultra-low-power wireless communication but only can absorb it in the form of an easy-to-use programmable embedded system solution.”

“We are thrilled to be joining forces with Cypress to address the fast growing IoT market,” Broadcom IoT General Manager Stephen DiFranco said. “With our IoT connectivity products, Cypress will be able to provide the connectivity; the MCU, system-on-chip, module and memory technologies; and the mature developer ecosystem that IoT designers require, creating an end-to-end portfolio of embedded solutions and a single IoT design platform.”

Under the terms of the deal, Broadcom will continue to focus on its wireless connectivity solutions for the access and mobility segments that are not IoT related, including serving set-top box, wireless access, smartphone, laptop and notebook customers. Cypress will capitalize on the rapidly growing Wi-Fi and Bluetooth connectivity (17% per year1) markets in consumer, industrial and automotive IoT segments.

“The robust, ready-to-scale WICED brand and developer network of module makers, value-added resellers (VARs), technology partners and ODMs who are already working with its technology will give us immediate revenue growth capability in new channels,” Rodgers said. “Cypress will continue to support and grow this network and to provide it with future generations of innovative, disruptive connected products. Cypress will also bring these new technologies to the automotive market, where we are already No. 3 worldwide in microcontrollers and memories, and where the connected car boom has just started.”

Greenhill & Co., LLC served as lead financial advisor, Bank of America Merrill Lynch served as financial advisor and is providing committed debt financing, subject to customary conditions, and Wilson Sonsini Goodrich & Rosati acted as legal counsel to Cypress for this transaction.

Cartamundi, imec and Holst Centre (set up by imec and TNO) are proud to announce to have just won the “Best Product” – Award at Printed Electronics Europe for their ultra-thin plastic RFID technology integrated into Cartamundi’s playing cards. The jury has hereby recognized the potential of this technology to become a gamechanger for the gaming industry, as well as for many other printed electronics applications in the Internet-of-Things domain.

With economic and form-factor advantages compared to traditional silicon-based technologies, Holst Centre’s and imec’s ultra-thin plastic RFID solution is essential to improve and broaden the applicability of electronics seamlessly integrated in paper. This enables Cartamundi to develop connected devices with additional value and content for consumers. At the conference, Cartamundi, imec and Holst Centre demonstrate an industry-first prototype of the ultra-thin flexible RFID chip integrated into a playing card. In each card, the RFID chip has a unique code that communicates wirelessly to an RFID reader, giving the cards in the game a unique digital identity.

Chris Van Doorslaer (CEO) is delighted with the award and sounds ambitious:

“Cartamundi’s ambition to embed wireless RFID tags in games and trading cards products is a ‘game changer’ indeed. The new technology will connect traditional game play with electronic devices like smartphones and tablets. As Cartamundi is committed to creating products that connect families and friends of every generation to enhance the valuable quality time they share during the day, this technology is a real enabler.”

“This is a thrilling development to demonstrate our TOLAE electronic technology integrated in the product of a partner company. TOLAE stands for Thin, Oxide and Large-Area Electronics”, stated Paul Heremans, department director of thin-film electronics at imec and technology director at the Holst Centre. “Our prototype thin-film RFID is thinner than paper—so thin that it can be invisibly embedded in paper products, such as playing cards. This key enabling technology will bring the cards and traditional games of our customer in direct connection with the Cloud. This achievement also opens up new applications in the IoT domain that we are exploring, to bring more data and possibilities to applications such as smart packaging, security paper, and maybe even banknotes.”

Steven Nietvelt Chief Technology & Innovation Officer: “This is Cartamundi at it’s very best: bringing new solutions to the ever creative game developing community. We are convinced the gaming community will be inspired by this technology. It can possibly enhance existing games but also allows for brand new concepts to arise.”

Imec and Cartamundi engineers will now explore up-scaling of the technology using a foundry production model.

This award would not have been possible without the support and advise of VLAIO. VLAIO played a substantial role by bringing all partners of the project together.

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Researchers at the Energy Department’s National Renewable Energy Laboratory (NREL) discovered single-walled carbon nanotube semiconductors could be favorable for photovoltaic systems because they can potentially convert sunlight to electricity or fuels without losing much energy.

The research builds on the Nobel Prize-winning work of Rudolph Marcus, who developed a fundamental tenet of physical chemistry that explains the rate at which an electron can move from one chemical to another. The Marcus formulation, however, has rarely been used to study photoinduced electron transfer for emerging organic semiconductors such as single-walled carbon nanotubes (SWCNT) that can be used in organic PV devices.

In organic PV devices, after a photon is absorbed, charges (electrons and holes) generally need to be separated across an interface so that they can live long enough to be collected as electrical current. The electron transfer event that produces these separated charges comes with a potential energy loss as the molecules involved have to structurally reorganize their bonds. This loss is called reorganization energy, but NREL researchers found little energy was lost when pairing SWCNT semiconductors with fullerene molecules.

“What we find in our study is this particular system — nanotubes with fullerenes — have an exceptionally low reorganization energy and the nanotubes themselves probably have very, very low reorganization energy,” said Jeffrey Blackburn, a senior scientist at NREL and co-author of the paper “Tuning the driving force for exciton dissociation in single-walled carbon nanotube heterojunctions.”

The paper appears in the new issue of the journal Nature Chemistry. Its other co-authors are Rachelle Ihly, Kevin Mistry, Andrew Ferguson, Obadiah Reid, and Garry Rumbles from NREL, and Olga Boltalina, Tyler Clikeman, Bryon Larson, and Steven Strauss from Colorado State University.

Organic PV devices involve an interface between a donor and an acceptor. In this case, the SWCNT served as the donor, as it donated an electron to the acceptor (here, the fullerene). The NREL researchers strategically partnered with colleagues at Colorado State University to take advantage of expertise at each institution in producing donors and acceptors with well-defined and highly tunable energy levels: semiconducting SWCNT donors at NREL and fullerene acceptors at CSU. This partnership enabled NREL’s scientists to determine that the electron transfer event didn’t come with a large energy loss associated with reorganization, meaning solar energy can be harvested more efficiently. For this reason, SWCNT semiconductors could be favorable for PV applications.