Samsung announces 4GB HBM2 DRAM

BY DR. PHIL GARROU, Contributing Editor

Samsung Electronics announced that it has begun mass producing the industry’s first 4-gigabyte (GB) DRAM package based on the second-generation High Bandwidth Memory (HBM2) interface, for use in high performance computing (HPC), advanced graphics and network systems, and enterprise servers.

The newly introduced 4GB HBM2 DRAM, uses Samsung’s 20nm process technology and is reportedly more than seven times faster than the current DRAM.

The 4GB HBM2 package is created by stacking a buffer die at the bottom and four 8-gigabit (Gb) core dies on top (FIGURE 1). These are then vertically interconnected by TSV holes and microbumps (FIGURE 2). A single 8Gb HBM2 die contains > 5,000 TSV holes, which is more than 36 times that of a 8Gb TSV DDR4 die, offering a dramatic improvement in data transmission performance compared to typical wire-bonding based packages.

Screen Shot 2017-04-21 at 12.24.14 PM Screen Shot 2017-04-21 at 12.24.20 PM

Samsung’s new DRAM package features 256 GBps of bandwidth, which is double that of a HBM1 DRAM package. This is equivalent to a more than seven-fold increase over the 36GBps bandwidth of a 4Gb GDDR5 DRAM chip, which has the fastest data speed per pin (9Gbps) among currently manufactured DRAM chips. Samsung’s 4GB HBM2 also enables enhanced power efficiency by doubling the bandwidth per watt over a 4Gb-GDDR5-based solution, and embeds ECC (error-correcting code) functionality to offer high reliability.

Samsung also plans to produce an 8GB HBM2 DRAM package in the next 12 months. This will offer designers a 95 percent space savings vs GDDR5 DRAM.

Samsung announced that production volume of HBM2 DRAM will increase over the remainder of the year.

The second-generation HBM (HBM2) technology is outlined by the JESD235A standard. It uses 128-bit DDR interface, 1024-bit I/O, 1.2 V I/O and core. Just like HBM1, HBM2 supports two, four or eight DRAM devices on a base logic die (2Hi, 4Hi, 8Hi stacks). HBM Gen 2 expands capacity of DRAM devices within a stack to 8 Gb and increases supported data-rates up to 1.6 Gb/s or even to 2 Gb/s per pin.

POST A COMMENT

Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.