BY JOHN HUNT, Senior Director, Engineering, Product Promotion, ASE Group, Tempe, AZ
When most people in packaging hear the term “Fan Out,” they usually think of the eWLB type of “chips first” fan out process/structure. This was the first of the embedded chips first structures to be taken into volume production by Infineon and ASE in Q1 2009. But this was not the end of the story. Today we speak of a chip first process and a chip last process building almost the same fan out structure.
Chips first fan out process describes a process where the singulated die are held in some form of matrix, followed by overmolding and the formation of the redistribution trace structure in situ on the surface of the die/matrix formation.
In contrast, chips last fan out process describes a process where the redistribution trace structure is formed first, sometimes on some type of temporary carrier, and then the singulated die are bonded using a flip chip assembly process onto this trace pattern, followed by overmolding of the package.
To the end user, it is the fan out package structure for the devices – active and passive – and the performance, cost and robustness of that package that really matters. How that fan out package structure is manufactured (i.e. processed) is of less importance. Packaging engineers are nothing but ingenious. Give them a challenge and they will find a way. For Fan Out, the good news is that there are two basic processes, Chip First and Chip Last, providing manufac- turing capacity to serve the end users.
As an example, ASE brought out a high volume chip last panel fan out solution to market in 2014 that provides a verysimilarfanoutstructuretotheeWLBfanoutstructure. And since that time, ASE has been in high volume production for several devices. In fact, one paper at ECTC 2016 describes the comparative similarity and differences of the Fan Out product for the same die built from these two different processes – chip first and chip last.
The Infineon Baseband chip was the first embedded chip first type of fan out to go into mass production and was well suited to the relatively low density, single chip requirements of that package. However, with the evolution of smart phone mobile devices, and the need for greater packaging densities, there is now a need for higher density fan out, often with multiple die, and the inclusion of passive devices within the fan out package structure. And it is this expanded appli- cation space for Fan Out – both for chip first and for chip last – that is getting the industry excited.
In January of this year, using a chip first wafer fan out solution, ASE released a high density fan out hybrid package structure with more than a thousand I/O, and multiple trace layers with very fine lines and spaces into production. It is clear that similar structures will also be built using a chip last process.
We can see that there are advantages and disadvantages in using each of these fan out process technologies, depending on the specific applications. Fan out chip last, however, has the advantage of an existing manufacturing infrastructure, with the promise of faster ramp up to high manufacturing yields. This is because the trace pattern can be inspected, and tested, and nearly known good die can be placed only on known good trace patterns. In contrast, for chip first, the die are committed by the time the trace pattern yield is deter- mined, and any bad trace patterns include the cost of these die in yield losses. Chip Last has also shown the promise of increased versatility in meeting the more complex require- ments of System in Package (SiP) applications.
We are seeing the transition of what had been a niche technology going into mainstream. The ingenuity and creativity of the packaging engineers are being tested as never before. And they have come out on top. As fan out comes of age, we shall find that there are applications and uses for more than one variation of structure and more than one variation of process. In the end, the market will help us to decide the most manufacturable and lowest cost solutions for each of the many different applications.