BY DR. PHIL GARROU, Contributing Editor
Toshiba was the first to commercially implement CMOS image sensors with backside TSV last technologies in 2007. Many of us stated in 2007 that further advances could be obtained by removing the CMOS circuitry to a separate layer and forming a true 3D chip stack, but the technology imple- mentation had to wait while the industry first converted to back side imaging technology.
With a conventional front-illumination structure, the metal wiring above the sensor’s photo-diodes impede photon gathering. A back-illuminated structure increases the amount of light that enters each pixel due to the lack of obstacles such as metal wiring and transistors that have been moved to the reverse of the silicon substrate.
The next generation, as expected, combined both BSI and stacking. Conventional CMOS image sensor technology creates the pixel function and analog logic circuitry on the same chip. The motivations for stacked chip CIS include: optimization of each function in the stack, adding function- ality to the stack and decreasing form factor.
Since the pixel section and circuit section are formed as independent chips, each function can be separately optimized, enabling the pixel section to deliver higher image quality while the circuit section can be specialized for higher functionality. In addition, faster signal processing and lower power consumption can also be achieved through the use of leading process for the chip containing the circuits.
The 2014 image sensor market was estimated by Techno Systems Research with Sony as the top seller of image sensors with 40.2% market share, followed by OmniVision (15.7%), Samsung (15.2%) and others with 28.9%.
Sony is clearly leading in commercializing the latest CIS packaging technologies. Some of the biggest names in tech use Sony sensors: The iPhone 6 camera has a Sony sensor, as does the Samsung Galaxy S6, Motorola phones, Nikon DSLRs, and Olympus mirrorless cameras.
Earlier in 2016 it was reported that there are two versions of the Samsung Galaxy S7. One has a Samsung stacked ISOCELL sensor (S5K2L1) and the other a special Sony stacked sensor (IMX260).
The recent Chipworks teardown of the Samsung Galaxy S7 with a Sony IMX 260 revealed BSI stacked technology. Furthermore, it revealed the first reported use of the Ziptronix (now Tessera) Direct Bond interconnect (DBI) technology rather than prior oxide –oxide bonding with subsequent TSVs connecting through the oxide interface. This BSI-stacked DBI technology is possibly the next step in the CIS roadmap.
The Chipworks cross-section reveals a 5 metal (Cu) CMOS image sensor (CIS) die and a 7 metal (6 Cu + 1 Al) image signal processor (ISP) die. The Cu-Cu vias are 3.0 μm wide and have a 14 μm pitch in the peripheral regions. In the active pixel array they are also 3.0 μm wide, but have a pitch of 6.0 μm.
Omnivision was the first to sample BSI in 2007 but costs were too high and adoption was thus very low. In 2015 Omnivision announced their OV 16880 a 16-megapixel image sensor built on OmniVision’s PureCel-STM stacked die technology.
Samsung’s first entrant into stacked technology with TSV was also at 16MP with the Samsung S5K3P3SX in late 2014. The CIS die is face-to-face bonded to a 65nm Samsung image signal processor die and connected with W based TSV. The CIS die is fabricated on a 65nm CMOS process with 5 levels of interconnect.
In early 2015 On Semiconductor (Aptina) introduced its first stacked CMOS sensor the AR 1335 with 1.1μm pixels. It resulted in a smaller die footprint, higher pixel performance and better power consumption compared to their traditional monolithic non-stacked designs. They announced that it would be introduced in commercial products in late 2015.
In late 2015, Olympus announced the OL 20150702-1 a new 3D stacked 16MP CMOS image sensor.