The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016.

For more than six decades, the annual IEEE International Electron Devices Meeting (IEDM) has been the world’s largest and most influential forum for technologists to unveil breakthroughs in transistors and related micro/nanoelectronics devices.

That tradition continues this year with a few new twists, including a supplier exhibition and a later paper- submission deadline (August 10) of a final, four-page paper. Accepted papers will appear in the proceedings without any changes. This streamlined process will ensure that even as the pace of innovation in electronics quickens, IEDM remains the place to learn about the latest and most important developments.

The 62nd annual IEDM will be held in San Francisco December 3 – 7, 2016, beginning with a weekend program of 90-minute tutorials and all-day Short Courses taught by industry leaders and world experts in their respective technical disciplines. These weekend events will precede a technical program of some 220 papers and a rich offering of other events including thought-provoking plenary talks, spirited evening panels, special focus sessions on topics of greatinterest,IEEE awards and an event for entrepreneurs sponsored by IEDM and IEEE Women in Engineering.

“The industry is moving forward at an accelerated pace to match the increasing complexity of today’s world, and a later submission deadline enables us to shorten the time between when results are achieved in the lab and when they are presented at the IEDM,” said Dr. Martin Giles, IEDM 2016 Publicity Chair, Intel Fellow, and Director of Transistor Technology Variation in Intel’s Technology and Manufacturing Group.

Tibor Grasser, IEDM 2016 Exhibits Chair, IEEE Fellow and Head of the Institute for Microelectronics at TU Wien, added, “We have decided to have a supplier exhibition in conjunction with the technical program this year, as an added way to provide attendees with the knowledge and information they need to advance the state-of-the-art.”

Here are some of the noteworthy events that will take place at this year’s IEDM:

Special Focus Sessions

• Wearable Electronics and Internet of Things (IoT) – Wearable technology offers great promise for communica- tions, fitness tracking, health monitoring, speech therapy, elder care/assisted living and many other applications. This Special Focus Session has been organized to benchmark wearable electronics technologies, to address applications with comprehensive system demonstrations, and to learn indus- trial perspectives about the gaps, challenges and opportu- nities for wider uses of wearable and IoT technologies. Papers on flexible/stretchable electronics, MEMs, display devices, sensors, printed electronics, organic devices and 2-D material devices enabling wearables/IoT devices also will be featured.

• Quantum Computing – As traditional CMOS scaling enters the post-Moore’s Law era, quantum computing has emerged as a possible candidate for further device scaling because it exploits the laws of quantum physics and may make much more powerful computers possible. This Special Focus Session will explore relevant semiconductor-related fabri- cation issues and will brainstorm R&D directions for new materials, devices, circuits, and manufacturing approaches for the scalable integration of a large number of qubits with CMOS technology, operating at cryogenic temperatures for the realization of quantum computers.

• System-Level Impact of Power Devices – While there are forums that serve circuit experts for the exchange of ideas and the reporting of breakthroughs, there hasn’t been a suitable forum for bringing device and circuit experts together to consider impacts at the system level, even though that would be fruitful due to the interactions of circuits and devices. IEDM aims to serve as the forum for their dialogue, and so this Special Focus Session has been organized. Papers are expected to explore the system-level impact of power devices, and also to describe various types of power devices targeting the full range of power/power conversion applications such as hybrid vehicles, utility and grid control, computing/telecom power supplies, motor drives, and wireless power transfer.
• Ultra-High-Speed Electronics – There have been many advances and breakthroughs in ultra-high-speed electronics for communications, security and imaging applications, but technology gaps continue to prevent spectrum above milli- meter-wave frequencies from being fully used. This Special Focus Session has been organized to discuss, showcase and benchmark advanced ultra-high speed devices and circuits based on high-electron-mobility transistors (HEMTs), hetero- junction bipolar transistors (HBTs) and conventional CMOS devices; high-speed interconnect; antennas for ultra-high- speed systems; ultra-high-frequency oscillators; and to discuss other possible applications.

90-Minute Tutorials – Saturday, Dec. 3

A program of 90-minute tutorial sessions on emerging technologies will be presented by experts in the fields, to bridge the gap between textbook-level knowledge and leading-edge current research. Advance regis- tration is recommended.

• The Struggle to Keep Scaling BEOL, and What We Can Do Next, Dr. Rod Augur, Distinguished Member of the Technical Staff, GlobalFoundries – Looking ahead, it’s the interconnect that threatens further cost-effective scaling. The tutorial will cover challenges and trade-offs in back- end-of-the-line(BEOL)scaling,andwillevaluateemerging devices from a scaled-BEOL viewpoint.

• Electronic Circuits and Architectures for Neuro- morphic Computing Platforms, Prof. Giacomo Indiveri, Univ. of Zurich and ETH Zurich – This tutorial will cover the principles and origins of neuromorphic (i.e., brain-inspired) engineering, examples of neuromorphic circuits, how neural network architectures can be used to build large-scale multi-core neuromorphic processors, and some specific application areas well-suited for neuromorphic computing technologies.

• Physical Characterization of Advanced Devices, Prof. Robert Wallace, Univ. Texas at Dallas – This tutorial will cover the hardware, physics, and chemistry that enable modern physical characterization of novel electronic materials, and will explore how these techniques can shed light on electronic materials research and development, and on the resultant devices. In addition to introducing examples of novel electronic materials for device applications, example techniques discussed will include high-resolution electron microscopy, scanning tunneling microscopy and spectroscopy, dynamic x-ray photoelectron spectroscopy, and ion mass spectrometry. The detection limits of these techniques and how they relate to device behavior also will be discussed.

• Present and Future of FEOL Reliability—from Dielectric Trap Properties to Reliable Circuit Operation, Dr. Ben Kaczer, Principal Scientist, Imec – This tutorial will introduce the main degradation mechanisms occurring in present-day CMOS. The reliability of novel devices (SiGe, IIIV, gate-all-around nanowires, junctionless FETs, tunnel FETs), of deeply-scaled devices, and of circuits (e.g., “reliability-aware” designs) will be covered in detail. The tutorial will give attendees an overview and background in this area sufficient to allow them to follow and participate in any discussion on reliability in general, and on front-end- of-the-line (FEOL) reliability in particular.

• Spinelectronics: From Basic Phenomena to Magneto- resistive Memory (MRAM) Applications, Dr. Bernard Dieny, Chief Scientist, Spintec CEA — This tutorial will cover spintronics phenomena, magnetic tunnel junctions (growth, magnetic and transport properties), field-written MRAM (toggle and thermally assisted MRAM), STT-MRAM (principle and status of development), 3-terminal MRAM andinnovativearchitecturesthatbenefitfromthesehigh- endurance non-volatile memories.

• Technologies for IoT and Wearable Applications, Including Advances in Cost-Effective and Reliable Embedded Non-Volatile Memories, Dr. Ali Keshavarzi, Vice President of R&D, Cypress Semiconductor — This tutorial will coverarangeoftechnologyopportunitiesforIoTandwearable applications, including embedded non-volatile memories (eNVM), IPs and integrated solutions based on charge-trap memory technologies such as SONOS for low power (LP) and ultra-low-power (ULP) for advanced technology nodes. Technologies will be described for various integrated IoT, wearableandenergy-harvestingsystemsusingprogrammable systems-on-chips (SoCs) with digital and analog capabilities, along with low-energy Bluetooth radio, WiFi radio, solar cells, sensors, actuators, and power management ICs. Advanced small form-factor packaging technologies useful for system integration also will be described.

Short Courses – Sunday, Dec. 4

The Short Courses provide the opportunity to learn about important areas and developments, and to benefit from direct contact with world experts. Advance regis- tration is recommended.

1. Technology Options at the 5-Nanometer Node, organized by An Steegen and Dan Mocuta of Imec (Sr. Vice President of Technology Development/Director of Logic Device and Integration, respectively) – This course will describe the complex technological challenges at the 5nm node and explore innovative potential solutions. It begins with an in-depth discussion of patterning strategies being pursued to print critical features. Then, a pair of lectures will provide an overview of current transistor technologies and their relative strengths/ weaknesses in the context of various applications such as mobility, data centers and IoT. Strategies for effective mitigation of performance-limiting parasitic resistance and capacitance will be discussed, and advanced interconnect technologies including post- copper materials options for BEOL and MEOL appli- cations will be addressed. Lastly, metrology challenges for in-line and end-of-line process technologies will be discussed. The intent of the course is to provide a thorough understanding in process technology targets at the 5nm node and their potential solutions. Attendees will have the opportunity to learn about advanced technology options that are being actively pursued in the industry from leading technologists.

The course consists of lectures from six distinguished speakers:

• Nano Patterning Challenges at the 5nm Node, Akihisa Sekiguchi, VP & Deputy GM, SPE Marketing and Process Development Division, Tokyo Electron, Japan

• Novel Channel Materials for High-Performance and Low-Power CMOS, Nadine Collaert, Distinguished Member of the Technical Staff, imec, Belgium

• Transistor Options & Challenges for 5nm Technology, Aaron Thean, Professor of Electrical & Computer Engineering, National University of Singapore

• Low Resistance Contacts to Enable 5nm Node Technology: Patterning, Etch, Clean, Metallization and Device Performance, Reza Arghavani, Managing Director, Lam Research, USA

• Parasitic R and C Mitigation Options for BEOL and MOL in N5 Technology, Theodorus Standaert, Sr. Engineering Mgr., Manager, Process Integration, IBM, USA

• Metrology Challenges for 5nm Technology, Ofer Adan, Technologist and Global Product Manager, Member of the Technical Staff, Applied Materials, Israel

2. Design/Technology Enablers for Computing Applications, organized by John Chen, Vice President of Technology and Foundry Management, NVIDIA – This course will describe how various design techniques and process technologies can enable computing applications, beginning with the relative advantages and disadvantages of processors such as CPU, GPU and FPGA with regard to today’s high data demands. It then will cover how memory becomes a bottleneck, and will discuss various emerging memory technol- ogies to mitigate the problem. Because managing power dissipation has become critical, it also will offer a broad perspective on power efficiency in computing and how interconnect plays a pivotal role in both performance and energy efficiency. Finally, 2.5-D and 3-D advanced packaging technology is discussed for system integration.

The course consists of lectures from five distinguished speakers:

• The Rise of Massively Parallel Processing: Why the Demands of Big Data and Power Efficiency are Changing the Computing Landscape, Liam Madden, Corporate VP, Hardware & Systems Development, Xilinx, USA

• Breaking the Memory Bottleneck in Computing Applications with Emerging Memory Technologies: a Design and Technology Perspective, Gabriel Molas, PhD Engineer, Leti, France

• Power Management with Integrated Power Devices… and how GaN Changes the Story, Alberto Doronzo, Power System/Apps Engineer, Texas Instruments, USA

• Interconnect Challenges for Future Computing, William J. Dally, Chief Scientist and Sr. VP of Research, NVIDIA, and Stanford Professor, USA

• Advanced Packaging Technologies for System Integration, Douglas Yu, Sr. Director, TSMC, Taiwan