Smartphone Market Driving 7nm & 5nm Node 3-D Transistors and Stacked Devices


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Date: December 15, 2016 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

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The smartphone market is expected to reach 1.5B units in 2016 consuming nearly 1/3 of the IC market as smartphones become the mini mobile computers in capabilities and the central hub/gateway for the Internet of Things (IoT) devices including wearables and home monitoring devices. Since 2011 the high end smartphone application processor (AP) has advanced a logic technology node every year using 45nm technology in 2011 for the Apple A5 AP in the iPhone 4s to the introduction of 14/16nm FinFET technology in 2015 for the iPhone 6s/6s+ A9 and also the Samsung Galaxy S6. This year (2016) the Galaxy S7 still uses 14nm FinFET and the iPhone 7/7+ A10 uses 16nm FinFET, but with the announcements from both Samsung and TSMC in Oct 2016 of their production start of 10nm FinFETs, smartphone APs using 10nm FinFET technology will appear in 2017 starting with the Samsung Galaxy S8 in March and then iPhone 7s in September.  At the 2016 VLSI Symposium in June both Samsung and TSMC papers mentioned their key improvements in 10nm technology over 14/16nm technology were in channel mobility enhancement, S/D-epi doping and contact resistance (Rc) reduction with a complete session #7 dedicated to papers on Rc. In 2018/19 smartphone AP using 7nm FinFET with single or dual high mobility strained-channel material replacing raised S/D-epi stressors to further boost device performance and improved Rc will appear. At the Oct 2016 ECS PRiME conference there were several papers describing options and issues for relaxed and strained high mobility SiGe and Ge channel materials reported in the “Symposium on High Purity and High Mobility Semiconductor 14” and “Symposium on SiGe, Ge and Related Materials”.  Then by 2020/21 5nm FinFET, lateral-GAA (gate-all-around) Si or Ge nanowire or Monolithic 3-D vertical stacked transistors using thin wafer bonding like LETI’s CoolCube are options for More Moore scaling.  More than Moore 3-D stacked devices are also being driven by the smartphone market to achieve small compact packaging.  Sony introduced the first stacked backside CMOS image sensor with the pixel array on top of the logic circuit using TSV (through silicon via) and this was incorporated into the Apple iPhone 5 in 2012 as an 8Mpixel rear facing camera. This year Sony’s 3rd generation stacked 3-D 12Mpixel rear camera that uses wafer to wafer bonding called Hybrid DBI (direct bond interconnect) was introduced into the Samsung Galaxy S7 smartphone. The first 3-D NAND Flash memory was introduced in the Apple iPhone7/7+ by Toshiba as a 256Gb 48-layer 3-D NAND while the optional 128Gb Flash is a 2-D NAND using 15nm technology from Toshiba or SK Hynix. Therefore, this will give an update to the previous April 30, 2015 Webinar on Smartphone as the technology driver.

John BorlandSpeaker: John Borland, J.O.B. Technologies

John Ogawa Borland received his B.S. and M.S. degrees for MIT. He completed his BS thesis on InP liquid phase epitaxial growth at Hughes Malibu Research Labs in 1980 and his MS thesis on InP molecular beam epitaxial growth at Nippon Telephone and Telegraph (NTT) Labs in Musashino, Tokyo, Japan in 1981. He is a senior member of IEEE, the IEEE Hawaii section chair (2014-present), the chair for the Hawaii joint EDS/SSCS chapter and on the advisory committee for the IEEE International Workshop on Junction Technology (2008-2016). He is also a member of the Electrochemical Society (ECS) and was co-organizer for various ECS technical conferences/symposium including the “Symposium on ULSI Process Integration” (2001, 2003 & 2005), “Semiconductor Silicon” (1994 & 1998) and “Chemical Vapor Deposition” (1987, 1989, & 1991). He has published over 140 technical and invited papers around the world in the areas of advanced semiconductor device manufacturing techniques and high efficiency c-Si solar cells and has been awarded 6 patents. Currently he is President of J.O.B. Technologies a strategic technical marketing consulting company he founded in June 2003 providing service to the semiconductor device manufacturing, equipment and metrology companies in the area of advanced front end of line process technology with the current focus on 7nm and 5nm technology. This includes localized high mobility compressive and tensile strain channel material formation (SiGe, SiC, SiGeSn, Ge, GeSn, GeSi and GeC) and high dopant activation using advanced annealing and metrology techniques. He was Director of Operations of APIC’s subsidiary Advanced Integrated Photonics a silicon photonics development Fab in Honolulu, Hawaii from April 2013 to its shutdown in August 2014 with focus on Ge technology for Ge photo detector dark current leakage reduction by 300x and Si-waveguide performance improvements. From July 1998 to May 2003 he was Director of Advanced Business Development at Varian Semiconductor Equipment Associates pioneering Ultra Shallow Junction by beam-line and plasma implantation with high dopant activation and low junction leakage. From Nov. 1992 to July 1998 he was Vice President of Strategic Technology at Genus pioneering high energy ion implantation for CMOS twin-well, triple-well and epi replacement on the implant side and on the CVD side integrated CVD polycide and selective HF vapor cleaning. From Sept. 1983 to Nov. 1992 he was at Applied Materials pioneering CMOS-epi latch-up immunity, epi-gettering, selective epi growth (SEG/ELO) for device isolation and low temperature low pressure single wafer epi and poly system development (Centura-epi and Centura-poly). From Aug. 1981 to Sept. 1983 he was at National Semiconductor Corp. developing the 1.25um VHSIC-CMOS front end processing including intrinsic gettering to improve gate oxide integrity and improved CMOS latch-up immunity through retrograde well, buried layer and epilayer engineering.

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