Yearly Archives: 2016

Key features of the cell structure, design and integration of the Micron 3D 32L FG-NAND device are discussed, and compared with Samsung’s 32L and 48L V-NAND device.

BY JEONGDONG CHOE, Ph. D., Senior Technical Fellow at TechInsights, Ottawa, Canada

The Intel/Micron 1st generation 3D TLC NAND with FG (floating gate) structure is finally on the market. TechInsights has torn down Micron’s Crucial MX300 750 GB 2.5-inch SSD and reverse engineered Micron’s 3D FG-NAND. The SSD has eight 3D NAND packages with 6FB22 NW852 package markings on the board, and two NAND dice in each package. We discuss some key features of the cell structure, design and integration of the Micron 3D 32L (32 layers or 32T, 32 Tiers) FG-NAND device, and compare with Samsung’s 32L and 48L V-NAND device.

Die size and memory density

Micron’s 32L 3D NAND die size (168.2 mm2) is much larger than Samsung’s 32L (84.3 mm2) and 48L (99.8 mm2) 3D V-NAND devices. Micron’s 32L 3D NAND memory size is 48 GB/die (384 Gb/die) which is more than 4 times Samsung 32L V-NAND (85.3Gb/die) and 1.5 times their 48L V-NAND (256 Gb/die). In other words, the memory density for the Intel/Micron 32L 3D NAND is 2.28 Gb/ mm2, while Samsung’s 32L V-NAND and 48L V-NAND are 1.01 Gb/mm2 and 2.57 Gb/mm2, respectively. FIGURES 1 and 2 show comparisons of memory density and memory array efficiency for the Micron 32L, Samsung 32L and 48L 3D NAND memories. Micron’s 2.28 Gb/mm2 memory density is the same as their announcement in 2015 at IEEE IEDM. They announced another 3D NAND with 768 Gb/ die TLC (which is 4.29 Gb/mm2) earlier this year at ISSCC 2016. We can find a gap between the two announcements, including memory density difference (2.28 Gb/mm2 and 4.29 Gb/mm2). They might further shrink bitline pitch to 40 nm or expand to 48 layers. Comparing the 32L 3D NAND devices, the memory density on Intel/Micron’s 1st generation 3D NAND is more than two times Samsung’s 32L 3D NAND. Although Micron jumped into the 3D NAND race two years later than Samsung, Micron beat Samsung’s 32L 3D NAND devices and came close to Samsung’s 48L ones by using CMOS circuit under the memory array. We’re looking forward to seeing their 2nd generation (either a modified 32L or a new 48L) FG-NAND.

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3D memory cell architecture

As shown on FIGURE 3, the Intel/Micron 1st generation 3D FG-NAND (32L or 32T) has 4 planes with 32 tiles; while Samsung’s 3D V-NAND, either 32L (2nd generation) or 48L (3rd generation), has 2 planes without a tile-like floor plan. An innovative technology from Micron is that CMOS decoders and sense-amps are sitting under the 3D FG-NAND memory array for high memory density (2.28 Gb/mm2). Referring to the memory tiles comprised of page buffer (PB), string drivers and CMOS circuits, the area of unit memory tile is 4.12 mm2. The 1 kB page buffer, string drivers and other CMOS circuits on each memory tile have 2.20 mm2, 0.83 mm2 and 1.09 mm2 areas, respec- tively (FIGURE 4). As Micron mentioned at ISSCC 2016, placement of the wordline drivers under the array allows for the wordline lengths to be short.

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Micron’s 32L 3D FG-NAND uses a 4 metal CMOS plus FG-NAND array on common source plate technology. The FG-NAND array has 32 active wordlines, 6 dummy wordlines (3 on the top portion and 3 on the bottom portion), one source-side select gate and one drain-side select gate. All of the wordlines and select gates are on a Si/W-silicide-based common source plate. The NAND array has 40 gates (38 wordlines plus 2 select transistors), which is different from Samsung’s 32L V-NAND which has 39 gates (36 wordlines plus 3 select transistors).

Micron’s V-NAND uses a vertical Si-channel surrounded by a floating gate (FG) and a control gate (CG), termed a ‘gate all around (GAA)’ structure. The vertical Si-channel and control gate stacked memory cell structure is the same as Samsung’s, however, Micron uses a silicon FG (floating gate) layer instead of Samsung’s SiN charge trap layer (CTL). The FG layer is far better way to store more electrons than a SiN layer. Micron’s 52 nm 32L NAND array vertical cell gate pitch is less than Samsung’s 60 nm 32L V-NAND vertical cell gate pitch. Micron’s memory cell array (or Si-channel hole) height is 2.21 μm, which is 27% lower than that of Samsung 32L (2.9 μm).

Micron’s 3D FG-NAND cell architecture has a ‘CG/FG first, Channel last’ scheme, while Samsung’s 3D V-NAND cell integration has a ‘Channel first, Gate last’ scheme. Micron’s process involves first making the control gate/ dielectric stack. A recess etch would have been used to form cavities for the polysilicon floating gates (FG) and inter-poly dielectrics. The deposition of the tunnel oxide and polysilicon channel would complete then NAND string. An etch-back processes is applied for both CG and FG structures to recess and isolate the gates.

Micron’s 2D 16 nm node planar thin-FG NAND Flash has a select gate with the same structure as the cell, which has a high-k dielectric stack and a thin polysilicon floating gate. To simplify the manufacturing of the 16 nm cell, the source and drain select gates are constructed in a similar manner as the cell. In contrast, Micron’s 3D FG-NAND device has a select gate composition that is different from cell gate. Here, the source and drain select devices are single gate oxide transistors.

Placing the select gates and dummy wordlines under and on the memory cell gates looks reasonable from an integration perspective. Intel/Micron and Samsung have the same configuration of dummy wordlines near the select transistors, but Samsung has a SEG (Si epitaxial growth) channel on GST (ground select transistor) structure. Micron uses a single select gate with a thick gate length (thickness) on the drain side, while Samsung has two thin SSTs (string select transistors). FIGURE 5 shows a comparison of 3D cell gate structure on Samsung and Intel/Micron 32L NAND devices.

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3D NAND competition and roadmap

When Micron will produce 48L 3D FG-NAND commercial products is an open question. FIGURE 6 shows a NAND roadmap for the major players of 3D NAND products (Samsung, Micron/Intel, Toshiba/SanDisk and SK-hynix). Samsung has 48L V-NAND SSD products and they are developing 64L for their next generation 3D V-NAND. Samsung has been more focused on 3D V-NAND devel- opment including yield improvement and 64L V-NAND than next generation 2D NAND (1z nm). Intel/Micron have just entered the V-NAND race with their 32L FG-NAND. Once they successfully release 48L and 64L, if in a timely manner, they may gain market share at the expense of Samsung, Toshiba and SK hynix. Toshiba and SanDisk are scheduled to release their 3D BiCS NAND products to compete in the 3D NAND sector soon.

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Intel/Micron’s 1st generation 3D FG-NAND devices with 32L (or 32T) are quite compatible with Samsung’s 32L 3D V-NAND. Samsung and Toshiba use a CTL (charge trap layer), while Micron adopted thin-FG silicon layer as a storage between channel and CG. Although Micron’s thin-FG layer contains more electrons than Samsung’s CTL SiN layer, the etch-back process used to isolate the FG layers may result in non-uniform FG sizes and coupling ratios. Furthermore, the FG layer is getting smaller and may form nanowire-like or nanodot-like structures on the Si cylinder during the process integration creating perfor- mance non-uniformities. Samsung’s CTL scheme does not suffer as much from process non-uniformities giving it an advantage. Additionally the CTL does not require isolation between each of the stacked cell gates.

Which is better? Intel/Micron’s 32L 3D FG-NAND or Samsung’s 32L (or 48L) 3D V-NAND? From the memory cell structure and process integration viewpoints, Samsung looks better than the Intel/Micron design due to the CTL scheme. From the die efficiency and memory density viewpoints, Intel/Micron’s CMOS circuit layout under the memory array has an advantage over Samsung’s conventional die floor plan.

Should Micron scale down the bitline pitch from 80 nm to 40 nm, it would be a memory
density advantage to them. We can discuss further after circuit, device and waveform analyses on Intel/Micron’s 3D NAND devices.

This article originally appeared on SemiMD.com and was featured in the Aug/Sept. 2016 issue of Solid State Technology. 

By Ed Korczynski, Sr. Technical Editor

In-the-know attendees at SEMICON West at a Thursday morning working breakfast heard from executives representing the world’s leading memory fabs discuss manufacturing challenges at the 4th annual Entegris Yield Forum. Among the excellent presenters was Norm Armour, managing director worldwide facilities and corporate EHSS of Micron. Armour has been responsible for some of the most famous fabs in the world, including the Malta, New York logic fab of GlobalFoundries, and AMD’s Fab25 in Austin, Texas. He discussed how facilities systems effect yield and parametric control in the fab.

Just recently, his organization within Micron broke records working with M&W on the new flagship Fab 10X in Singapore—now running 3D-NAND—by going from ground-breaking to first-tool-in in less than 12 months, followed by over 400 tools installed in 3 months. “The devil is in the details across the board, especially for 20nm and below,” declared Armour. “Fabs are delicate ecosystems. I’ll give a few examples from a high-volume fab of things that you would never expect to see, of component-level failures that caused major yield crashes.”

Ultra-Pure Water (UPW)

Ultra-Pure Water (UPW) is critical for IC fab processes including cleaning, etching, CMP, and immersion lithography, and contamination specs are now at the part-per-billion (ppb) or part-per-trillion (ppt) levels. Use of online monitoring is mandatory to mitigate risk of contamination. International Technology Roadmap for Semiconductors (ITRS) guidelines for UPW quality (minimum acceptable standard) include the following critical parameters:

  • Resistivity @ 25C >18.0 Mohm-cm,
  • TOC <1.0 ppb,
  • Particles/ml < 0.3 @ 0.05 um, and
  • Bacteria by culture 1000 ml <1.

In one case associated with a gate cleaning tool, elevated levels of zinc were detected with lots that had passed through one particular tool for a variation on a classic SC1 wet clean. High-purity chemistries were eliminated as sources based on analytical testing, so the root-cause analysis shifted to to the UPW system as a possible source. Then statistical analysis could show a positive correlation between UPW supply lines equipped with pressure regulators and the zinc exposure. The pressure regulator vendor confirmed use of zinc-oxide and zinc-stearate as part of the assembly process of the pressure regulator. “It was really a curing agent for an elastomer diaphragm that caused the contamination of multiple lots,” confided Armour.

UPW pressure regulators are just one of many components used in facilities builds that can significantly degrade fab yield. It is critical to implement a rigorous component testing and qualification process prior to component installation and widespread use. “Don’t take anything for granted,” advised Armour. “Things like UPW regulators have a first-order impact upon yield and they need to be characterized carefully, especially during new fab construction and fit up.”

Photoresist filtration

Photoresist filtration has always been important to ensure high yield in manufacturing, but it has become ultra-critical for lithography at the 20nm node and below. Dependable filtration is particularly important because industry lacks in-line monitoring technology capable of detecting particles in the range below ~40nm.

Micron tried using filters with 50nm pore diameters for a 20nm node process…and saw excessive yield losses along with extreme yield variability. “We characterized pressure-drop as a function of flow-rate, and looked at various filter performances for both 20nm and 40nm particles,” explained Armour. “We implemented a new filter, and lo and behold saw a step function increase in our yields. Defect densities dropped dramatically.” Tracking the yields over time showed that the variability was significantly reduced around the higher yield-entitlement level.

Airborne Molecular Contamination (AMC)

Airborne Molecular Contamination (AMC) is ‘public enemy number one’ in 20nm-node and below fabs around the world. “In one case there were forrest fires in Sumatra and the smoke was going into the atmosphere and actually went into our air intakes in a high volume fab in Taiwan thousands of miles away, and we saw a spike in hydrogen-sulfide,” confided Armour. “It increased our copper CMP defects, due to copper migration. After we installed higher-quality AMC filters for the make-up air units we saw dramatic improvement in copper defects. So what is most important is that you have real-time on-line monitoring of AMC levels.”

Building collaborative relationships with vendors is critical for troubleshooting component issues and improving component quality. “Partnering with suppliers like Entegris is absolutely essential,” continued Armour. “On AMCs for example, we have had a very close partnership that developed out of a team working together at our Inotera fab in Taiwan. There are thousands of important technologies that we need to leverage now to guarantee high yields in leading-node fabs.” The Figure shows just some of the AMCs that must be monitored in real-time.

Big Data 

The only way to manage all of this complexity is with “Big Data” and in addition to primary process parameter that must be tracked there are many essential facilities inputs to analytics:

  • Environmental Parameters – temperature, humidity, pressure, particle count, AMCs, etc.
  • Equipment Parameters – run state, motor current, vibration, valve position, etc.
  • Effluent Parameters – cooling water, vacuum, UPW, chemicals, slurries, gases, etc.

“Conventional wisdom is that process tools create 90% of your defect density loss, but that’s changing toward facilities now,” said Armour. “So why not apply the same methodologies within facilities that we do in the fab?” SPC is after-the-fact reactive, while APC is real-time fault detection on input variables, including such parameters as vibration or flow-rate of a pump.

“Never enough data,” enthused Armour. “In terms of monitoring input variables, we do this through the PLCs and basically use SCADA to do the fault-detection interdiction on the critical input variables. This has been proven to be highly effective, providing a lot of protection, and letting me sleep better at night.”

Micron also uses these data to provide site-to-site comparisons. “We basically drive our laggard sites to meet our world-class sites in terms of reducing variation on facility input variables,” explained Armour. “We’re improving our forecasting as a result of this capability, and ultimately protecting our fab yields. Again, the last thing a fab manager wants to see is facilities causing yield loss and variation.”

—E.K.

TSMC’s UBM-free fan-in WLCSP


September 21, 2016

BY DR. PHIL GARROU, Contributing Editor

At the 2016 ECTC Conference, TSMC discussed their UFI (UBM-Free Integration) Fan-In WLCSP technology which they claim enables large die fine pitch packages.

Development of low-cost WLCSP for large die with high I/O count is desired for broadening its applications. Reliability issues including solder cracking and high chip warpage are known to be the main challenges for extending the die size of conventional WLCSP to more than 5×5 mm2 with ball pitch smaller than 350 μm.

TSMC has discovered that by controlling the maximum strain location and optimizing materials, chip warpage and the stress between silicon and the PCB can be reduced which improves both component and board-level reliabilities of WLCSP packages. Packages as large as 10.3×10.3 mm2 with both 400 and 350 μm ball pitches have been developed.

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UBM is used as an interfacial layer between the metal pad of the integrated circuit and the solder ball. The formation of UBM/ solder intermetallic compounds (IMC) limits the board level reliability of the package due to the poor mechanical robustness of IMCs. When the die size is increased, stress increases which promotes cracking at the UBM/solder ball interface.

TSMC claims their UFI WLCSP fabrication cost is lower than conventional WLCSPs due to the elimination of the UBM. Removal of the UBM also reduces the thickness of the package by 30%. Figure 1 compares the structures of a standard WLCSP vs the TSMC UFI WLCSP. In the UFI WLCSP, the solder balls are directly mounted to the Cu RDL followed by the polymeric PL (protection layer which secure the balls.

Very similar removal of UBM and subsequent thickening of the copper pad has been reported before by Amkor in 2010 [1].

TSMC simulation results showed the solder joint fatigue life decreases with increasing die sizes for both UFI and the conventional WLCSP. Predicted solder ball fatigue life was found to increases with decreasing die thickness. The authors suggest that decreasing the die thickness not only reduces the thermal expansion difference between the die and the PCB, but also causes the die to bend more under thermal loading. In addition, simulation results imply that solder joint creep strain for solder mask defined (SMD) structures is 72% higher than for non-solder mask defined (NSMD) structures because of its reduced flexible solder joint height and the constraint of the solder mask. Thus they concluded that it is better to use NSMD type of PCB for UFI WLCSP. The use of NSMD structures to increase reliability has been known since the work of Bell Labs Ejim [2].

The UFI WLCSP passes all component-level tests and exhibited board-level thermal cycle life that is 1.4 and 2.3 times longer than that of the conventional WLCSP in terms of the first failure and the Weibull distribution, respectively. 10mm UFI WLCSP have passed component-level reliability tests such as TCB1000, uHAST96 and HTS1000, and board- level reliability tests of TCG500 and drop tests.
To demonstrate the possibility of higher interconnect density, they fabricated UFI- WLCSP with multiple RDL layers. The package with two RDL layers had die size of 10.3 x 10.3 mm2 and ball pitch of 350 μm (Figure 2). Again such structures passed all component level reliability testing.

References

1. http://imapsource.org/doi/abs/10.4071/2010DPC- tha32?journalCode=apap
2. TI Ejim et. al., “Reliability performance and failure mode of high I/O thermally enhanced ball grid array packages” Electronics Manufacturing
Technology Symposium, 1998, p.323 – 332.

A changing industry


September 21, 2016

BY PETE SINGER, Editor-in-Chief

The semiconductor industry is changing in some big ways. Demand for PCs and mobile devices – once the main drivers of growth – has slowed. Gains from traditional scaling are harder to come by. Cost per transistor is now increasing. Consolidation is widespread up and down the supply chain, which may slow innovation. ITRS efforts have been abandoned.

Yet, despite this “maturing” of the industry – at least as we know it — opportunities abound. The Internet of Things (IoT) is set to explode, which will result in a demand for “things” such as sensors and actuators, but also cloud computing.

Earlier this year, Brian Krzanich, CEO of Intel, wrote about five core beliefs that he holds to be “undeniably true” for the future:

• The cloud is the most important trend shaping the future of the smart, connected world – and thus Intel’s future.
• The many “things” that make up the PC Client business and the Internet of Things are made much more valuable by their connection to the cloud.
• Memory and programmable solutions such as FPGAs will deliver entirely new classes of products for the data center and the Internet of Things.
• 5G will become the key technology for access to the cloud and as we move toward an always-connected world.
• Moore’s Law will continue to progress and Intel will continue to lead in delivering its true economic impact.

While it’s true that it’s difficult to forecast what the overall impact of the IoT movement will have on the semiconductor industry, or how big it will be. Speaking at The ConFab in June, Tom Caulfield, SVP and GM of Fab 8 at GLOBALFOUNDRIES, said the IoT opportunity represents
“magnitudes that are well beyond anything we’ve done before.” A recent McKenzie study estimates $50-75 billion dollars of additional semicon- ductor revenue in an industry that today is $350 billion.

IoT, cloud computing and 5G will result in increased demand for leading edge semiconductor technology, which in turn will create a demand for 7 and 5nm devices and beyond. Perhaps more importantly, there will be tremendous demand for a wider variety of solid state devices, including MEMS, LEDs, power electronics, biomedical devices, thin film batteries and photonics/plasmonics.

There will be a need to integrate these devices for the usual reasons: to improve performance, and reduce cost and size. This will lead to innovative new packaging strategies and better chip-package co-design tools. It will create a demand for new types of manufacturing equipment and materials. New business models and new approaches to collaboration will also be required.

In short, the semiconductor industry is going through some fundamental changes, but the future has never looked brighter. As Caulfield said at The ConFab, “The demand for silicon is going to grow in an incredible way. What we need to do in this industry, is what we’ve done all along. We’ve reinvented ourselves every 18 months to 2 years with Moore’s Law. Now we have to start reinventing ourselves in how we engage and collaborate together.”

Applied Materials, Inc. today introduced the display industry’s first high-resolution inline e-beam review (EBR) system, increasing the speed at which manufacturers of OLED and UHD LCD screens can achieve optimum yields and bring new display concepts to market.

Applied is the semiconductor industry leader in EBR with more than 70 percent market share in 2015. The company has combined its leading-edge SEM capabilities used in semiconductor device review with a large-scale display vacuum platform, resulting in an inline EBR technology that is the fastest, most effective method to discover and address the root causes of killer defects in advanced mobile and TV displays.

Applied’s EBR system has received orders from 6 of the top 10 largest display manufacturers in the world and demand is increasing as manufacturers look to quickly and cost effectively optimize their yields and bring new types of displays to market faster.

“Our new EBR system is the latest in a strong pipeline of display products that enables customers to solve critical OLED and LCD manufacturing challenges,” said Ali Salehpour, senior vice president and general manager, Display and Adjacent Markets and Applied Global Services, Applied Materials. “Applied’s unique ability to combine semiconductor yield techniques and panel-level SEM technology expands our addressable market and avoids costly yield excursions for our customers. Emerging applications such as augmented and virtual reality and smart vehicles require better displays with new form factors. These applications are driving demand for solutions like our EBR tool that give customers significant time-to-market advantages.”

“As a worldwide leader in display, Tianma values the strong relationship with Applied Materials to help us develop new technologies required to produce the high-quality, high-performance mobile displays that consumers have come to expect,” said Dr. Jun Ma, vice president, Tianma Micro-electronics Co., Ltd. “Applied’s EBR system will enable us to reduce the start-up time at our Wuhan fab and accelerate our ability to bring more advanced display technologies to market. In addition to EBR, we look forward to working with Applied to introduce other semiconductor yield techniques to mobile display manufacturing.”

Advanced display technologies require an increasing number of process steps resulting in more and smaller contaminates, and new types of defects. Current inline automated optical defect inspection tools for displays are not as effective as SEM analysis in distinguishing killer from non-killer defects, or in determining systematic root causes of defects. Prior to the introduction of Applied’s EBR system, conducting SEM analysis on displays required breaking the glass substrate into pieces and examining each piece separately under a microscope. This is not only costly and time consuming but also makes it nearly impossible to determine the location of the defect on the full panel. Applied solves these limitations by providing inline SEM review at the industry’s highest resolution and throughput without requiring the panel to be broken.

Applied Materials, Inc. (Nasdaq:AMAT) is a leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world.

Applied Materials’ display e-beam review (EBR) system

Applied Materials’ display e-beam review (EBR) system

Solid State Technology announced today that its premier semiconductor manufacturing conference and networking event, The ConFab, will be held at the iconic Hotel del Coronado in San Diego on May 14-17, 2017. A 30% increase in attendance in 2016 with a similar uplift expected in 2017, makes the venue an ideal meeting location as The ConFab continues to expand.

    

For more than 12 years, The ConFab, an invitation-only executive conference, has been the destination for key industry influencers and decision-makers to connect and collaborate on critical issues.

“The semiconductor industry is maturing, yet opportunities abound,” said Pete Singer, Editor-in-Chief of Solid State Technology and Conference Chair of The ConFab. “The Internet of Things (IoT) is exploding, which will result in a demand for “things” such as sensors and actuators, as well as cloud computing. 5G is also coming and will be the key technology for access to the cloud.”

The ConFab is the best place to seek a deeper understanding on these and other important issues, offering a unique blend of market insights, technology forecasts and strategic assessments of the challenges and opportunities facing semiconductor manufacturers. “In changing times, it’s critical for people to get together in a relaxed setting, learn what’s new, connect with old friends, make new acquaintances and find new business opportunities,” Singer added.

Dave Mount

David Mount

Solid State Technology is also pleased to announce the addition of David J. Mount to The ConFab team as marketing and business development manager. Mount has a rich history in the semiconductor manufacturing equipment business and will be instrumental in guiding continued growth, and expanding into new high growth areas.

Mainstream semiconductor technology will remain the central focus of The ConFab, and the conference will be expanded with additional speakers, panelists, and VIP attendees that will participate from other fast growing and emerging areas. These include biomedical, automotive, IoT, MEMS, LEDs, displays, thin film batteries, photonics and advanced packaging. From both the device maker and the equipment supplier perspective, The ConFab 2017 is a must-attend networking conference for business leaders.

The ConFab conference program is guided by a stellar Advisory Board, with high level representatives from GLOBALFOUNDRIES, Texas Instruments, TSMC, Cisco, Samsung, Intel, Lam Research, KLA-Tencor, ASE, NVIDIA, the Fab Owners Association and elsewhere.

Details on the invitation-only conference are at: www.theconfab.com. For sponsorship inquiries, contact Kerry Hoffman at [email protected]. For details on attending as a guest or qualifying as a VIP, contact Sally Bixby at [email protected].

NuMat Technologies, a pioneer in the design and integration of atomically engineered materials into gas delivery, separation and purification systems, and The Linde Group, a gases and engineering company, have announced a collaborative partnership focused on the development of next generation separation and storage technologies that critically depend on material performance. The first of its kind partnership will pursue commercial applications that leverage NuMat’s innovations in Metal-Organic Frameworks (“MOFs”), an emerging class of ultra-high surface area materials which can be programmed to selectively interact with targeted gases and chemicals.

“We are excited to partner with Linde, a global leader in the gas industry, to develop cutting-edge solutions for the most demanding customer requirements,” commented NuMat CEO Ben Hernandez. “We see enormous potential to pair our respective material and system technologies to unlock cost-advantaged production economics, packaging innovations and improved environmental outcomes across the full gas life-cycle.”

The companies have formed joint teams to work on multiple projects on an on-going basis, including opportunities which address both near-term market needs and those which could be transformative.

“As a leading global technology company, sustained research and development is vital to Linde’s long-term business success and the success of our customers. In order to ensure we have availability to state-of-the-art technologies it is important that we work with partners who are leading in their field, such as NuMat. With this agreement we welcome NuMat into our global research network and look forward to collaborating to deliver MOF based technology solutions that provide value to our customers,” says Carl Jackson, Head of Electronics Technology and Innovation, The Linde Group.

Toshiba America Electronic Components, Inc. (TAEC) has expanded its family of 24nm single-level cell (SLC) NAND flash memory solutions. The new 16 gigabit (Gb) BENAND is housed in an industry-standard 48-pin TSOP package, and offers a combination of high read/write performance, effective write endurance (using 8-bit BCH error correction code), and extended temperature operation. This makes it suitable for a wide variety of commercial and industrial applications.

The new addition rounds out Toshiba’s broad SLC product lineup, allowing designers to take advantage of the price/performance of advanced 24nm NAND flash SLC technology at densities from 1Gb to 128Gb. Based on a 4x4Gb die, 16Gb BENAND operates from a power supply of 2.7V to 3.3V with a temperature range of -40°C to 85°C. Many industrial applications have a long life expectancy. Toshiba designed BENAND with this in mind. With the ability to replace older generations of discrete SLC NAND, BENAND extends the product life of everything from telecom applications and LCD TVs to robots and printers – while also potentially reducing BOM costs.

According to Brian Kumagai, director of business development for TAEC, “SLC NAND is still very much an integral part of the overall NAND market, and leading-edge 24nm devices play a key role in enabling replacement of the older NAND devices that are still being used today.”

Toshiba’s 24nm BENAND requires no ECC from the host controller. This enables it to be used with host controllers that do not have 8-bit ECC capability.  Many legacy designs still use older processors that do not have 8-bit ECC capability, making BENAND a viable option for companies looking to design in a cutting-edge NAND solution with existing hardware. To ensure easy migration, BENAND’s features such as page/block size, spare area size, commands, interface and package remain the same as legacy 4xnm SLC NAND.

Toshiba’s continuing commitment to supporting 24nm SLC NAND flash provides industrial designers with the confidence of knowing that they have chosen the correct technology for their applications requiring production longevity. This support eliminates concerns about redesigning to a newer generation.

Intel Corporation today announced the appointment of Robert “Bob” H. Swan as executive vice president and chief financial officer (CFO), effective Oct. 10, 2016. Swan will report to Intel CEO Brian Krzanich and oversee Intel’s global finance and IT organizations, as well as the Corporate Strategy Office. He replaces Stacy Smith, who, as previously announced, is taking a broader role within Intel leading manufacturing, sales and operations. Smith served nine years as Intel’s CFO.

“I’m thrilled to join Intel, a company where incredible innovation is supported by strong financial management,” Swan said.

“Bob brings a wealth of leadership and financial experience to Intel. His financial acumen and strategic insight will be welcome additions to our leadership team as Intel’s transformation continues,” Krzanich said.

Swan, 56, joins Intel from growth equity firm General Atlantic where he served as an operating partner working closely with the firm’s global portfolio companies on growth objectives. Prior to General Atlantic, he served nine years as the CFO of eBay Inc. Before that, he was CFO at Electronic Data Systems Corp and at TRW Inc. He also served as CFO, COO and CEO of Webvan Group Inc. Prior to that, Bob served in a number of senior finance roles at General Electric.

By Ted Shafer, Business Manager, Mature Product Sales, ASML

Ted Shafer of ASML reports on the highlights from the ≤200mm manufacturing session during SEMICON West, organized by the SEMI Secondary Equipment and Applications Special Interest Group. Your next opportunity to catch up on latest trends on ≤200mm manufacturing trends and its impact on the secondary equipment and applications market is SEMICON Europa 2016 and the Secondary Equipment Tech Arena session. 

Wednesday July 13th at SEMICON West a seminar and panel discussion were held to discuss the longevity and growth of the 200mm equipment market, and responses from IDMs, OEMs and 3rd parties to the challenges this growth presents.

Tim Tobin of Entrepix was the first speaker.  Entrepix is a premier 3rd party refurbisher of CMP and other process equipment.  Tim was the first to remark on a phenomenon that the other speakers and panelists also noted: a huge portion of the die in the devices we use daily do not require state of the art 300mm manufacturing.  For example, 60% – 80% of the chips in your smartphone or tablet are manufactured on 200mm – or smaller – wafers.  These wafers are created using mature equipment, which is frequently purchased from the secondary market, often from refurbishers such as Entrepix.

SEMI’s Christian Dieseldorff next provided a great overview of 200mm market trends, titled “200mm Fab: Trends, Status, and Forecast”.  Driven by the growth of IoT (Internet of Things), new 200mm fabs are being built and additional capacity is being added at existing fabs.  Key take-away is that after peaking in 2006, then declining for several years, 200mm wafer starts per month are now forecasted to exceed 2006’s level of 5.4M by 2019.  The question on everyone’s mind is, once that level is exceeded, where will the tools come from to manufacture those wafers?

200mm-image1

Pierric Gueguen of Yole spoke of the increased adoption of exotic substrates like GaN, Sapphire and Silicon Carbide.  These substrates provide many performance advantages, such as lower power consumption, faster switching speed, and high temperature resistance.  Yet the substrates cannot scale to 12”, and sometimes not to 8”.  So the increased adoption of these substrates is driving additional demand for 150mm/200mm tools.

As a counter-point to the 200mm discussions, Karen Erz of Texas Instruments gave a very well-received presentation on TI’s pivot to 300mm for analog, which has traditionally been manufactured on 200mm wafers.  A key to TI’s success is to embrace without fear buying opportunities for used equipment when they present themselves.  TI does not compete at the leading edge – their minimum feature size is 130nm – and thus mature, pre-owned, cost-effective equipment is always their first choice.  In fact, surplus 300mm is often more available, and less expensive, than comparable 200mm tools.  TI capitalized on the bankruptcies of the 300mm fabs of Qimonda Dresden, Qimonda Richmond, and PROMOS, also surplus tools at Powerchip, to scoop up large batches of inexpensive 300mm tools.  They continue to buy surplus 300mm tools when they come on the market, even in advance of actually requiring the tools.  As a result, 92% of RFAB’s analog production is done with pre-owned 300mm equipment.

Emerald Greig of Surplus Global, in addition to organizing the seminar, also provided a well-researched presentation on surplus equipment trends, titled “The Indispensable Secondary Market”.  Surplus Global is one of the largest surplus equipment traders, and they track the used equipment market very closely.  Emerald discussed how the supply of tools per year is trending dramatically downwards.  In 2009 they saw 6,000 tools come on the market, and that run-rate has steadily decreased to the point where by last year it was under 1,000/year.  This year we are at just 600.

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AMAT’s John Cummings provided the first OEM perspective on the 200mm market.  John showed how over 70% of the chips in the segments of automotive, wearables and mobile are produced on <=200mm wafers.  These segments are growing – for example a BMW i3 contains an astonishing 545 total die, and 484 of them are manufactured on <=200mm wafers.   AMAT reports that there are not enough used 200mm tools on the market to support the demand, and thus AMAT supplies their customers with new 200mm tools to augment the upgrades and refurbs they perform on pre-owned tools.  AMAT also provides new functionality for their mature 200mm products, increasing their usefulness and extending their lifetime.

Finally there was the OEM panel discussion, consisting of Kevin Chasey of TEL, David Sachse of LAM, Hans Peters from Ebara, and Ted Shafer of ASML.  Emerald Greig of Surplus Global provided some initial questions and solicited additional ones from the audience.   The OEMs echoed one common theme of the presentations, that 200mm demand is robust, and core tools are increasingly hard to find.  TEL additionally noted that China is a growing player in this market, and that OEMs must now support their 200mm product lines much longer than initially planned.  LAM said that 200mm core supply is so tight that the prices are rising above even comparable 300mm cores.  In response, LAM augments the supply of used tools by creating new 200mm tools.  Ebara added that the core tools coming on the market are often undesirable first-generation tools or tools in very bad condition.  On the other hand, this creates a role for the OEM, who has the expertise to make these tools production-worthy.  ASML noted that many of their larger 200mm customers are considering a migration from the PAS 5500 platform to ASML’s TWINSCAN platform for 200mm production.  Although developed for 300mm, and in general larger and more expensive than the 200mm 5500 series, ASML has spent the last 15 years making TWINSCANs increasingly productive and reliable, to the point where they often offer superior cost of ownership at 200mm than ASML’s 5500 platform.  Furthermore, customers buying TWINSCAN for 200mm production have an easy upgrade to 300mm when/if their plans call for it.

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In summary, the seminar showcased a robust exchange of ideas, where the presenters and panelists examined the resurgent 200mm market, and described many solutions to the common challenge of limited and expensive 200mm cores.

Attend SEMICON Europa and the Secondary Equipment & Applications session on October 26 to find out the latest trends and discuss in what areas OEMs, IDMs and secondary  market operators can cooperate more closely to improve sustainable access to legacy manufacturing equipment.

Find out more about SEMI’s Secondary Equipment and Applications Special Interest Group and the Secondary Equipment Legacy Management Program that is currently under development. For more information and to get involved, contact [email protected] (Ms. Rania Georgoutsakou, Director Public Policy for Europe, SEMI).