Yearly Archives: 2016

Synopsys, Inc. (Nasdaq:  SNPS) today announced the successful tapeout of multiple customer test chips with DesignWare Logic Libraries and Embedded Memories for TSMC’s 7-nanometer (nm) FinFET process. The tapeouts mark a significant milestone in Synopsys’ and TSMC’s collaboration on the development of DesignWare Logic Library, Embedded Memory and Interface IP for TSMC’s 7-nm FinFET process. The collaboration extends Synopsys’ long history of successful IP development on TSMC advanced FinFET processes for high-performance, low-power system-on-chips (SoCs).

“TSMC and Synopsys have a long track record of successful collaboration on advanced FinFET processes, providing our mutual customers with a low-risk path to integrating a broad portfolio of high-quality, silicon-proven IP into their SoCs,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Achieving multiple customer tapeouts of Synopsys DesignWare IP on TSMC’s 7-nm process demonstrates the benefits of our collaboration and gives designers confidence that they will meet their power, performance and area targets while accelerating their time to market.”

“As a leading provider of physical IP, Synopsys continues to provide early access to IP in the most advanced process technologies, helping designers incorporate necessary functionality and accelerate their design schedules,” said John Koeter, vice president of marketing for IP and prototyping at Synopsys. “With multiple customer tapeouts of DesignWare IP for TSMC’s 7-nm process, Synopsys enables designers to reduce integration risk and differentiate their products with this latest technology.”

Applied Materials, Inc. and the Institute of Microelectronics (IME), a research institute under the Agency for Science, Technology and Research (A*STAR), today announced a five-year extension of their research collaboration at the Centre of Excellence in Advanced Packaging in Singapore. The organizations will expand the scope of their R&D collaboration to focus on advancing Fan-Out Wafer-Level Packaging (FOWLP), a key technology inflection expected to help make chips and end-user devices smaller, faster and more power efficient.

With an anticipated additional S$188 million of combined investment, the Centre will expand to a second location at Fusionopolis 2, in addition to the existing facility at Singapore’s Science Park II. The two facilities combined will span an area of approximately 1,700 square meters and be staffed by a team of close to 100 researchers, scientists and engineers. The Centre was built to develop new capabilities in advanced packaging through a full line of Applied Materials’ Wafer-Level Packaging (WLP) processing equipment, and has successfully delivered advancements in semiconductor hardware, process and device structures.

“Our collaboration with A*STAR over the past five years has been instrumental in establishing Applied Materials’ presence in Singapore and building up our R&D capabilities,” said Russell Tham, Regional President, Applied Materials South East Asia. “With the entire R&D value stream from ideation to product development being carried out locally via this joint lab, the expansion will further Applied Materials’ development of new technologies and products for global markets, while remaining a key contributor to Singapore’s innovation economy.”

Dr. Raj. Thampuran, Managing Director, A*STAR, said, “Our relationship with Applied Materials transcends a new milestone with the extension of our collaboration in R&D into new areas. The progress we have made from our initial collaboration is a testament to the successful partnership A*STAR has with Applied Materials. As we look towards the future, we remain committed to advancing innovations in the semiconductor industry and being at the forefront of leading edge ideas in this rapidly evolving technological landscape.”

The Internet of Things (IoT) and Big Data are driving forces in today’s market of interconnected and multi-functional electronic devices. FOWLP is considered a key technology platform for system scaling, enabling multiple chips to be integrated in a small form factor on a single package. With FOWLP capable of providing significant benefits for the mobile and wireless markets, increased investment in the sector could help propel Singapore’s standing as a global hub for semiconductor R&D. Through a successful alliance with its private sector partners across the value chain, A*STAR has contributed to Singapore’s vibrant research, innovation and enterprise ecosystem. In 2014, A*STAR and 10 other industry partners launched four Advanced Semiconductor Joint Labs to provide an integrated platform for complex microchip manufacturing R&D. These global partnerships together with the Applied Materials – A*STAR joint R&D Centre will continue to strengthen Singapore’s capabilities in semiconductor R&D and contribute to the creation of high-value jobs and competitiveness of the industry.

The Singapore Centre conducts WLP research across Applied Materials for its global customers. The Centre undertakes complex multi-disciplinary research to develop new innovations in advanced packaging including bump, TSV, 2.5D interposers and now FOWLP. Through its work at the Centre, Applied Materials has developed technology that has been successfully implemented in several of its semiconductor equipment products. In addition, the extension of the collaboration highlights the important role a successful public-private partnership plays in creating value and building up differentiated competencies for Singapore.

“Applied Materials’ leading expertise in materials engineering drives the development of highly differentiated products and solutions that make new technologies possible,” said Dr. Prabu Raja, Group Vice President and General Manager of the Patterning and Packaging Group, Applied Materials. “We are excited to expand our collaboration with A*STAR and leverage our complementary strengths to solve challenges in advanced packaging and build new capabilities for future innovations.”

A*STAR takes a long-term vision towards strategic investments in industry-ready R&D that contribute to Singapore’s economic growth. It is home to one of the premier advanced packaging and wafer-level packaging research facilities in Asia. IME’s leading research capabilities in advanced chip packaging are focused on meeting the challenging requirements in complex and sophisticated chip packaging, in order to develop slimmer devices with greater system capabilities such as ultra-low power consumption, increased memory and bandwidth, and diverse functionality.

Dr. Tan Yong Tsong, Executive Director, IME, said, “Our long standing collaboration with Applied Materials demonstrates the value of public-private partnership under open innovation, and underscores the readiness and competitiveness of IME’s research capabilities for the industry. Through this joint lab, we will continue to push the envelope through our differentiated R&D competencies to deliver breakthrough technologies.”

By Zvi Or-Bach, President & CEO, MonolithIC 3D Inc.

As we have predicted two and a half years back, the industry is bifurcating, and just a few products pursue scaling to 7nm while the majority of designs stay on 28nm or older nodes.

Our March 2014 blog Moore’s Law has stopped at 28nm has recently been re-confirmed. At the time we wrote: “From this point on we will still be able to double the amount of transistors in a single device but not at lower cost. And, for most applications, the cost will actually go up.” This reconfirmation can be found in the following IBS cost analysis table slide, presented at the early Sept FD-SOI event in Shanghai.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

Gate costs continue to rise each generation for FinFETs, IBS predicts.

As reported by EE Times – Chip Process War Heats Up, and quoting Handel Jones of IBS “28nm node is likely to be the biggest process of all through 2025”.

IBS prediction was seconded by “Samsung executive showed a foil saying it believes 28nm will have the lowest cost per transistor of any node.” The following chart was presented by Samsung at the recent SEMICON West (2016).

Zvi 2

And even Intel has given up on its “every two years” but still claims it can keep reducing transistor cost. Yet Intel’s underwhelming successes as a foundry suggests otherwise. We have discussed it in a blog titled Intel — The Litmus Test, and it was essentially repeated by SemiWiki’s Apple will NEVER use Intel Custom Foundry!

This discussion seems academic now, as the actual engineering costs of devices in advanced nodes have shown themselves to be too expensive for much of the industry. Consequently, and as predicted, the industry is bifurcating, with a few products pursuing scaling to 7nm while the majority of designs use 28nm or older nodes.

The following chart derived from TSMC quarterly earnings reports was published last week by Ed Sperling in the blog Stepping Back From Scaling:

Zvi 3

Yes, the 50-year march of Moore’s Law has ended, and the industry is now facing a new reality.

This is good news for innovation, as a diversity of choices helps support new ideas and new technologies such as 3D NAND, FDSOI, MEMS and others. These technologies will enable new markets and products such as the emerging market of IoT.

A good opportunity to learn more about these new scaling technologies is the IEEE S3S ’16, to be held in the Hyatt Regency San Francisco Airport, October 10th thru 13th, 2016. It starts with 3D and FDSOI tutorials, the emerging technologies for the IC future. CEA Leti is scheduled to give an update on their CoolCube program, Qualcomm will present some of their work on monolithic 3D, and three leading researchers from an imec, MIT, and Korea university collaboration will present their work on advanced monolithic 3D integration technologies. Many other authors will discuss their work on monolithic 3DIC and its ecosystem, in addition to tracks focused on SOI, sub-VT and dedicated sessions on IoT.

Thorlabs has expanded its piezoelectric line to include new types of piezoelectric actuators, low‐voltage piezoelectric chips, and discrete stacks with through holes, enabling a higher level of flexibility when integrating the actuators into other devices. These chips are ideal for laser tuning, micro‐ dispensing, and life‐science applications.

The chips can be manufactured with or without pre‐attached wires, with holes ranging from Ø2.0 mm to Ø6.0 mm, cross sections ranging from 5.0 mm × 5.0 mm to 10.0 mm × 10.0 mm, and thicknesses under 5.0 mm. Stacks are available in lengths from 5 mm to 100 mm, providing free stroke displacements up to 100 μm. Their in‐house manufacturing facility can also be deployed to provide custom dimensions, voltage ranges, and coatings upon request.

The piezoelectric chips are driven under a maximum voltage of 150 V, providing maximum free stroke displacements from 1.8 μm to 3.0 μm with sub‐millisecond response time. Through a precision grinding process, the accuracy of the design height is ensured to better than ±5 μm. The high accuracy makes it significantly easier to design devices around our piezoelectric chips, as it allows the users to have a loose tolerance when choosing their other components, and helps guarantee a better parallelism when employing multiple chips between two substrates.

“Reliability and durability of multilayer piezoelectric actuators are becoming increasingly important as the piezo application fields expand,” commented Cary Zhang, Piezo Product Line Manager. “Thorlabs’ multilayer piezo actuators are based on modified PZT‐5H ceramics, which are sintered at low temperatures (<1000 °C) to possess improved characteristics such as low electrical capacity, large displacement, and high stiffness.”

Besides the newly released piezo chips/stacks, Thorlabs manufactures a wide range of high quality piezo actuators, including chips, stacks, tubes, shear piezo and bimorphs. Modular, screw, and replaceable‐tip piezo actuators, including single axis, multi‐axis, closed‐loop and open‐loop actuators are also available.

Thorlabs, a vertically integrated photonics products manufacturer, was founded in 1989 to serve the laser and electro‐optics research market.

2016_09-16_Piezo-1

As part of an initiative to optimize service to the growing global polymer processing market, Nordson Corporation (Nasdaq:NDSN) today announced it plans to combine its existing screw and barrel operations in Youngstown, Ohio; New Castle, Pennsylvania; and Pulaski, Virginia into a single expanded manufacturing center of excellence in Austintown, Ohio.

“We expect this initiative to drive efficiencies in manufacturing processes, decrease lead times, enhance customer service, improve competitiveness and accelerate growth,” said John Keane, Nordson Corporate Senior Vice President. “Our plan is for Austintown to join similar regional hubs for our screw and barrel products in Thailand and Germany. No other single supplier will be able to provide the polymer industry with such localized service on a global scale.”

Nordson expects the transition to an existing facility in Austintown to be completed over the next 18 months, subject to the conclusion of customary negotiations with local and state officials. The transition will occur in stages to minimize any potential impact to current customers. Planned investments in the facility over the period include upgraded bi-metallic processing and machining systems to improve product quality, precision and throughout.

The majority of positions in the existing Youngstown, New Castle and Pulaski facilities will transfer to the Austintown facility. Total employment in Austintown is expected to be approximately 260. Nordson will be actively recruiting for any positions not being filled by current employees.

GLOBALFOUNDRIES today announced plans to deliver a new leading-edge 7nm FinFET semiconductor technology that will offer the ultimate in performance for the next era of computing applications. This technology provides more processing power for data centers, networking, premium mobile processors, and deep learning applications.

GLOBALFOUNDRIES’ new 7nm FinFET technology is expected to deliver more than twice the logic density and a 30 percent performance boost compared to today’s 16/14nm foundry FinFET offerings. The platform is based on an industry-standard FinFET transistor architecture and optical lithography, with EUV compatibility at key levels. This approach will accelerate the production ramp through significant re-use of tools and processes from the company’s 14nm FinFET technology, which is currently in volume production at its Fab 8 campus in Saratoga County, N.Y. GLOBALFOUNDRIES plans to make an additional mutli-billion dollar investment in Fab 8 to enable development and production for 7nm FinFET.

“The industry is converging on 7nm FinFET as the next long-lived node, which represents a unique opportunity for GLOBALFOUNDRIES to compete at the leading edge,” said GLOBALFOUNDRIES CEO Sanjay Jha. “We are well positioned to deliver a differentiated 7nm FinFET technology by tapping our years of experience manufacturing high-performance chips, the talent and know-how of our former IBM Microelectronics colleagues and the world-class R&D pipeline from our research alliance. No other foundry can match this legacy of manufacturing high-performance chips.”

“GLOBALFOUNDRIES made a bold decision to jump directly from 14nm to 7nm–a decision that is now supported by several leading semiconductor companies as they see only marginal performance and power benefits for the high cost of the 10nm process node,” said Jim McGregor, founder and principal analyst at TIRIAS Research. “Much like the 28nm and 16/14nm process nodes, 7nm appears to be the next major process node that will be widely leveraged by the entire semiconductor industry for at least the next decade.”

“Leading-edge technologies like GLOBALFOUNDRIES 7nm FinFET are an important part of how we deliver our long-term roadmap of computing and graphics products that are capable of powering the next generation of computing experiences,” said Dr. Lisa Su, president and CEO, AMD. “We look forward to continuing our close collaboration with GLOBALFOUNDRIES as they extend the solid execution and technology foundation they are building at 14nm to deploy high-performance, low-power 7nm technology in the coming years.”

“IBM is committed to pushing the limits of semiconductor technology as part of its aggressive long term research agenda,” said Arvind Krishna, senior vice president and director of IBM Research. “IBM Research continues to collaborate with GLOBALFOUNDRIES in developing new ideas, new skills and new technologies that will help accelerate our joint research in 7nm technology and beyond.”

GLOBALFOUNDRIES will deliver a comprehensive and competitive IP library, co-optimized with process development. To enable customers to accelerate adoption of 7nm FinFET technology, GLOBALFOUNDRIES has expanded its strategic partnership with INVECAS beyond 14LPP and FDX™ processes to now include foundry IP development for 7nm process technologies. This will provide customers with a strong foundation to build early designs that meet their performance, power and area requirements.

“INVECAS specializes in providing unrivaled IP solutions, ASIC and design services to GLOBALFOUNDRIES’ customers that span the wide-range of GLOBALFOUNDRIES’ leading edge FinFET and FDX processes,” said Dasaradha Gude, CEO, INVECAS. “Our strategic partnership with GLOBALFOUNDRIES combined with our tailor-made foundry IP model allows us to develop a 7nm FinFET process foundation IP that meets the challenging performance requirements of 7nm customers’ leading-edge applications.”

Building on the success of its 14LPP technology platform, GLOBALFOUNDRIES’ 7nm FinFET technology is positioned to enable next-generation computing applications that demand ultra-high performance, from high-end mobile SoCs to processors for cloud servers and networking infrastructure. The company’s high-performance offerings are complemented by its 22FDXTM and 12FDXTMtechnologies, which have been developed to meet the ultra-low-power requirements of the next generation of intelligent connected devices, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

GLOBALFOUNDRIES’ 7nm FinFET technology will be supported by a full platform of foundation and complex intellectual property (IP), including an application-specific integrated circuit (ASIC) offering. Test chips with IP from lead customers have already started running in Fab 8. The technology is expected to be ready for customer product design starts in the second half of 2017, with ramp to risk production in early 2018.

Cascade Microtech, a FormFactor company (NASDAQ:FORM), and a supplier of solutions that enable precision measurements of discrete devices and integrated circuits (ICs) at the wafer level, today announced the launch of the Estrada-EM system – the industry’s first integrated measurement solution (IMS) to offer high-performance electromigration (EM) wafer-level reliability (WLR) testing of copper lines and vias in an oxygen-depleted environment. The Estrada-EM system delivers important WLR benefits to a test industry which has traditionally been limited to package-level reliability (PLR) test methods alone for EM. By overcoming several long-standing technical hurdles, this new product enables semiconductor reliability test programs to produce faster test results and assure high data integrity.

Electromigration is widely recognized to be a critical reliability issue for state of the art semiconductor technologies, and expected to become an even greater challenge at the 10 nm node and beyond. Proper evaluation of EM reliability necessitates the testing of many samples, under many conditions. By eliminating the packaging steps required for PLR, which delay the start of every test, the Estrada-EM WLR solution provides the same electromigration reliability answers days, or even weeks, sooner. In addition to eliminating the packaging delays, the system further boosts test program throughput with an extended-range thermal system for test acceleration, high-parallel test capacity, and unique features for unattended test which include automated in-situ probe alignment and autonomous dynamic thermal test profiles. The result is quicker technology evaluation cycles and faster fab process qualifications, for reduced time to market and increased profitability.

Today’s environment of shrinking reliability margins and increasingly sophisticated IC design rules demands not only fast results, but also highly accurate test data. WLR testing with the Estrada-EM IMS entirely avoids the risk of latent water and ESD damage which can occur in the test structures during the wafer sawing, structure bonding, and package handling which occurs for PLR. To further enhance data integrity, the system’s source measurement units (SMUs) incorporate unique performance capabilities such as programmable compliance to ensure the legitimacy of breakdown mechanisms and continuous monitoring to capture maximum data detail. This meticulous care leads to the industry’s most well-informed interconnect reliability models and technology decisions.

These benefits are extended to the full reliability test market by Cascade Microtech’s revolutionary PureZone oxygen-purging chamber system, which carefully wraps the wafer in an inert gas environment to prevent oxidation of copper pads and structures. This innovation enables, for the first time, direct testing of all wafers with copper interconnect technologies, including those without pad capping or passivation and even partially-processed wafers.

“Today’s technology race puts pressure on reliability labs for quicker answers, and the complexity of new nodes means a variety of materials and structures need to be evaluated in a compressed timeframe,” said Mike Slessor, President and CEO, FormFactor, Inc. “We’re happy to be able to help our customers accelerate design and qualification cycles by using EM WLR to complement EM PLR as they respond to emerging reliability challenges.”

GLOBALFOUNDRIES today introduced a scalable, embedded magnetoresistive non-volatile memory technology (eMRAM) on its 22FDX platform, providing system designers with access to 1,000x faster write speeds and 1,000x more endurance than today’s non-volatile memory (NVM) offerings. 22FDX eMRAM also features the ability to retain data through 260°C solder reflow, industrial temperature operation, while maintaining an industry-leading eMRAM bitcell size.

GLOBALFOUNDRIES’ eMRAM will be offered initially on its 22FDX platform, which leverages the industry’s first 22nm fully-depleted silicon-on-insulator (FD-SOI) technology. This versatile eMRAM technology is designed for both code storage (flash) and working memory (SRAM) to enable ultra-efficient memory sub-systems that can be power cycled without any energy or performance penalty. The power efficiency of FDX and eMRAM, coupled with the available RF connectivity IP, makes 22FDX an ideal platform for battery-powered IoT products and automotive MCUs.

“Customers are looking for a high-performance non-volatile memory solution that expands their product capabilities,” said Gregg Bartlett, senior vice president CMOS Platforms Business Unit, GLOBALFOUNDRIES. “Our introduction of 22FDX eMRAM enables system designers with new capabilities, allowing them to build greater functionality into their MCUs and SoCs, while enhancing performance and power efficiency.”

The emergence of autonomous vehicles is rapidly driving the need for increased on-chip memory capacities required for real-time vision processing, high-precision, continuous 3D mapping data and next-generation automotive MCUs that update over-the-air. GLOBALFOUNDRIES’ eMRAM uniquely addresses these advanced driving assistance system (ADAS) requirements by combining greater memory density than SRAM, with the fast write, very high endurance, and non-volatility that only magnetoresistive memory can provide.

“Emerging non-volatile memories are moving from the lab to the fab,” said Thomas Coughlin, President of Coughlin Associates. “GLOBALFOUNDRIES’ 22FDX eMRAM will offer a major advancement in SoC capabilities, by leveraging the key performance attributes of embedded MRAM. Designers of battery powered IoT devices, automotive MCUs and SoCs and SSD storage controllers will certainly want to take advantage of this versatile embedded NVM technology.”

The introduction of GLOBALFOUNDRIES’ 22FDX eMRAM is a result of the company’s multi-year partnership with MRAM pioneer, Everspin Technologies. The partnership has already delivered the world’s highest density ST-MRAM in August, 2016  – Everspin’s 256Mb DDR3 perpendicular magnetic tunnel junction (pMTJ) product, which is now successfully sampling and is being readied for mass production at GLOBALFOUNDRIES.

GLOBALFOUNDRIES’ 22FDX eMRAM is currently in development and is expected to be available for customer prototyping in 2017, with volume production in 2018. GLOBALFOUNDRIES’ eMRAM technology is scalable beyond 22nm and is expected to be available on both FinFET and future FDX platforms.

SEMI, the global industry association representing more than 2,000 companies in the electronics manufacturing supply chain, announced that MEMS & Sensors Industry Group (MSIG) will become a SEMI Strategic Association Partner effective January 1, 2017.

Through this strategic partnership, SEMI and MSIG members will benefit from stronger consolidated representation in the MEMS and sensors segments. Members will access SEMI’s global platforms, including its SEMICON expositions and International Standards program, and MSIG’s events, including MEMS & Sensors Executive Congresses, MEMS & Sensors Technical Congress and MSIG Conference Asia. MSIG also brings member-focused initiatives, such as the TSensors initiative, as well as industry Standards and community-building to the new partnership.

“SEMI members are increasingly engaged with MEMS and sensors manufacturing,” said Denny McGuirk, president and CEO of SEMI. “The convergence of IC technology, flexible hybrid electronics (FHE), and MEMS and sensors for consumer electronics and IoT applications makes this partnership a clear win for the combined membership. The synergies between our associations will result in increased member value, a unified voice for the MEMS and sensors sector, and a strong platform for global industry collaboration. Ultimately, it will accelerate our joint strategic objectives at a global level and provide greater opportunities to advance the growth and prosperity of members.”

“Our partnership with SEMI reflects our commitment to our members, who have supported us since MSIG’s inception in 2001,” notes Karen Lightman, executive director, MEMS & Sensors Industry Group. “MSIG members will benefit from this relationship with increased access to global resources and service offerings, the expertise of a complementary industry and fast-track entry to worldwide programs. Ultimately, MSIG members will gain broader reach as they pursue new business opportunities. We are delighted to have such a capable and accomplished partner and look forward to our strategic association partnership with SEMI.”

Actions Semiconductor Co., Ltd. (NASDAQ:  ACTS), one of China’s leading fabless semiconductor companies that provides comprehensive portable multimedia and mobile internet system-on-a-chip (SoC) solutions for portable consumer electronics, today announced that it has entered into a definitive merger agreement on September 12, 2016 pursuant to which the Company will be acquired by a consortium of investors, including Supernova Investment Ltd. and other certain shareholders of the Company: Surrey Glory Investments Inc., Tongtong Investment Holding Co., Ltd., Perfectech Int’l Ltd, Allpremier Investment Limited, Octovest International Holding Co., Ltd., Ventus Corporation, Middlesex Holdings Corporation Inc, Rich Dragon Consultants Limited, Nutronics Technology Corporation, Uniglobe Securities Limited, New Essential Holdings Limited, Embona Holdings (Malaysia) Limited, Suffolk Dragon Ventures Ltd and Top Best Development Limited.

Pursuant to the terms of the Merger Agreement, at the effective time of the merger, a wholly owned subsidiary of Parent will merge with and into the Company, with the Company continuing as the surviving company, and each of the Company’s ordinary shares, par value US$0.00001 per share, issued and outstanding immediately prior to the effective time of the merger (the “Shares”) will be cancelled and cease to exist in exchange for the right to receive US$0.366 in cash without interest, and each American Depositary Share (“ADS”) of the Company, every ADS representing six Shares, will be cancelled in exchange for the right to receive US$2.20 in cash without interest, except for (a) certain Shares owned by the Rollover Shareholders, each of which will continue to exist and become one ordinary share, par value of $0.00001 each, of the Surviving Company, (b) Shares (including Shares represented by ADSs) owned by the Company or any of its subsidiaries, (c) Shares reserved (but not yet issued and allocated) by the Company for issuance and allotment upon exercise of any share incentive awards issued under the Company’s employee share incentive plans, and (d) Shares held by shareholders who have validly exercised and not effectively withdrawn or lost their rights to dissent from the merger pursuant to Section 238 of the Companies Law of the Cayman Islands (the “Dissenting Shares”), which will be cancelled and cease to exist in exchange for the right to receive the payment of fair value of the Dissenting Shares in accordance with Section 238 of the Companies Law of the Cayman Islands.

The merger consideration represents a premium of 49.7% to the closing price of the Company’s ADSs on May 18, 2016, the last trading day prior to the Company’s announcement of its receipt of a “going-private” proposal, and a premium of 40.6% to the volume weighted average closing price of the Company’s ADSs during the 30 trading days prior to its receipt of a “going-private” proposal. The Buyer Consortium intends to fund the merger through available cash of the Company and its subsidiaries.

The Company’s board of directors (the “Board”), acting upon the unanimous recommendation of a committee of independent and disinterested directors established by the Board (the “Special Committee”), approved the Merger Agreement and the merger and resolved to recommend that the Company’s shareholders vote to authorize and approve the Merger Agreement and the merger. The Special Committee negotiated the terms of the Merger Agreement with the assistance of its independent financial and legal advisors.

The merger, which is currently expected to close during the last quarter of 2016, is subject to customary closing conditions including the approval of the Merger Agreement by an affirmative vote of holders of Shares representing at least two-thirds of the voting power of the Shares present and voting in person or by proxy at a meeting of the Company’s shareholders which will be convened to consider the approval of the merger agreement and the merger. Pursuant to a voting and support agreement entered among Parent and the other Rollover Shareholders, the Rollover Shareholders have agreed to vote all the Shares and ADSs beneficially owned by them in favor of the authorization and approval of the Merger Agreement and the merger. If completed, the merger will result in the Company becoming a privately-held company and its ADSs will no longer be listed on The NASDAQ Select Global Market.

The Company will prepare and file with the U.S. Securities and Exchange Commission (the “SEC”) a Schedule 13E-3 transaction statement, which will include a proxy statement of the Company. The Schedule 13E-3 will include a description of the Merger Agreement and contain other important information about the merger, the Company and the other participants in the merger.

In connection with the merger, Houlihan Lokey (China) Limited is serving as financial advisor to the Special Committee; Jones Day is serving as U.S. legal counsel to the Special Committee; Maples and Calder is serving as Cayman Islands legal counsel to the Special Committee. K&L Gates LLP is serving as U.S. legal counsel to the Buyer Consortium.