Yearly Archives: 2016

Thiophene-fused polycyclic aromatic hydrocarbons (PAHs) are known to be useful as organic semiconductors due to their high charge transport properties. Scientists at Nagoya University have developed a short route to form various thiophene-fused PAHs by simply heating mono-functionalized PAHs with sulfur. This new method is expected to contribute towards the efficient development of novel thiophene-based electronic materials.

Nagoya, Japan – Dr. Lingkui Meng, Dr. Yasutomo Segawa, Professor Kenichiro Itami of the JST-ERATO Itami Molecular Nanocarbon Project, Institute of Transformative Bio-Molecules (ITbM) of Nagoya University and Integrated Research Consortium on Chemical Sciences, and their colleagues have reported in the Journal of the American Chemical Society, on the development of a simple and effective method for the synthesis of thiophene-fused PAHs.

Thiophene-fused PAHs are organic molecules composed of multiple aromatic rings including thiophene. Thiophene is a five-membered aromatic ring containing four carbon atoms and a sulfur atom. Thiophene-fused PAHs are known to be one of the most common organic semiconductors and are used in various electronic materials, such as in transistors, organic thin-film solar cells, organic electro-luminescent diodes and electronic devices. More recently, they have found use in wearable devices due to their lightweight and flexibility.

Thienannulation (thiophene-annulation) reactions, a transformation that makes new thiophene rings via cyclization, leads to various thiophene-fused PAHs. Most conventional thienannulation methods require the introduction of two functional groups adjacent to each other to form two reactive sites on PAHs before the cyclization can take place. Thus, multiple steps are required for the preparation of the substrates. As a consequence, a more simple method to access thiophene-fused PAHs is desirable.

A team led by Yasutomo Segawa, a group leader of the JST-ERATO project, and Kenichiro Itami, the director of the JST-ERATO project and the center director of ITbM, has succeeded in developing a simple and effective method for the formation of various thiophene-fused PAHs. They have managed to start from PAHs that have only one functional group, which saves the effort of installing another functional group, and have performed the thienannulation reactions using elemental sulfur, a readily available low cost reagent. The reactions can be carried out on a multigram scale and can be conducted in a one-pot two-step reaction sequence starting from an unfunctionalized PAH. This new approach can also generate multiple thiophene moieties in a single reaction. Hence, this method has the advantage of offering a significant reduction in the number of required steps and in the reagent costs for thiophene-fused PAH synthesis compared to conventional methods.

The researchers have shown that upon heating and stirring the dimethylformamide solution of arylethynyl group-substituted PAHs and elemental sulfur in air, they were able to obtain the corresponding thiophene-fused PAHs. The arylethynyl group consists of an alkyne (a moiety with a carbon-carbon triple bond) bonded to an aromatic ring. The reaction proceeds via a carbon-hydrogen (C-H) bond cleavage at the position next to the arylethynyl group (called the ortho-position) on PAHs, in the presence of sulfur. As the ortho-C-H bond on the PAH can be cleaved under the reaction conditions, prior functionalization (installation of a functional group) becomes unnecessary.

Arylethynyl-substituted PAHs are readily accessible by the Sonogashira coupling, which is a cross-coupling reaction to form carbon-carbon bonds between an alkyne and a halogen-substituted aromatic compound. The synthesis of thiophene-fused PAHs can also be carried out in one-pot, in which PAHs are subjected to a Sonogashira coupling to form arylethynyl-substituted PAHs, followed by direct treatment of the alkyne with elemental sulfur to induce thienannulation.

“Actually, we coincidentally discovered this reaction when we were testing different chemical reactions to synthesize a new molecule for the Itami ERATO project,” says Yasutomo Segawa, one of the leaders of this study. “At first, most members including myself felt that the reaction may have already been reported because it is indeed a very simple reaction. Therefore, the most difficult part of this research was to clarify the novelty of this reaction. We put in a significant amount of effort to investigate previous reports, including textbooks from more than 50 years ago as well as various Internet sources, to make sure that our reaction conditions had not been disclosed before,” he continues.

The team succeeded in synthesizing more than 20 thiophene-fused PAHs. They also revealed that multiple formations of thiophene rings of PAHs substituted with multiple arylethynyl groups could be carried out all at once. Multiple thiophene-fused PAHs were generated from three-fold and five-fold thienannulations, which generated triple thia[5]helicene (containing three thiophenes) and pentathienocorannulene (containing five thiophenes), respectively. The pentathienocorannulene was an unprecedented molecule that was synthesized for the first time.

“I was extremely happy when I was able to obtain the propeller-shaped triple thia[5]helicene and hat-shaped pentathienocorannulene, because I have always been aiming to synthesize exciting new molecules since I joined Professor Itami’s group,” says Lingkui Meng, a postdoctoral researcher who mainly conducted the experiments. “We had some problems in purifying the compounds but we were delighted when we obtained the crystal structures of the thiophene compounds, which proved that the desired reactions had taken place.”

“The best part of this research for me is to discover that our C-H functionalization strategy on PAHs could be applied to synthesize structurally beautiful molecules with high functionalities,” says Segawa. “The successful synthesis of a known high-performance organic semiconductive molecule, (2,6-bis(4-n-octylphenyl)- dithieno[3,2-b:2?,3?-d]thiophene (the lower right of Figure 4), from a relatively cheap substrate opens doors to access useful thiophene compounds in a rapid and cost-effective manner.”

“We hope that ongoing advances in our method may lead to the development of new organic electronic devices, including semiconductor and luminescent materials,” say Segawa and Itami. “We are considering the possibilities to make this reaction applicable for making useful thiophene-fused PAHs, which would lead to the rapid discovery and optimization of key molecules that would advance the field of materials science.”

Qualcomm Incorporated (NASDAQ:  QCOM) today announced the opening of Qualcomm Communication Technologies (Shanghai) Co. Ltd., a semiconductor test facility in the Waigaoqiao (WGQ) free-trade zone in Shanghai, and its first foray into providing manufacturing services for semiconductors. By working with Amkor Technology, Inc., one of the world’s leading providers of contract semiconductor assembly and test services, the new company will combine Amkor’s extensive test services experience and cleanroom facilities with Qualcomm Technologies’ industry leadership in cutting-edge product engineering and development.

The new manufacturing facility demonstrates Qualcomm Technologies’ commitment to continue to invest and help develop semiconductor expertise in China, and is indicative of growth in semiconductor market leadership in the country. Through the ownership and operation of a semiconductor test center, Qualcomm Technologies will enhance its focus on customer service, continue to develop its expertise in operational excellence, and increase its business presence in China.

“The test facility is part of our continued mission to streamline supply chain operations and improve operational efficiency,” said Roawen Chen, senior vice president, QCT global operations, Qualcomm Technologies, Inc.

“Qualcomm Technologies continually strives to improve our manufacturing footprint in China and the formation of Qualcomm Communication Technologies in Shanghai is another example of this dedication,” said Frank Meng, chairman, Qualcomm China.

“We are excited to work with Qualcomm Technologies in their new test operation in China,” said Steve Kelley, Amkor’s president and chief executive officer. “Amkor offers the most advanced outsourced assembly and test technologies in China, and this expanded relationship is a natural extension of the long history of close collaboration between our two companies.”

The Shanghai-based facility is set to begin operations on October 18, 2016.

An overview of liquid-to-liquid cooling systems and their operating principles

BY MARKO NIEMANN, Regional Sales Director, Laird Engineered Thermal Systems, Cologne, Germany

Cooling and temperature control systems are used throughout semiconductor fabrication facilities. In fabrication facilities both large and small, hundreds to thousands of cooling systems are installed and operate continuously. The processes employed are usually setup as copy-exact, which means the process systems are developed and transferred from the OEM of the process tool. These crtitical production tools used in a semiconductor fabrication facilities are required to be reliable and easy to service to deliver minimum downtime. The same is required of the cooling systems that support them. Usually the cooling systems employed have a water- cooled evaporator instead of an air-cooled evaporator. A liquid-liquid unit is quieter than a liquid to air unit because a fan is not required. Even more important, the heat can be rejected by available general facility cooling water and the heat is not rejected into the air temperature conditioned environment. These cooling systems can be placed near the tool, hidden in a false floor or on the lower level in a sub-floor. Cooling systems are built to meet SEMI S2 or F47 standards. OEM customers vary in their demand according to their unique requirements, but compliance is mandatory and sometimes OEM customers ask to get certifications for SEMI S2 or F47, which includes for example seismic “protections.” In these fabrication facilities a variety of liquid cooling systems are used including: compressor and thermoelectric based recirculating chillers.

Cooling systems

Liquid cooling systems are required to:

  • Protect the tool process against chemical reaction by avoiding an unknown Wetted-Parts-Material-Mix
  • Achieve a stable temperature, independent from facility water temperatures that can change
  • Achieve a temperature below or above the facility water temperature
  • Solve different temperature or fluid requirements at one tool with a multi-loop liquid cooling system

In semiconductor fabrication facilities, the required temperature control range varies from -80°C to +150°C. For the majority of applications, only one stable temperature set point is required. In the final chip test environment however, temperatures are required to vary in order to stress the chip. Here different temperature set points need to be reached with a single thermal management system. Due to the high-precision processes, tool manufacturers demand a very stable temperature environment. Typical of these requirements are +/-0.1K stability (e.g. for etching) to ±0.001K (e.g. for lithography) while cooling capacities can be up to several kilowatts.

In semiconductor fabrication facilities, custom multi- stage compressor based chillers are used to support cooling for very low temperature requirements. Most standard chillers utilized need some form of modification to meet semiconductor process facility requirements and may even require a water-cooled condenser. Some of the installation base also uses thermoelectric (19” rack) cooling systems, i.e. for etch applications, instead of compressor-based systems.

The cooling capacity demands and the range over which the system operates varies from a couple of hundred Watts (thermoelectric chiller and compressor based systems) to hundreds of Kilowatts (liquid-to-liquid cooling systems). The majority of the installed base uses liquid-to-liquid cooling systems that operate close to ambient and are based on a fluid-to-fluid heat-exchange principle.

The cooling systems utilize facility water to prevent heat dissipation of the cooling unit from warming the cleanroom and destabilizing the process tool’s thermal management system. These liquid-to-liquid systems keep the air quality level high by avoiding dust up introduced from the airflow of an air-to-air thermal management system. This consideration is independent of the location of the thermal management system. Due to the cyclic nature of the market, product requirements change and time to market is crucial. The cooling system solution developed is usually a custom product with a unique approach and design specific to the OEM.

Technical requirements

Cooling systems are often placed in the sub-fab, which means they are located one or two floors below the tool they are connected to. For cooling systems that use water as coolant, the height between the tool and the cooling system cannot exceed 10 meters, otherwise the height difference can cause the water to boil as the pressure is lower than the vapor pressure of water.
If the cooling system is placed at a lower level, the coolant circuit can function as a closed loop to the atmosphere. In this case, the cooling unit needs to incorporate a closed pressurized reservoir (7 PSI pressure cap) to minimize over flow conditions. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap (FIGURE 1).

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

FIGURE 1. The reservoir can be designed as a flow through reservoir or as a standpipe reservoir with a pressurized cap.

A standpipe reservoir introduces additional fluid to the liquid circuit as required, whereas a flow-through reservoir continuously exchange fluid. It is important to know that the pump simply needs to overcome the height and pressure difference one-time during start-up in a closed loop system, as the supply and return lines will equilibrate given that they have the same length and diameter.

Material compatibility

In the semiconductor process environment, copper and brass are materials with limited compatibility due to their susceptibility to galvanic corrosion. Wetted parts, which come in direct contact with the medium (liquid), are typically made of stainless steel. These parts range from the complete plumbing circuit of the cooling unit to the process loop. Stainless steel is usually used in the process loop due its resistance to galvanic corrosion or because a special fluid is used that is not compatible with PVC, copper, and brass etc. When stainless steel is required, the heat exchanger, valves and the pumps will require special consideration. Occasionally, stainless steel may require additional passivation or a limited subset of stainless steel materials may be used.

If copper or brass is used to accomodate cost considerations, the material needs to be insulated to minimize the thermal impact on the system from outside thermal sources. Special particle free insulation may be required in this instance.

Special fluids used in the semiconductor environment include: di-electric fluids (Galden, 3M Novec), which are non-conductive. Special hoses and sealings need to be used for these fluids and special attention to handling is also required. These coolants run in a closed loop as the fluid vapor pressure is relatively low compared to water.

The use of de-ionized water is common. Copper or brass can be run up to 3 MOhm-cm resistivity if the set point temperature does not exceed 30°C for extended periods of time. However to ensure long lifetimes and for higher resistivity demands, the cooling system should be equipped with a nickel brazed or complete passivated stainless steel evaporator/heat-exchanger. The pumps should be stainless steel and all component parts in contact with the fluid should be made of passivated stainless steel to prevent corrosion. This is referred to as high-purity plumbing. In addition, a DI cartridge can be equipped with an indicator light or regulated through the cooling system and the DI level will be constantly measured and monitored keeping to a preset resistivity. The DI cartridge filters the ions out of the fluid and needs to be replaced to ensure its effectiveness.

Valves

If the unit is placed below the fabrication floor, an anti- siphoning package can be used to avoid backflow of the fluid and prevent overflowing the unit in event the pump stops. The anti-siphoning package consists of a one-way check valve in the supply line and normally open solenoid valves triggered by the unit in the return line. The solenoid valve would close in case the pump stops and the one-way check valve allows for the flow in only one direction. Instead of a one-way check valve, another solenoid valve can be used, though this depends on the flow rate and size (FIGURE 2).

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

FIGURE 2. Instead of a one-way check valve, another solenoid valve can be used.

For a process facility, constant monitoring and control of the facility process water is required and modulating solenoid valves from Siemens or Bellimo need to be used. The valve diameter and actuating motor have to be sized correctly to achieve stable temperatures and trigger the correct switching cycles. Assuring this means the inclusion of a long- lasting actuator and facility water flowing through an acceptable pressure drop from the facility water supply and return. Sometimes three-way mixing valves are used. This allows for continuous flow into the facility water loop and adds cooling for the heat exchanger of the thermal management system when required. The constant flow back to the facility water loop avoids a water hammer in cases where it would close and reopen when cooling is required. Flow requirements can go be as high as hundreds of liters per minute.

Space consideration

Cleanroom costs can be up to $60,000 /m2, therefore the chiller footprint is important and can have a costly impact. Semiconductor cooling systems should be stackable (stacked high) and preferable narrow to maximize space and minimize their impact on costs. Therefore the design of a cooling system’s footprint needs to be closely examined. The system should also be located where it is easy to access from two sides. Routine maintenance on cooling systems is required to exchange components such as pumps, motors, valves and fans to maximize system uptime.

SEMI requirements

For a completed tool, OEMs require a SEMI S2 certification and sometimes a Semi F-47 certification in areas with high earthquake probability. As the SEMI S2 certification requires a high amount of documentation, subsystems like a cooling unit will finally be integrated into the tool. Most of the time it is sufficient to meet the intent of SEMI S2 and the OEM will do a full certification of the final tool with all sincorporated subsystems in their NRTL laboratory. Below are some items to consider when designing a cooling unit to meet SEMI S2 and F-47 standards.

SEMI S2:

  • Drip tray must be large enough to hold 110% of the volume of the largest container in the cooling product
  • EMO button and/or EMO connection
  • Seismic brackets, seismic tie downs for standalone units
  • A specific power connection setup depending on the power consumption

F-47:

  • Continue to run during a power drop for a given time and fixed reduction of power

These requirements vary from customer to customer, but to some extent the certification is known to the manufacturer of the system.

If the unit is not placed below the fabrication facility flooring, the cooling system will instead be placed in the cleanroom or a grey room. Again, requirements here can vary drastically from customer to customer. If the cooling system, sub-assembly or any component is required to be in the cleanroom, then the entire assembly including each component must be as clean as possible. This requires the entire manufacturing process to have a high level of attention to cleanliness. Debris, dust, burrs or chips occurring at every process step need to be examined and removed ideally after every fabrication step. The industry is quite sensitive to this.

After the final assembly, the cooling unit needs to go through a manual check with UV-light and wipe down for final cleaning with gloves. The unit is then double bagged and each bag needs to be labeled appropriately. There are suppliers who specialize in cleaning, to semicon- ductor standards, and this can be subcontracted. Since it contributes to the cost and lead-time, the level of detail used requires scrutiny.

Service

Selling a cooling unit into the semiconductor market requires long-term servicing agreements in the contract. If a product is qualified in one facility other facilities can take over the setup as a copy exact requirement and use the existing cooling solution. For this after-market service and support, full understanding of the end users demands is critical. Service and support needs to responsive. In the event a tool unexpectedly goes down, immediate support is required or the OEM can lose millions of dollars in revenue.

Once the tool is installed service needs to be done on-site on the same day of failure, as large cooling systems cannot be replaced easily or shipped back to manufacturer for repair. OEMs have moved away from purchasing redundant cooling systems as their processes are getting leaner and expenses are reviewed more closely. This puts the contractual emphasis on service and a global service infrastructure.

Ideally the manufacturer is aware of the service demands and support strategy of their customers. Systems today are designed to minimize the downtime and make use of hot swappable parts, such as pumps on rails or modular exchange of complete assemblies, including electrical control boxes.

Conclusion

A semiconductor fabrication facility’s unique environment makes designing and building a liquid based cooling system one of the most challenging environments. Careful consideration is required not only for component selection, but also on the overall liquid cooling system unit and its integration with a semiconductor tool. Challenges designers face include the type of heat transfer mechanism utilized on the control and heat dissipation sides, material compat- ibility, valve control, cleanliness, space optimization, semi compliance and serviceability. These are all areas in need of attention to detail to properly ensure an optimized total cost of ownership.

“Promising” and “remarkable” are two words U.S. Department of Energy’s Ames Laboratory scientist Javier Vela uses to describe recent research results on organolead mixed-halide perovskites.

Perovskites are optically active, semiconducting compounds that are known to display intriguing electronic, light-emitting and chemical properties. Over the last few years, lead-halide perovskites have become one of the most promising semiconductors for solar cells due to their low cost, easier processability and high power conversion efficiencies. Photovoltaics made of these materials now reach power conversion efficiencies of more than 20 percent.

Vela’s research has focused on mixed-halide perovskites. Halides are simple and abundant, negatively charged compounds, such as iodide, bromide and chloride. Mixed-halide perovskites are of interest over single-halide perovskites for a variety of reasons. Mixed-halide perovskites appear to benefit from enhanced thermal and moisture stability, which makes them degrade less quickly than single-halide perovskites, Vela said. He added they can be fine-tuned to absorb sunlight at specific wavelengths, which makes them useful for tandem solar cells and many other applications, including light emitting diodes (LEDs).Using these compounds, scientists can control the color and efficiency of such energy conversion devices.

Speculating that these enhancements had something to do with the internal structure of mixed-halide perovskites, Vela, who is also an associate professor of chemistry at Iowa State University (ISU), worked with scientists with expertise in solid-state nuclear magnetic resonance (NMR) at both Ames Laboratory and ISU. NMR is an analytical chemistry technique that provides scientists with physical, chemical, structural and electronic information about complex samples.

“Our basic question was what it is about these materials in terms of their chemistry, composition, and structure that can affect their behavior,” said Vela.

Scientists found that depending on how the material is made there can be significant nonstoichiometric impurities or “dopants” permeating the material, which could significantly affect the material’s chemistry, moisture stability and transport properties.

The answers came via the combination of the use of optical absorption spectroscopy, powder X-ray diffraction and for the first time, the advanced probing capabilities of lead solid-state NMR.

“We were only able to see these dopants, along with other semicrystalline impurities, through the use of lead solid-state NMR,” said Vela.

Another major discovery scientists made was that solid state synthesis is far superior to solution-phase synthesis in making mixed-halide perovskites. According to Vela, the advanced spectroscopy and materials capabilities of Ames Laboratory and ISU were critical in understanding how various synthetic procedures affect the true composition, speciation, stability and optoelectronic properties of these materials.

“We found you can make clean mixed halide perovskites without semi-crystalline impurities if you make them in the absence of a solvent,” Vela said.

According to Vela, the significance of their findings is multifold and they are only beginning to grasp the implications of those findings.

“One obvious implication is that our understanding of the amazing opto-electronic properties of these semiconductors was incomplete,” said Vela. “We’re dealing with a compound that is not inherently as simple as people thought.”

The research is further discussed in a paper, “Persistent Dopants and Phase Segregation in Organolead Mixed-Halide Perovskites,” authored by Vela, Bryan A. Rosales, Long Men, Sarah D. Cady, Michael P. Hanrahan, and Aaron J. Rossini; and published online in Chemistry Materials. The work was supported by DOE’s Office of Science.

Lomonosov MSU physicists found a way to “force” silicon nanoparticles to glow in response to radiation strongly enough to replace expensive semiconductors used in display business. According to Maxim Shcherbakov, researcher at the Department of Quantum Electronics of the Moscow State University and one of the authors of the study, the developed method considerably enhances the efficiency of nanoparticle photoluminescence.

The key term in the problem is photoluminescence — the process, when materials irradiated by visible or ultraviolet radiation start to respond with their own light, but in a different spectral range. In the study, the material glows red.

In some of the modern displays, semiconductor nanoparticles, or the so-called quantum dots, are used. In quantum dots, electrons behave completely unlike those in the bulk semiconductor, and it has long been known that quantum dots possess excellent luminescent properties. Today, for the purposes of quantum-dot based displays various semiconductors are used, i.e. CdSe, etc. These materials are toxic and expensive, and, therefore, researchers have long been scrutinizing the far cheaper and much more studied silicon. It is also suitable for such use in all respects except one — silicon nanoparticles vaguely respond to radiation, which is not appealing for optoelectronic industry.

Scientists all over the world were seeking to solve this problem since the beginning of the 1990’s, but until now no significant success has been achieved in this direction. The breakthrough idea about how to “tame” silicon originated in Sweden, at the Royal Institute of Technology, Kista. A post-doctoral researcher Sergey Dyakov (a graduate of the MSU Faculty of Physics and the first author of the paper) suggested placing an array of silicon nanoparticles in a matrix with a non-homogeneous dielectric medium and cover it with golden nanostripes.

‘The heterogeneity of the environment, as has been previously shown in other experiments, allows to increase the photoluminescence of silicon by several orders of magnitude due to the so-called quantum confinement,’ says Maxim Shcherbakov. ‘However, the efficiency of the light interaction with nanocrystals still remains insufficient. It has been proposed to enhance the efficiency by using plasmons (quasiparticle appearing from fluctuations of the electron gas in metals — ed). Plasmon lattice formed by golden nanostripes allow to “hold” light on the nanoscale, and allow a more effective interaction with nanoparticles located nearby, bringing its luminescence to an increase.’

The MSU experiments with samples of “gold-plated” matrix with silicon nanoparticles made in Sweden brilliantly confirmed the theoretical predictions – the UV irradiated silicon for the first time shone bright enough to be used it in practice.

The first author of the paper Sergey Dyakov will present the findings on The 10th International Congress on Advanced Electromagnetic Materials in Microwaves and Optics (September 17-22, Crete). The work was also published in the Physical Review B (“Optical properties of silicon nanocrystals covered by periodic array of gold nanowires”).

Synopsys, Inc. (Nasdaq: SNPS) and GLOBALFOUNDRIES today announced that Synopsys has joined the foundry’s FDXcelerator Partner Program, an ecosystem designed to facilitate 22FDX system-on-chip (SoC) designs. This program enables designers to deploy Synopsys’ comprehensive RTL-to-GSDII solution with superior power and performance metrics for FDX-based designs. The collaboration accelerates the development of innovative products in applications spanning systems for intelligent clients, 5G connectivity, augmented and virtual reality and automotive.

Through the FDXcelerator Partner Program, Synopsys and GLOBALFOUNDRIES offer easy access to a complete 22FDX Reference Flow based on the Synopsys Galaxy Design Platform. This includes validated 22FDX “plug & play” support for tools, including Design Compiler, IC Compiler II, IC Validator, PrimeTime, StarRC, Custom Compiler, HSPICE and CustomSim solutions. The collaboration enables Synopsys’ tools to enhance support for differentiating GLOBALFOUNDRIES FD-SOI design features, including support for the adaptive body bias that unlocks FDX SoC performance and ultra-low-power operation, while lowering barriers of migration from bulk nodes. This allows engineers to create optimized designs, while minimizing development costs.

“Synopsys’ close collaboration with GLOBALFOUNDRIES provides designers access to a trusted EDA solution with advanced technical capabilities to address the requirements for developing differentiated FD-SOI-based designs,” said Bijan Kiani, vice president of product marketing for Synopsys’ Design Group. “We are helping designers adopt GLOBALFOUNDRIES’ innovative FDX offering by delivering comprehensive tools and methodologies to take advantage of the power, performance and cost advantages of the FDX technologies.”

“We are thrilled that Synopsys is an initial FDXcelerator partner,” said Alain Mutricy, senior vice president of Product Management at GLOBALFOUNDRIES. “Through this collaboration, our mutual customers can now take full advantage of the FDX value proposition by leveraging the validated Synopsys-based reference flow. The FDX-enabled Galaxy Design Platform will offer seamless support of body bias and other critical FDX performance management capabilities. The program will also enable access to Synopsys FDX EDA experts available for proactive training and support of mutual 22FDX design customers.”

With the recent announcement of the company’s next-generation 12FDX technology, the FDXcelerator Partner Program builds upon GLOBALFOUNDRIES’ industry-first FD-SOI roadmap, a lower-cost migration path for designers desiring advanced node design. By participating in FDXcelerator and continuing to invest in expanding the feature set of its tools to further support FDX customers, Synopsys is well positioned to participate in the adoption and growth of the FDX market. Moreover, the FDXcelerator Partner Program broadens the qualification and quality assurance collaboration between the companies, including tighter interlock around quality testing and methodology.

Additional Synopsys tools and features will be enhanced for FDX, and more information will be shared with the FDX design community in the months to come. Customers and partners interested in learning more about FDXcelerator can visit www.globalfoundries.com/fdxcelerator

GLOBALFOUNDRIES today unveiled a new 12nm FD-SOI semiconductor technology, extending its leadership position by offering the industry’s first multi-node FD-SOI roadmap. Building on the success of its 22FDX offering, the company’s next-generation 12FDX platform is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles.

As the world becomes more and more integrated through billions of connected devices, many emerging applications demand a new approach to semiconductor innovation. The chips that make these applications possible are evolving into mini-systems, with increased integration of intelligent components including wireless connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption. GLOBALFOUNDRIES’ new 12FDX technology is specifically architected to deliver these unprecedented levels of system integration, design flexibility, and power scaling.

12FDX sets a new standard for system integration, providing an optimized platform for combining radio frequency (RF), analog, embedded memory, and advanced logic onto a single chip. The technology also provides the industry’s widest range of dynamic voltage scaling and unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate energy efficiency.

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” said GLOBALFOUNDRIES CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

GLOBALFOUNDRIES’ new 12FDX technology is built on a 12nm fully-depleted silicon-on-insulator (FD-SOI) platform, enabling the performance of 10nm FinFET with better power consumption and lower cost than 16nm FinFET. The platform offers a full node of scaling benefit, delivering a 15 percent performance boost over today’s FinFET technologies and as much as 50 percent lower power consumption.

“Chip manufacturing is no longer one-shrink-fits-all. While FinFET is the technology of choice for the highest-performance products, the industry roadmap is less clear for many cost-sensitive mobile and IoT products, which require the lowest possible power while still delivering adequate clock speeds,” said Linley Gwennap, founder and principal analyst of the Linley Group. “GLOBALFOUNDRIES’ 22FDX and 12FDX technologies are well positioned to fill this gap by offering an alternative migration path for advanced node designs, particularly those seeking to reduce power without increasing die cost. Today, GLOBALFOUNDRIES is the only purveyor of FD-SOI at 22nm and below, giving it a clear differentiation.”

“When 22FDX first came out from GLOBALFOUNDRIES, I saw some game-changing features. The real-time tradeoffs in power and performance could not be ignored by those needing to differentiate their designs,” said G. Dan Hutcheson, chairman and CEO of VLSI Research. “Now with its new 12FDX offering, GLOBALFOUNDRIES is showing a clear commitment to delivering a roadmap for this technology — especially for IoT and Automotive, which are the most disruptive forces in the market today. GLOBALFOUNDRIES’ FD-SOI technologies will be a critical enabler of this disruption.”

“FD-SOI technology can provide real-time trade-offs in power, performance and cost for those needing to differentiate their designs,” said Handel Jones, founder and CEO, IBS, Inc. “GLOBALFOUNDRIES’ new 12FDX offering delivers the industry’s first FD-SOI roadmap that brings the lowest cost migration path for advanced node design, enabling tomorrow’s connected systems for Intelligent Clients, 5G, AR/VR, Automotive markets.”

GLOBALFOUNDRIES Fab 1 in Dresden, Germany is currently putting the conditions in place to enable the site’s 12FDX development activities and subsequent manufacturing. Customer product tape-outs are expected to begin in the first half of 2019.

“We are excited about the GLOBALFOUNDRIES 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang, Director General, Academician of Chinese Academy of Sciences, Shanghai Institute of Microsystem and Information Technology. “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”

“NXP’s next generation of i.MX multimedia applications processors are leveraging the benefits of FD-SOI to achieve both leadership in power efficiency and scaling performance-on-demand for automotive, industrial and consumer applications,” said Ron Martino, vice president, i.MX applications processor product line at NXP Semiconductors. “GLOBALFOUNDRIES’ 12FDX technology is a great addition to the industry because it provides a next generation node for FD-SOI that will further extend planar device capability to deliver lower risk, wider dynamic range, and compelling cost-performance for smart, connected and secure systems of tomorrow.”

“As one of the first movers of design for FD-SOI, VeriSilicon leverages its Silicon Platform as a Service (SiPaaS) together with experience in delivering best-in-class IPs and design services for SoCs,” said Wayne Dai, president and CEO of VeriSilicon. “The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments. We look forward to extending our collaboration with GLOBALFOUNDRIES on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market.”

“12FDX development will deliver another breakthrough in power, performance, and intelligent scaling as 12nm is best for double patterning and delivers best system performance and power at the lowest process complexity,” said Marie Semeria, CEO of Leti, an institute of CEA Tech. “We are pleased to see the results of the collaboration between the Leti teams and GLOBALFOUNDRIES in the U.S. and Germany extending the roadmap for FD-SOI technology, which will become the best platform for full system on chip integration of connected devices.”

“We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering. Now this new 12FDX offering will further expand FD-SOI market adoption,” said Paul Boudre, Soitec CEO. “At Soitec, we are fully prepared to support GLOBALFOUNDRIES with high volumes, high quality FD-SOI substrates from 22nm to 12nm. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”

By Christian G. Dieseldorff, Industry Research & Statistics Group at SEMI (September 6, 2016)

SEMI’s Industry Research and Statistics group has published its August update of the World Fab Forecast report. The report has served the industry for 24 years, observing and analyzing spending, capacity, and technology changes for all front-end facilities worldwide, from high-volume to R&D fabs.  SEMI’s latest data show increasing equipment spending, reaching 4.1 percent YOY in 2016 and 10.6 percent in 2017. Figure 1 (below) shows a forecast of  -2 percent decline from 2H2015 to 1H2016 and an 18 percent increase from 1H2016 to. 2H2016.

Figure 1: Fab Equipment Spending by Quarter

Figure 1: Fab Equipment Spending by Quarter

The largest growth drivers for the industry are mobile devices (including devices using SSDs), automotive, and soon anticipated to be IoT, with these applications, in many cases, requiring 3D NAND and Logic 10nm/7nm.

The SEMI report indicates that the two industry segments leading to the biggest increase in 2H16 are Foundry (29 percent) and Memory (21 percent).  Growth in Memory is driven by a significant increase in 3D NAND spending in 2016. Comparing 2016 to 2017, Foundry growth remains quite steady, with a 14 percent increase in 2016 and 13 percent in 2017.

Companies like Samsung, Micron, Flash Alliance, Intel, and SK Hynix drive Memory growth with 3D NAND to an astounding 152 percent increase in 2016 and 29 percent in 2017. However, utilization of all this equipment is still low in 2016 but is expected to increase in 2017.

Looking at other product segments, DRAM equipment spending is expected to decline by 31 percent in 2016 and then recover slightly with 2 percent growth in 2017. Power devices also show strong growth with 25 percent in 2016 and 16 percent in 2017. The Analog segment will slump by -15 percent in 2016 but increase by 20 percent in 2017. Similarly, MPU will drop -20 percent in 2016 and then is expected to increase by 48 percent in 2017.

Comparing spending by region in 2016, SE Asia shows the largest growth, with 157 percent in 2016, driven mainly by 3D NAND (see Figure 2).

China, in third place for overall spending, shows 64 percent growth for 2016 primarily due to 3D NAND by non-Chinese companies, closely followed by Foundry companies. Although the largest spenders in China currently are overseas device companies, China-based chipmakers are starting to pick up investment activity.

Figure 2: Fab Equipment Spending by Region

Figure 2: Fab Equipment Spending by Region

By contrast, the largest growth rate in 2017 is in Europe/Mideast with about 60 percent which is mainly due to ramping of 10nm facilities. Korea is in second place for total spending, mainly driven by Samsung’s investment in DRAM and Flash. Japan in third place driven by Flash Alliance (3D NAND).

The World Fab Forecast report provides more detailed information by company and fab for construction spending, equipment spending and capacities by region and product type.  Since the last publication in May 2016, the SEMI research team has made over 330 changes to 300 facilities/lines. This includes 27 new records and 18 records closed.

For information about semiconductor manufacturing for the remainder of 2016 and in 2017, and for details about capex for construction projects, fab equipping, technology levels, and products, order the SEMI World Fab Forecast Report. The report, in Excel format, tracks spending and capacities for over 1,100 facilities including over 82 future facilities, across industry segments from Analog, Power, Logic, MPU, Memory, and Foundry to MEMS and LEDs facilities.  Using a bottoms-up approach methodology, the SEMI Fab Forecast provides high-level summaries and graphs, and in-depth analyses of capital expenditures, capacities, technology and products by fab.

The SEMI Worldwide Semiconductor Equipment Market Subscription (WWSEMS) data tracks only new equipment for fabs and test and assembly and packaging houses.  The SEMI World Fab Forecast and its related Fab Database reports track any equipment needed to ramp fabs, upgrade technology nodes, and expand or change wafer size, including new equipment, used equipment, or in-house equipment. Also check out the Opto/LED Fab Forecast. Learn more about the SEMI fab databases at: www.semi.org/MarketInfo/FabDatabase and www.youtube.com/user/SEMImktstats

The global high-tech engineering and construction company M+W Group has presented current and future trends, as well as state of the art solutions, for an integrated approach to waste reduction in order to improve the sustainability of semiconductor fabs. The presentation was held at the High-Tech Facility International Forum 2016 in Taipei on 8th September in conjunction with the Semicon Taiwan trade show.

Having successfully contributed to the forum’s widely recognized meetings over the past two years M+W Group was also invited to this year’s expert meeting on high- tech facilities. There, M+W Group leading experts presented the company’s solutions for an Integrated Waste Reduction Program for Semiconductor Facilities. It was emphasized that minimization of waste produced in semiconductor wafer fabs and other high-tech facilities begins during the buildings’ design and must focus on both the construction as well as the operational phases.

Drawing on its globally recognized experience, M+W Group outlined how sustainability in a semiconductor wafer fab can best be evaluated, monitored and optimized through the application of a holistic Life Cycle Assessment (LCA) tool that provides systematic evaluation of all environmental aspects of a wafer fab during their construction, operational lifetime and decommissioning.
Herbert Blaschitz, CEO of M+W Group’s Global Business Unit Advanced Technology Facilities, said “There is an ever-increasing interest in the industry to implement fully sustainable semiconductor wafer fab solutions. We at M+W Group have broad and successful experience in this field and are proud to be at the forefront of this development.”

About the High-Tech Facility International Forum: As part of SEMICON Taiwan the High- Tech Facility International Forum 2016 focuses on cost-efficient waste reduction for sustainable facilities. The forum builds a platform for major players in the high tech facility community to discuss latest trends, challenges and outstanding solutions for the Taiwanese high-tech industry. Other members besides M+W Group include TSMC, UMC (wafer fab foundries for Integrated Circuits (IC)), Macronix, Inotera (IC memory manufacturers), AUO, Chimei Innolux (flat panel display manufacturers), ASE, SPIL (IC assembly), Epistar (LED Manufacturer) and Motech (PV module manufacturer).

GLOBALFOUNDRIES today announced a new partner program, called FDXcelerator, an ecosystem designed to facilitate 22FDX system-on-chip (SoC) design and reduce time-to-market for its customers.

With the recent announcement of the company’s next-generation 12FDX™ technology, the FDXcelerator Partner Program builds upon GLOBALFOUNDRIES industry-first FD-SOI roadmap, a lower cost migration path for customers desiring advanced node design.

Together with GLOBALFOUNDRIES and FDXcelerator Partner solutions, customers will be able to build innovative 22FDX SoC solutions as well as ease migration to FD-SOI from bulk nodes such as 40nm and 28nm. Initial FDXcelerator Partners have committed a set of key offerings to the program, including:

  •  tools (EDA) that complement industry leading design flows by adding specific modules to easily leverage FDSOI body-bias differentiated features,
  •  a comprehensive library of design elements (IP), including foundation IP, interfaces and complex IP to enable foundry customers to start their designs from validated IP elements,
  • platforms (ASIC), which allow a customer to build a complete ASIC offering on 22FDX,
  • reference solutions (reference designs, system IP), whereby the Partner brings system level expertise in Emerging application areas, enabling customers to speed-up time to market,
  • resources (design consultation, services), whereby Partners have trained dedicated resources to support 22FDX technology, and;
  • product packaging and test (OSAT) solutions.

“22FDX is increasingly gaining momentum as the platform of choice to build differentiated, highly-integrated system solutions,” said Alain Mutricy, senior vice president of Product Management at GLOBALFOUNDRIES.  “Now is the time to step up industry collaboration to enable our customers to accelerate adoption of 22FDX. FDXcelerator will extend the reach of the FD-SOI ecosystem by creating a market place for truly innovative FDX-tailored solutions and services.”

The FDXcelerator Partner Program creates an open framework to allow selected Partners to integrate their products or services into a validated, plug and play catalog of design solutions. This level of integration allows customers to create high performance designs while minimizing development costs through access to a broad set of quality offerings, specific to 22FDX technology. The Partner ecosystem positions members and customers to take advantage of the broad adoption and accelerating growth of the FDX market.

FD-SOI technology has been gaining ground as designers leverage the process as an alternative to Fin-FET-based technologies for chips that require performance on demand and energy efficiency at the lowest solution cost. According to a recent Linley Group Microprocessor Report, FD-SOI Offers Alternative to FinFET, GLOBALFOUNDRIES’ FDX technologies provide an alternative path for applications that cannot accept the cost and complexity of FinFETs.

Initial partners of the FDXcelerator Partner Program are: Synopsys (EDA), Cadence (EDA), INVECAS (IP and Design Solutions), VeriSilicon (ASIC), CEA Leti (services), Dreamchip (reference solutions) and Encore Semiconductor (services). These companies have already initiated work to deliver advanced 22FDX SoC solutions and services. Additional FDXcelerator members will be announced in the following months.