Yearly Archives: 2016

Lam Research Corp. (Nasdaq: LRCX), an advanced manufacturer of semiconductor equipment, today announced that it is expanding its atomic layer etching (ALE) portfolio with the addition of ALE capability on its Flex dielectric etch systems. Enabled by Lam’s Advanced Mixed Mode Pulsing (AMMP) technology, the new ALE process has demonstrated the atomic-level control needed to address key challenges in scaling logic devices to 10nm and below. First in the industry to use plasma-enhanced ALE in production for dielectric films, the latest Flex system has been adopted as tool of record for high-volume manufacturing of logic devices.

“From transistor and contact creation to interconnect patterning, a new level of precision is needed by logic manufacturers to continue scaling beyond the 10nm technology node,” said Vahid Vahedi, group vice president, Etch Product Group. “For device-enabling applications like self-aligned contacts, where etch helps create critical structures, conventional technologies do not provide sufficient control for the stringent specifications now demanded. Our latest Flex product with dielectric ALE delivers atomic-scale control with proven productivity to meet customers’ key requirements.”

To continue logic device scaling, chipmakers are adopting new integration schemes such as those using self-aligned contacts (SACs) in order to address issues like RC delay. As a result, contact etch has become one of the most crucial processes, directly impacting both wafer yield and transistor performance. In order to define critical device structures with high fidelity, the etch process requires directional (anisotropic) capability with ultra-high selectivity, while also delivering the productivity needed for manufacturing.

For next-generation logic and foundry applications, Lam’s Flex dielectric etch systems offer the industry’s most advanced capacitively coupled plasma (CCP) reactor, featuring a unique, small-volume design to deliver repeatable results. The latest system uses proprietary AMMP technology to enable ALE of dielectric films such as silicon dioxide (SiO2). This capability results in a 2x improvement in selectivity over previous dielectric etch technologies while delivering atomic-level control.

SPTS Technologies, an Orbotech company and a supplier of advanced wafer-processing solutions for the global semiconductor and related industries, today announced its collaboration with Novati Technologies, a global nanotechnology development center, to establish Novati’s new plasma dicing line at their fab in Austin, Texas. Novati has selected SPTS’s Rapier-300S plasma dicing solution over competing options to provide next-generation plasma dicing capabilities and services for customers.

“Plasma dicing has many advantages over conventional singulation methods and offers designers and manufacturers greater flexibility with regards to die shape, size and position,” stated Kevin Crofton, President of SPTS Technologies and Corporate Vice President at Orbotech. “The Rapier-300S is the latest addition to our Mosaic™ plasma dicing platform which includes wafer handling solutions for 150mm, 200mm and 300mm wafers, both full thickness and taped to dicing frames. Novati selected the Rapier-300S to provide their customers with the latest dicing technology to complement their advanced semiconductor fabrication solutions and services.”

“Novati provides customers with technology building blocks, engineering expertise, professional program management and a broad complement of flexible processing equipment that enable the accelerated development of 200mm and 300mm production-worthy solutions,” stated John Behnke, President of Novati Technologies. “In order to remain at the forefront of novel process development, we must provide our foundry customers with the latest process solutions capable of manufacturing next generation devices.”

SPTS’s Mosaic plasma dicing system with the Rapier-300S overcomes many of the design limitations of conventional dicing methods, particularly for smaller, thinner, more fragile die, as well as offering the potential for significant increases in yield and throughput. By leveraging SPTS’s extensive expertise and experience in deep silicon etch which serves as the basis of Rapier-300S plasma dicing technology, customers are able to support the development of innovative More-than-Moore solutions.

To learn more about SPTS’s Rapier-300S and Mosaic plasma dicing platform and the benefits of Plasma Dicing for Next Generation Ultra Small and Ultra Thin Die, register now for a free webinar on Wed 14th Sept, 2016, with presentations from Amandine Pizzagalli, Analyst at Yole Developpment, and Richard Barnett from SPTS Technologies.

SEMI today presented its industry leadership award for sustainable manufacturing to Po Wen Yen, CEO of United Microelectronics Corporation (UMC). Yen received theSEMI Sustainable Manufacturing Leadership Award – Inspired by Akira Inoue, at the Leadership Gala Dinner at SEMICON Taiwan 2016, the largest annual electronics manufacturing industry event in Taiwan.

“Yen exemplifies outstanding leadership and commitment to sustainable manufacturing issues. He approaches environmental protection in a holistic way, thinking broadly and then setting up the infrastructure to institutionalize the change while staying involved each step of the way,” said Denny McGuirk, president and CEO of SEMI. “This SEMI award for significant sustainable manufacturing achievement recognizes his status among a distinguished group of electronics industry executives.”

As CEO of UMC, Yen drove UMC to become a global leader in sustainable semiconductor manufacturing, emphasizing to his staff, customers, and suppliers, that “sustainable development is not only UMC’s vision but is also our core philosophy.” Yen also created a corporate structure where all sustainability-related goals and activities are overseen by a committee that he chairs, and then he reports these developments directly to the UMC Board of Directors.  Yen’s commitment has led to significant positive impacts on sustainable manufacturing at UMC. Yen’s specific accomplishments noted by the SEMI Award committee include:

Environmental Protection

  • Global Warming –To reduce energy use at UMC, Yen created and chairs an Energy Saving Committee, which reduced electrical power usage by 29,469 Mwh in 2014, which is the equivalent of removing 15,353 tons of CO2 from the atmosphere, and reduced natural gas usage by 11,979 Mwh, the equivalent to reducing 2,159 tons of CO2 emissions from being released into the atmosphere.
  • Water Resources – UMC maximizes water efficiency and promotes the importance of water resources and conservation. Total water recovery and reuse reached more than 180 percent of water intake for the calendar year 2015.
  • Green Manufacturing – UMC innovated corporate programs to manage hazardous substances and reduce pollution and waste during semiconductor manufacturing. UMC has a robust Hazardous Substance Process Management (HSPM) system in place that is certified by the International Electro-Technical Commission Quality Assessment System.
  • Green Buildings – UMC’s Fab 12A in the Tainan Science Park obtained both Taiwan’s Gold Certification for Green Buildings and LEED Gold Certification.
  • Green Products –To better evaluate the environmental impacts of products, UMC collaborated with the Industrial Technology Research Institute (ITRI) to implement a Life Cycle Assessment for each fab, improving its management processes and reducing resource consumption.


Community Service

  • Social Welfare – UMC encourages a culture of community volunteering with many programs. One example, “Spreading the Seeds of Hope,” has assisted over 6,000 children from disadvantaged families.
  • UMC Fire Brigade – Still the only corporation in Taiwan’s electronics industry to have its own fire department, UMC established its high-tech fire brigade more than 20 years ago. The fire brigade consists of 106 members, including 13 full-time employees and 93 voluntary firefighters.

The Sustainable Manufacturing Leadership Awardis sponsored by SEMI. The award is named after the late Akira Inoue, past president of Tokyo Electron Limited and a strong advocate of sustainable manufacturing in the semiconductor industry. Inoue also served on the SEMI Board of Directors. The award recognizes individuals in industry who have made significant leadership contributions to reduce the environmental and social impacts of semiconductor manufacturing. Past Award recipients include: Mark Durcan (CEO, Micron), TY Chiu (CEO, SMIC), Ajit Manocha (CEO, GLOBALFOUNDRIES), and Morris Chang (CEO, TSMC).

Global growth in the number of “things” connected to the Internet continues to significantly outpace the addition of human users to the World Wide Web. New connections to the “Internet of Things” are now increasing by more than 6x the number of people being added to the “Internet of Humans” each year. Despite the increasing number of connections, IC Insights has trimmed back its semiconductor forecast for Internet of Things system functions over the next four years by about $1.9 billion, mostly because of lower sales projections for connected cities applications (such as smart electric meters and infrastructure). Total IoT semiconductor sales are still expected to rise 19% in 2016 to $18.4 billion, as shown in Figure 1, but the updated forecast first presented in the Update to the 2016 IC Market Drivers Report reduces the market’s compound annual growth rate between 2014 and 2019 to 19.9% compared to the original CAGR of 21.1%. Semiconductor sales for IoT system functions are now expected to reach $29.6 billion in 2019 versus the previous projection of $31.1 billion in the final year of the forecast.

Figure 1

Figure 1

The most significant changes in the new outlook are that semiconductor revenues for connected cities applications are projected to grow by a CAGR of 12.9% between 2014 and 2019 (down from 15.5% in the original forecast) while the connected vehicles segment is expected to rise by a CAGR of 36.7% (up from 31.2% in the previous projection). IoT semiconductor sales for connected cities are now forecast to reach $15.7 billion in 2019 while the chip market for connected vehicle functions is expected to be $1.7 billion in 2019, up from the previous forecast of $1.4 billion.

For 2016, revenues of IoT semiconductors used in connected cities applications are expected to rise 15% to about $11.4 billion while the connected vehicle category is projected to climb 66% to $787 million this year.

Sales of IoT semiconductors for wearable systems have also increased slightly in the forecast period compared to the original projection.  Sales of semiconductors for wearable IoT systems are now expected to grow 22% to about $2.2 billion in 2016 after surging 421% in 2015 to nearly $1.8 billion following Apple’s entry into the smartwatch market in 2Q15.  The semiconductor market for wearable IoT applications is expected to be nearly $3.9 billion in 2019.  Meanwhile, the forecast for IoT semiconductors in connected homes and the Industrial Internet categories remains unchanged.  The connected homes segment is still expected to grow 26% in 2016 to about $545 million, and the Industrial Internet chip market is forecast to increase 22% to nearly $3.5 billion.  The semiconductor forecast for IoT connections in the Industrial Internet is still expected to grow by a CAGR of 25.7% to nearly $7.3 billion in 2019 from $2.3 billion in 2014.

SEMICON Taiwan will be held from September 7 to 9 at Taipei Nangang Exhibition Center, Hall 1. Upbeat about the growth prospects of Taiwan’s semiconductor sector, SEMICON Taiwan 2016 features 600 exhibitors covering over 1,600 booths,and is expected to attract more than 43,000 visitors in three days.

For the sixth consecutive year, Taiwan has been the largest consumer of semiconductor equipment due to its large foundry and advanced packaging capacity, totaling $9 billion in 2016 and expecting to grow to $10 billion in 2017, accounting for a quarter of the global market. According to the latest report from IEK, the total production value of Taiwan semiconductor industry is expected to reach $2.4 trillion, performing better than the global market with a growth rate of 7.2 percent.

SEMICON Taiwan 2016 adds new pavilions including Okinawa (Japan), Philippines, Singapore, and World of IoT, in addition to pavilions on Cross-Strait, Kyushu (Japan), German, Holland High Tech and Korea, plus theme pavilions of AOI, CMP, High-Tech Facility, Materials, Precision Machinery, Secondary Market, Smart Manufacturing and Taiwan Localization. The total of nine theme pavilions and the eight country/region pavilions will offer visitors the most up-to-date options of greatest diversity.

The ascending trends of the Internet of Things and the need for smaller and more powerful mobile devices and wearables have created limitless new opportunities for semiconductor industry. In response to these trends, SEMICON Taiwan 2016 features the World of IoT pavilion showing off the latest application products, but also includes 21 forums, inviting speakers from the industry and academia, including TSMC, UMC, ASE, SPIL, Amkor, Lam Research, TEL and more, to share their exclusive perspectives on topics including memory, advanced packaging, semiconductor materials, high-tech facility, IC design, MEMS, 2.5D/3D IC technology, embedded and wafer level technology, and sustainable supply chain management. The three-day program is expected to attract over 4,000 attendances, providing an ideal platform for information exchange.

Covering the hottest topics like smart manufacturing, high-tech facility, and materials, more than 50 presentations will be given on TechXPOT stages, providing not only the latest technology updates but also great opportunities to meet potential partners.  To connect the right people and facilitate collaboration, SEMICON Taiwan organizes a series of networking events, like the Materials, High-Tech Facility, and Smart Manufacturing Get Togethers and the Supplier Search Program, creating business opportunities.

Diverse show activities and services include:

  • Live Broadcasting: HD live streaming provides first-hand highlights of forums and events from each corner on big screen and Facebook.
  • SEMICON Taiwan App: Providing the most updated exhibition information along with personal assistance functions, the SEMICON Taiwan App allows a smarter and more convenient visiting experience.
  • Jing Jing Lucky Draw: One of the most anticipated show activities will give away Ninebot One E+, Kodak Pixpro SP360, HTC Vive, Irobot Roomba, and new-years-eve hotel coupon.

Terry Tsao, SEMI Taiwan president states, “For years, SEMICON Taiwan not only has successfully connected Taiwan with the global markets, but also has bridged healthy communication between the government and the industry. Through increasing diversity, we expect to see SEMICON Taiwan continue to play an important role in facilitating collaboration and integration, helping the Taiwan semiconductor industry remain in a leading position.”

For more information, visit www.semicontaiwan.org/en

For decades, scientists have tried to harness the unique properties of carbon nanotubes to create high-performance electronics that are faster or consume less power — resulting in longer battery life, faster wireless communication and faster processing speeds for devices like smartphones and laptops.

But a number of challenges have impeded the development of high-performance transistors made of carbon nanotubes, tiny cylinders made of carbon just one atom thick. Consequently, their performance has lagged far behind semiconductors such as silicon and gallium arsenide used in computer chips and personal electronics.

Now, for the first time, University of Wisconsin-Madison materials engineers have created carbon nanotube transistors that outperform state-of-the-art silicon transistors.

The UW-Madison engineers use a solution process to deposit aligned arrays of carbon nanotubes onto 1 inch by 1 inch substrates. The researchers used their scalable and rapid deposition process to coat the entire surface of this substrate with aligned carbon nanotubes in less than 5 minutes. The team's breakthrough could pave the way for carbon nanotube transistors to replace silicon transistors, and is particularly promising for wireless communications technologies. Credit: Stephanie Precourt

The UW-Madison engineers use a solution process to deposit aligned arrays of carbon nanotubes onto 1 inch by 1 inch substrates. The researchers used their scalable and rapid deposition process to coat the entire surface of this substrate with aligned carbon nanotubes in less than 5 minutes. The team’s breakthrough could pave the way for carbon nanotube transistors to replace silicon transistors, and is particularly promising for wireless communications technologies. Credit: Stephanie Precourt

Led by Michael Arnold and Padma Gopalan, UW-Madison professors of materials science and engineering, the team’s carbon nanotube transistors achieved current that’s 1.9 times higher than silicon transistors. The researchers reported their advance in a paper published Friday (Sept. 2) in the journal Science Advances.

“This achievement has been a dream of nanotechnology for the last 20 years,” says Arnold. “Making carbon nanotube transistors that are better than silicon transistors is a big milestone. This breakthrough in carbon nanotube transistor performance is a critical advance toward exploiting carbon nanotubes in logic, high-speed communications, and other semiconductor electronics technologies.”

This advance could pave the way for carbon nanotube transistors to replace silicon transistors and continue delivering the performance gains the computer industry relies on and that consumers demand. The new transistors are particularly promising for wireless communications technologies that require a lot of current flowing across a relatively small area.

As some of the best electrical conductors ever discovered, carbon nanotubes have long been recognized as a promising material for next-generation transistors.

Carbon nanotube transistors should be able to perform five times faster or use five times less energy than silicon transistors, according to extrapolations from single nanotube measurements. The nanotube’s ultra-small dimension makes it possible to rapidly change a current signal traveling across it, which could lead to substantial gains in the bandwidth of wireless communications devices.

But researchers have struggled to isolate purely carbon nanotubes, which are crucial, because metallic nanotube impurities act like copper wires and disrupt their semiconducting properties — like a short in an electronic device.

The UW-Madison team used polymers to selectively sort out the semiconducting nanotubes, achieving a solution of ultra-high-purity semiconducting carbon nanotubes.

“We’ve identified specific conditions in which you can get rid of nearly all metallic nanotubes, where we have less than 0.01 percent metallic nanotubes,” says Arnold.

Placement and alignment of the nanotubes is also difficult to control.

To make a good transistor, the nanotubes need to be aligned in just the right order, with just the right spacing, when assembled on a wafer. In 2014, the UW-Madison researchers overcame that challenge when they announced a technique, called “floating evaporative self-assembly,” that gives them this control.

The nanotubes must make good electrical contacts with the metal electrodes of the transistor. Because the polymer the UW-Madison researchers use to isolate the semiconducting nanotubes also acts like an insulating layer between the nanotubes and the electrodes, the team “baked” the nanotube arrays in a vacuum oven to remove the insulating layer. The result: excellent electrical contacts to the nanotubes.

The researchers also developed a treatment that removes residues from the nanotubes after they’re processed in solution.

“In our research, we’ve shown that we can simultaneously overcome all of these challenges of working with nanotubes, and that has allowed us to create these groundbreaking carbon nanotube transistors that surpass silicon and gallium arsenide transistors,” says Arnold.

The researchers benchmarked their carbon nanotube transistor against a silicon transistor of the same size, geometry and leakage current in order to make an apples-to-apples comparison.

They are continuing to work on adapting their device to match the geometry used in silicon transistors, which get smaller with each new generation. Work is also underway to develop high-performance radio frequency amplifiers that may be able to boost a cellphone signal. While the researchers have already scaled their alignment and deposition process to 1 inch by 1 inch wafers, they’re working on scaling the process up for commercial production.

Arnold says it’s exciting to finally reach the point where researchers can exploit the nanotubes to attain performance gains in actual technologies.

“There has been a lot of hype about carbon nanotubes that hasn’t been realized, and that has kind of soured many people’s outlook,” he says. “But we think the hype is deserved. It has just taken decades of work for the materials science to catch up and allow us to effectively harness these materials.”

The researchers have patented their technology through the Wisconsin Alumni Research Foundation.

ZEISS introduces the new ZEISS ForTune system for photomask tuning. With its latest optical design, it takes two main mask tuning processes to the next level in terms of efficiency, accuracy and throughput. The first tool has already been delivered to the first customer.

The new ZEISS ForTune mask tuning system combines the capabilities from ZEISS CDC and RegC in a new advanced system. This means mask registration and Critical Dimension Uniformity (CDU) can be completed in one process. It helps to:

  1. Expand the Lithography Process Window and reduce the wafer intrafield hot spots (using the CDC technology)
  2. Improve wafer intra-field On-Product Overlay and enhance Mask Image Placement (using the RegC technology)

ZEISS ForTune is a technology with advanced system and optics design, allowing for high process efficiency and prediction accuracy, as well as for significantly improved output.

The mask tuning system has been first introduced to Wafer Fab customers at the SEMICON West in San Francisco, USA in July 2016.

“In order to produce IC devices at sub-16nm design nodes, semiconductor manufacturers are integrating many novel technologies, including multiple patterning, spacer pitch splitting, 3D logic and memory structures, new materials and complex reticles. Using these new technologies requires tight specifications for On-Product Overlay, Mask Registration, and Lithography Process Window. ForTune is a powerful new technology that enables Mask Makers and Wafer Fabs to tackle these challenges in a fast and cost-effective way,” states Ofir Sharoni, Product Manager of ZEISS ForTune in Karmiel, Israel. Another presentation of the new system will take place at the SPIE Photomask Conference in September 2016 in San Jose, USA.

Besides the official product launch, the next generation Wafer and Mask Tuning System has already been successfully delivered to an US based chip manufacturer, who ordered the new ZEISS ForTune system earlier this year.

Leading sensors and actuators companies will present the latest trends at the upcoming SEMI European MEMS Summit in Stuttgart on 15-16 September 2016.  Following 2015’s highly successful debut in Milano, the SEMI European MEMS Summit this year moves to Stuttgart. Over 250 attendees, including the industry’s global thought leaders, will discuss challenges, opportunities, and solutions.  A full capacity exhibition with representatives from the full value chain will complement the conference.

The event’s keynote presentations will feature:

  • Bosch Sensortec:  “Smart Connected MEMS Sensors – Enabler for the IoT” by Udo Gomez, CTO
  • STMicroelectronics:  “MEMS Sensors and Actuators – Opportunities and Challenges” by Benedetto Vigna, EVP and GM
  • Qorvo: “BAW and the ‘Edge of Tomorrow’ in Wireless Communication: Innovate, Ramp. Repeat” by Robert Aigner, Senior Director
  • AMKOR: “Sensor in Package – Standard Package Platform for Sensor Fusion and IoT” by Adrian Arcedera, VP

In addition to keynotes, the MEMS Summit’s exceptional speaker line-up includes presentations from ams AG, Bosch, Coventor, Fraunhofer IPMS, GLOBALFOUNDRIES, IHS, Invensas, NXP, Roland Berger, STMicroelectronics, Teledyne DALSA, and Yole Developpement.  The event’s main sessions will address Market and Business, Technology, Internet of Things, Automotive, Consumer, and Wearable Electronics. Promising start-ups Innoluce, USound, Polight and Enerbee will pitch their innovative solutions in a brand new session.

The Summit benefits from strong support from within the industry including Platinum Sponsor Bosch Sensortec; Gold Sponsors ASE Group, STMicroelectronics, and SUSS MicroTec; Silver Sponsors Applied Materials, EV Group, LAM Research, and SPTS. Other sponsors include AMKOR Technology, JSR Micro, Materion, Trymax, and VAT.

For more information and registration, please visit www.semi.org/eu/EuropeanMEMSSummit

Driven by rising demand for thinner wafers and stronger die, dicing technology is evolving.

“Reaching more than US$100 million in 2015, the dicing equipment market will double by 2020-2021,” announced Yole Développement (Yole) (Source: Thin Wafer Processing & Dicing Equipment Market report, Yole Développement, May 2016). Yet at the same time thin wafers are creating new challenges of significant interest in the dicing equipment industry such as die breakage, chipping, low die strength, handling issues and dicing damage.

Yole’s Technology & Market Analyst, Amandine Pizzagalli, is pleased to give her vision of the dicing technologies, market forecast and competitive landscape during the webcast “Plasma Dicing for Next Generation Ultra Small and Ultra Thin Die” organized by SPTS Technologies, an Orbotech company. This webcast will take place on September 14. To register click PLASMA DICING.

Today, the most common dicing technology applied across memory, logic, MEMS, RFID and power devices is mechanical dicing, also known as blade dicing. 

“Blade dicing represents more than 80% of the dicing brand equipment business in terms of dicing tools and stealth dicing 20%,” explained Amandine Pizzagalli from Yole.

However, companies are showing a growing need for thinner wafers and smaller devices in general and Yole sees a trend towards adopting alternative dicing technologies. These include stealth dicing and plasma dicing based on deep reactive ion etching technology. Yole’s analysts details the plasma dicing market per application:

  • Memory specifically has predominantly relied on a combination of blade and laser dicing applied together to singulate complex stacks. Using only blade dicing on top layers leads to delamination issues because of the high metal density. However, it’s difficult to safely singulate 50 µm thin wafers even with laser dicing and this could allow plasma dicing to enter this area. “Even if the philosophy of the designers is changing, memories manufacturers are still the most conservative”, details Amandine from Yole.
  • In MEMS devices blade dicing is largely applied for singulating the ASIC, capping and MEMS sensors. However, exposure to water from the process can contaminate some sensors and destroy sensitive MEMS structures, example in MEMS microphones. In such cases, stealth dicing has been already adopted in large volume production. Plasma dicing has also been adopted in low volume production today for MEMS devices.
  • In parallel, the RFID is a growing market segment: plasma dicing is already in production but the adoption rate is still small. According to Yole’s analysts, a fast growth for plasma dicing especially for RFID devices is expected. Indeed plasma dicing has the ability to reduce die fragility, boost die strength, increase the number of chips per wafer and thus reduce Cost Of Ownership of equipment overall.

“As die sizes continue to shrink, singulation by plasma etching offers considerable benefits for die quality and strength as compared to traditional dicing solutions,” stated Richard Barnett, Etch Product Manager at SPTS Technologies, an Orbotech company. And he adds: “Ultra-small and ultra-thin devices like RFID chips or fragile devices like MEMS are more susceptible to damage from the vibration and chipping caused by mechanical saws, or from the heat caused by lasers.”

Under its new thin wafer & dicing equipment market report, the “More than Moore” market research and strategy consulting company is analyzing the competitive landscape: the current market is today controlled by DISCO and Accretech, which today claim market shares of almost 80% focused on blade dicing and stealth dicing, respectively:

  • DISCO leads the blade dicing market and offers a large product portfolio including stealth dicing and laser ablation. They have also a partnership with Plasma-Therm which gives them access to the complete range of dicing technologies: Yole’s analysts had the opportunity to discuss the market, its evolution and challenges with Abdul Lateef, CEO, and Thierry Lazerand, Business Development Director, of Plasma-Therm. To discover this interview, click Plasma-Therm solution.
  • Accretech leads the stealth dicing market offering.
  • ASM Pacific is a strong player in laser ablation, especially because their process does not lead to contamination issues compared to standard laser ablation technology.

During SPTS Technologies webcast, Amandine Pizzagalli will describe the today’s competitive landscape of the key dicing technologies across MEMS devices, power devices, CMOS image sensors, and RFID devices, highlighting her major findings on the evolution and trends of the dicing technologies.

These results are part of Yole’s report entitled Thin Wafer Processing & Dicing Equipment Market. Under this analysis, Yole presents a comprehensive overview of the key dicing technologies benchmarks in terms of feature requirements. This report includes insights into the number of tools, broken down by wafer size, by application and by dicing technology… A full description of the report is available on i-micronews.com, manufacturing reports section.

In parallel, SPTS Technologies speaker, Richard Barnett also proposes an overview of the latest advances in plasma dicing. During his talk, Richard will highlight the latest data illustrating how processing routes affect die strength, share experiences with different types of tapes and other die features such as solder balls. SPTS Technologies will share details of the latest equipment which is now available for plasma dicing wafers up to 300mm (on 400mm tape frames) for full production applications.

Edwards logo

September 22, 2016 at 1:00 p.m. ET

Free to attend

Length: Approximately one hour

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The semiconductor industry’s response to perfluorinated compounds PFCs started in 1994 when DuPont, the supplier of the primary gas used in CVD chamber cleans, C2F6, issued a sales policy restricting sales after 12/31/96 “…only to those applications that contain and either recover or destroy” C2F6 subsequent to use. The sales policy started an industry effort to understand potential impacts of all fluorinated greenhouse gases used in semiconductor manufacturing and to develop methods to estimate and reduce emissions. The industry has worked on a global basis via the World Semiconductor Council to develop common PFC metrics, measurement methodologies and approaches to reduce emissions. Preferring a pollution prevention approach, the industry and its suppliers have evaluated and implemented when feasible process optimization, gas substitution, capture/recycle and abatement. The WSC also set a goal to reduce absolute PFC emissions by 10% from baseline levels by 2010. The WSC exceeded the 2010 goal, achieving a 32% reduction, largely by replacing carbon based PFC chamber cleaning gases with NF3 in new process equipment, optimizing processes to reduce gas consumption, and using alternative chemistries and installing abatement where feasible. The new WSC2020 target calls for the implementation of best practices to further reduce normalized emissions in 2020 by 30% from the 2010 aggregated baseline. How do the semiconductor industry’s greenhouse gas emissions compare to other sectors, what data uncertainties exist, and what can be done to cost effectively achieve further emissions reductions?

Speakers: 

Debbie Ottinger, USEPA

Deborah Ottinger has worked on the U.S. Environmental Protection Agency’s (EPA’s) programs to protect climate and stratospheric ozone since 1991. She currently plays a key role in the implementation of EPA’s Greenhouse Gas Reporting Program (GHGRP), which requires large emitters and suppliers of greenhouse gases (GHGs) to monitor and report their emissions and supplies to EPA. She also manages the U.S. Emissions Inventory Program for fluorinated GHGs emitted from industrial processes.

Dr. Michael Czerniak, Environmental Solutions Business Development Manager, Edwards

Starting his professional career with Philips, initially in their UK R&D labs and subsequently in the fab in Nijmegen, Holland, Mike has worked in the semiconductor business since gaining his PhD in 1982. He had subsequent marketing roles at UK-based OEMs Cambridge Instruments, VSW and VG Semicon before joining Edwards 19 years ago. He has held various technical and marketing roles before starting his current role earlier this year.

David Speed, Distinguished Member of the Technical Staff, GLOBAL FOUNDRIES

David Speed is a Distinguished Member of the Technical Staff at GLOBALFOUNDRIES. He works in the corporate EHS group and represents GLOBALFOUNDRIES on a wide variety of environmental, health, and safety issues. He has a PhD in Environmental Engineering from UCONN, with BS and MS degrees from URI and RPI.

Sponsored by Edwards

Edwards is a leading developer and manufacturer of sophisticated vacuum system products, abatement solutions and related value-added services. Our products are integral to manufacturing processes for semiconductors, flat panel displays, LEDs and solar cells; are used within an increasingly diverse range of industrial processes including power, glass and other coating applications, steel and other metallurgy, pharmaceutical and chemical; and for both scientific instruments and a wide range of R&D applications.