Yearly Archives: 2016

Semiconductor Research Corporation (SRC) today announced that Tokyo Electron Limited (TEL) has joined SRC’s Nanomanufacturing Materials and Processes (NMP) initiative.

TEL’s addition contributes to a 33 percent increase in core SRC membership over the last 18 months and is the second non-US headquartered company to join within the same period. It is further indication of how important pre-competitive research is to overcome the current obstacles that impede future semiconductor technology progress.

“SRC is pleased TEL has made the decision to invest research dollars into the NMP program,” said Ken Hansen, President & CEO, SRC. “TEL’s addition strengthens research throughout the entire semiconductor supply chain that has consistently provided SRC members end-to-end solutions to the challenges facing the industry.”

As one of twelve different research areas, the NMP initiative focuses on developing revolutionary and high-impact materials and processes to enable future generations of semiconductor manufacturing technologies, while training well-educated students for innovation-driven careers in integrated circuit manufacturing. Key NMP research topics include Extreme Ultraviolet Lithography (EUV), Directed Self-Assembly (DSA), Atomic Layer Deposition and Etch (ALD/ALE) processes, interconnect scaling and optimization, and new semiconductor device materials.

“TEL sees the value of collaborating as a member of the SRC NMP program to find solutions for important semiconductor technology issues,” said Gishi Chung, Corporate Director & SVP, TEL.

Problems frequently arise as a result of an incomplete or absent formal risk assessment when processes are modified or new materials introduced.

BY ALAN IFOULD and ANDREW CHAMBERS, Edwards, North Somerset, UK

The sub-fab is home to the many pumps and abatement systems that not only help to create the pristine environments required in the process chambers of the numerous tools in the cleanroom, but also handle the exhaust gases and by-products generated by the manufacturing process. In this respect, the efficiency and efficacy of sub-fab operations directly affect the availability, productivity, total operating cost and yield of the manufacturing fab above. Perhaps more importantly, in addition to supporting the process vacuum, equipment in the sub-fab is designed to render cleanroom process wastes harmless and ready for safe disposal or, if appropriate, release into the environment. As such, they are vital to protecting the safety of the people working in the fab as well as those living and working in the surrounding community, and ultimately, all of us who share that environment. The very nature of the process materials and reaction byproducts handled in the sub fab, which may be variously corrosive, toxic, pyrophoric, flammable or environmentally damaging, creates significant risks, especially for those who must operate and maintain the equipment located there. Moreover, as device manufacturing becomes more complex, with the introduction of new materials, new precursors and new processes, the risk of mistakes with potentially catastrophic consequences in both human and financial terms will only increase.

While ultimate responsibility for personnel safety in the sub-fab lies with the fab operator, equipment manufac- turers have a part to play by optimizing their products not only for efficient, effective and reliable operation, but also by ensuring any risks associated with operation, maintenance and repair are assessed and minimised to the greatest extent possible.

There is often a strong focus on technical performance and cost attributes when selecting sub-fab equipment. However, processes and procedures to ensure optimum operation and continuous mitigation of risks to service personnel are equally critical; these demand the devel- opment of clear and effective operating procedures and guidelines – in industry jargon “best known methods” or BKMs – to ensure the equipment achieves its full performance potential and safety integrity maintained. The manufacturers of sub-fab equipment are perhaps in the best position to define these guidelines since they will typically have acquired an understanding of the risks posed by hazardous materials on a case-by-case basis during the course of system optimization. Frequent development of BKMs is undertaken in collaboration with the process tool manufacturer or early adopters of the process. However, defining operating and maintenance methods and procedures that are truly the best known requires a commitment to doing so at the highest levels of corporate management, and a formal process of reporting, analysis, synthesis and dissemination throughout the equipment support community.

A key component of any BKM program is the active participation of the equipment manufacturer’s service personnel who are responsible for installing, commissioning and maintaining the equipment and are also likely to have first- hand knowledge and experience of the potential hazards. Since service personnel are invariably in the front-line when safety incidents occur, they are well motivated to contribute since they themselves are often at greatest risk, and it is essential that their contribution is incorporated into product development programs to complement the technical performance with assured safety and reliability.

Even a cursory search of the internet will quickly reveal numerous examples of fab and sub-fab incidents. Amongst the lessons that can be taken from these events is that the risk management process and the resulting controls have to cover every foreseeable circumstance across the equipment lifecycle: installation, commissioning, operation, servicing and maintenance. Notable recent serious accidents include:

– March 2014 – A fab worker dies after a carbon dioxide leak

– January 2013 – One worker dies and four others are hospitalized after a hydrofluoric acid leak at a manufacturing facility

– September 2013 – A fire at major memory fab results in the closure of the facility with losses estimated in the range of $1 billion and a measurable impact on global DRAM pricing

– August 2012 – A security guard and 3 firefighters are hospitalized when a fire occurs in the exhaust ducts of a photovoltaic manufacturing laboratory in Singapore. The entire facility is shut down for weeks and 35 workers are laid off

These were events with consequences visible and far-reaching enough to make the national and international news. However, experience indicates that smaller events, often with narrowly-averted disastrous consequences, occur on a much more frequent basis with adverse impacts on fab productivity. These events are typically not widely broadcast, thereby limiting the community learning that might otherwise take place.

In respect of process exhausts, three types of hazard recur repeatedly as manufacturing processes evolve and new process materials are introduced: condensation of reactive chemical precursors or reaction products, corrosion due to condensation of acidic materials, and pipe blockage due to accumulation of condensate in significant volume. The images in FIGURES 1-3 show a few examples.

FIGURE 1. (left) Condensed explosive polysiloxane material in an epitaxial deposition system process foreline, (middle and right) CVD exhaust pipe destroyed by explosion of condensed process by-product.

FIGURE 1. (left) Condensed explosive polysiloxane material in an epitaxial deposition system process foreline, (middle and right) CVD exhaust pipe destroyed by explosion of condensed process by-product.

FIGURE 2. (left) Acidic TEOS-based polymer with a pH of approximately 1, (middle) Condensed corrosive Br2-based liquid, (right) Exhaust pipe damaged by exposure to condensed acidic material.

FIGURE 2. (left) Acidic TEOS-based polymer with a pH of approximately 1, (middle) Condensed corrosive Br2-based liquid, (right) Exhaust pipe damaged by exposure to condensed acidic material.

FIGURE 3. Exhaust blockage caused by various materials (left) AlCl3 from a metal etch process, (middle) NH4Cl from an LPCVD process, (right) Unknown material deposited in the exhaust of a metal carbide CVD process.

FIGURE 3. Exhaust blockage caused by various materials (left) AlCl3 from a metal etch process, (middle) NH4Cl from an LPCVD process, (right) Unknown material deposited in the exhaust of a metal carbide CVD process.

In many cases, the cause of the risk is understood and solutions exist, but problems frequently arise as a result of an incomplete or absent formal risk assessment when processes are modified or new materials introduced. For example, condensation of potentially dangerous or explosive materials can usually be prevented by carefully controlling the temperature of the exhaust gas through the pipework and pumps. Pipe heating systems are widely available for forelines and exhaust pipes, and pumps can be designed with internal thermal management, but if the risk is not properly assessed, the appropriate controls will not be put in place. Furthermore, while a risk analysis may conclude that exhaust pipe heating is required in a specific case, it should also recognize that key to its effective implementation is the avoidance of cool spots, particularly at bends and junctions. Even a small local drop in temperature can create a hazardous situation despite the application of what is widely perceived as an effective protective measure – a subtle effect, but one with which field service personnel have become familiar through hard-won experience. At a practical level, if each process exhaust is designed in isolation, such considerations make their design and implementation a time-consuming and labor-intensive process. However, as noted in a previous publication [1] the ability to maintain effective thermal control throughout the exhaust stream can be enhanced by integrating the vacuum pumping and point- of-use abatement functions together with the interconnecting exhaust pipes into a single unified system. In this way the pipe routing can be standardized to permit optimization of the exhaust pipe heating installation for each specific process and to avoid the need for customization in the field. Integration and standardization also permits careful optimization of pump capacities and pipe diameters and routing to minimize power consumption and maximize destruction or removal efficiency (DRE). Finally, whether consid- ering an integrated system or not, secondary enclosures for pumps, abatement and exhaust pipes provide an additional layer of protection by permitting hazardous materials to be routed away from personnel in the event of an unintended release.

In some cases, it is not possible to prevent the accumu- lation of hazardous materials. It then becomes essential to monitor the deposition and remove it through periodic maintenance procedures. For example, blockage can be monitored by measuring the pressure drop over the length of the exhaust pipe – as material accumulates in the pipe the pressure drop increases. By monitoring for blockage, operators can ensure that the system is cleaned before its performance impacts production and at the same time avoid cleaning more frequently than required. Integrated vacuum and abatement systems often combine monitoring capabilities with automated software to alert operators of the need for maintenance.

While problems associated with accumulation of materials in process exhausts is arguably the most frequently encountered hazard faced by sub-fab maintenance personnel, another widely applied risk mitigation strategy, particularly for flammable process materials, is dilution below their lower flammability limit (LFL) with an inert gas such as nitrogen. However, it is important to understand the nature of the chemical processes occurring in the deposition chamber and to base the dilution calculation on the composition and volume of the effluent gas rather than the precursor. For example, TEOS is a precursor gas widely used in the chemical vapor deposition of silicon oxide films. The lower temperature needed for the CVD process and the absence of aggressive reaction products are the main advan- tages of using TEOS compared with traditional precursors such as silane and the mechanical and electrical properties of Si02 films deposited from TEOS are also very good. The decomposition products of TEOS in the gas phase in the absence of oxygen include organic fragments (ethanol, ethanal, ethene, methane, carbon monoxide), and in the presence of oxygen include water vapour, carbon dioxide, ethanal and methanol [2], many of which are flammable. A dilution calculation based on the amount of TEOS entering the chamber rather than the volume of decompo- sition products exiting the chamber could easily lead to an underestimate of the required volume of diluent and the presence of a flammable mixture in the exhaust pipe in some circumstances. Once again, a rigorous risk assessment is required to identify such potential hazards and put corrective measures in place where needed.

Risk assessment and communication

It should be clear from the preceding discussion that a detailed technical understanding of semiconductor manufacturing processes and materials and their impact on sub-fab equipment is a prerequisite for safe and efficient pumping and abatement of process exhaust. In particular, ensuring the safety of sub fab operations requires a formal process for risk assessment. Once determined, safe operating proce- dures must be codified and effectively communicated to field personnel, and a mechanism must exist to update procedures based on feed-back from the field. FIGURE 4 is taken from the Risk Assessment Procedure [3] used at Edwards (adapted from Semi S10) and illustrates the Risk Rating Table, a matrix by which risks are evaluated and appropriate responses determined.

Once risks are assessed the information must be effec- tively communicated to users and field service personnel. To ensure appropriate dissemination of required information, Edwards publishes Application Notes for equipment users and Safety Application Procedures (SAP) for service engineers.

Conclusion

The hazardous nature of many of the materials present in the semiconductor manufacturing process creates significant safety risks for fab personnel and others living or working near the fab, and financial risks for manufacturers and investors. Managing those risks takes more than good intentions and common sense precautions. It requires a detailed and continuously updated technical understanding of the processes and materials based on broad experience across many different types of applications, and ideally, partnership with process tool manufacturers during development and optimization of new processes. As in other high risk industries – nuclear, aviation, automotive, healthcare, oil, rail and military – best practice safety and risk management is heavily influ- enced by equipment manufacturers, who are in the best position to understand the capabil-
ities of their products across a wide range of applications.

Ultimately the fab management team own the responsibility for managing risk and safety with the highest levels of corporate respon- sibility. Semiconductor equipment manufacturers, and in particular, manufacturers of pumping and abatement systems that handle and safely dispose of hazardous materials, have an invaluable supporting role to play with their continuous accumulation of know-how and formal processes for risk assessment, including a mechanism for distributing safety information to, and incorporating feedback from, the field.

References

1. Andrew Chambers, Managing hazardous process exhausts in high volume manufacturing, Solid State Technology, 2016 Issue 2
2. Van der Vis, M.G.M., et al, The thermodynamic properties of tetrae- thoxysilane (TEOS) and an infrared study of its thermal decomposition, Colloque C3, supplement au Journal de Physique 11, Volume 3, aofit 1993, http://dx.doi.org/10.1051/jp4:1993309
3. Adapted from Semiconductor Equipment and Materials International (SEMI) standard S-10, http://www. semi.org

New wafer processing technologies overcome FOWLP’s technical hurdles, paving the way for a new generation of ultra compact, high I/O electronic devices.

BY DAVID BUTLER, SPTS Technologies, an Orbotech company, Hereford, UK

Our ability to create ever-smaller electronic devices that maintain or surpass the performance of their physically larger predecessors – exemplified by today’s wearables, smartphones and tablets – is dictated by many factors that extend well beyond Moore’s Law, from the underlying embedded components to the ways in which they’re packaged together. With regard to the latter, fan-out wafer level packaging (FOWLP) is quickly emerging as the new die and wafer level packaging technique of choice, and is widely antici- pated to underpin the next generation of compact, high performance electronic devices.

Whereas with conventional flip-chip WLP schemes the I/O terminals are spread over the chip surface area, limiting the number of I/O connections, FOWLP embeds individual die in an epoxy mold compound (EMC) with space allocated between each die for additional I/O connection points, avoiding the use of more expensive silicon real estate to accommodate a higher I/O count. Redistribution layers (RDLs) are formed using physical vapor deposition (PVD) and subsequent electroplating and patterning to re-route I/O connections on the die to the mold compound regions on the periphery (FIGURE 1).

FIGURE 1. FOWLP process flow.

FIGURE 1. FOWLP process flow.

Leveraging FOWLP, semiconductor devices with thousands of I/O points can be seamlessly connected via finely-spaced lines as thin as two to five microns, maximizing interconnect density while enabling high bandwidth data transfer. Significant height and cost savings are achieved via the elimination of the substrate.

With FOWLP today we have the ability to embed heterogeneous devices including baseband processors, RF transceivers and power management ICs in these mold wafers, thereby enabling the latest gener- ation of ultra-thin wearables and mobile wireless devices. With continued line and space reductions, FOWLP has the potential to accommodate higher performing devices including memory and application processors, positioning FOWLP to extend into new markets including automotive and medical applications and beyond.

Leading vendors implementing FOWLP today include Amkor, ASE, Freescale, NANIUM, STATS ChipPAC, and TSMC, with TSMC being the most high-profile vendor given its widely-reported contract win to produce A10 processors for Apple’s iPhone 7 – a deal said to be attrib- utable in part to TSMC’s mature FOWLP-based InFO technology.

According to a report entitled “FO WLP Forecast update 09/2015” published by research firm Yole Développement in September 2015, the launch of TSMC’s InFO format is expected to increase industry packaging revenues for FOWLP from $240M in 2015 to $2.4B in 2020. With a projected 54% CAGR, Yole expects FOWLP to be the fastest growing advanced packaging technology in the semiconductor industry.

Low heat, high speed processing

All fan-out wafers feature singulated die embedded in the EMC, with spin-on dielectrics surrounding the RDL. These materials present some unique challenges, including moisture absorption, excessive outgassing and a limited tolerance to elevated temperatures. If not dealt with properly, contamination at the metal deposition stage can compromise contact resistance.

Whereas conventional circuits built on silicon can withstand heat up to 400oC and can be degassed in under one minute, the EMC and dielectrics used in FOWLP have a heat tolerance closer to 120oC. Temperatures exceeding this low threshold can cause decompo- sition and excessive wafer warping. Degassing wafers at such low temperatures naturally takes a longer amount of time, and can drastically reduce the throughput of a conventional sputter system.

Multi-wafer degas (MWD) technology has emerged as a compelling solution to this problem, enabling up to 75 wafers to be degassed at 120oC in parallel before being individually transferred to subsequent pre-clean and sputter deposition, without breaking vacuum.

With this approach, wafers are dynamically pumped under clean, high vacuum conditions, with radiation heat transfer warming wafers directly to temperatures within the operating budget for packaging applications.

Each wafer can spend up to 30 minutes inside the MWD, but because they’re processed in parallel, a “dry” wafer is outputted for metal deposition every 60 to 90 seconds, at a rate of between 30 to 50 wafers per hour. This approach increases PVD system throughput by 2-3 times compared to a single wafer degas processing technology, and as materials emerge with even lower thermal budgets based on increased passivation thickness, longer degas times can be accommodated with no impact on throughput (FIGURE 2).

FIGURE 2. The Sigma fxP PVD system with multi-wafer degas module from Orbotech-SPTS.

FIGURE 2. The Sigma fxP PVD system with multi-wafer degas module from Orbotech-SPTS.

These benefits are not readily attainable, however, unless we can overcome the attendant warping challenges. Epoxy mold wafers can be warped after curing, and the size and shape of the warpage hinge on the different shapes, densities and placement of the embedded die. A FOWLP PVD system must therefore be able to minimize temperature-induced shape shifting, and accommodate wafers with up to a 10mm bow. The acceptable industry threshold for bowing is probably lower than 6mm, however, as it’s not easy to make uniformly thick conductors on a substrate exhibiting 6mm+ warpage.

Utmost integrity

After successful degas, but prior to metal deposition, the FO wafer is pre-cleaned in a plasma etch module. This facilitates the removal of trace oxide layers from the contacts, but due to the composition of the organic dielectric surrounding the contacts, will result in carbon build-upon the chamberwalls.This carbon does not adhere well to ceramic chamber surfaces, and if not carefully managed, can result in early particle failure.

New in-situ paste technologies allow these carbon deposits to better adhere to chamber surfaces during the pre-cleaning process, enabling preventative maintenance intervals that exceed 6,000 wafers. This approach can significantly improve productivity by reducing the frequency of dedicated wafer pastes, which typically require production to be paused every 10 to 20 wafers for chamber pasting when using conventional techniques.

The myriad benefits that FOWLP promises for the production of ultra compact, high I/O electronic devices far outweigh the aforementioned technical barriers to mainstream FOWLP adoption. With the ability to overcome the degassing, warping, and integrity challenges that can impede FOWLP implementations, electronics manufacturers can unlock the full potential of FOWLP while eliminating frictions affecting production speeds and yields.

Recent breakthroughs in materials engineering of low-resistance W barriers/liners and bulk fill are making it possible to extend W use to next-generation devices.

BY JONATHAN BAKKE, Applied Materials, Santa Clara, CA

Tungsten (W), with its low resistivity and minimal electro-migration, has long been used for a variety of applications in fabricating semiconductor devices. For instance, it is used for logic contact, local interconnect (LIC), and metal gate (MG) fill as well as DRAM buried word line and contact and 3D NAND MG and contact. Sustained scaling, however, is posing challenges to its continued use with conventional process flows. Interconnect dimensions have shrunk to the point at which contact resistance is becoming an obstacle to realizing optimum transistor performance; fill integrity degrades as aspect ratios and the degree of re-entrance increase, making it difficult to ensure high-quality metallization.

At earlier nodes, larger dimensions made W fill possible using conformal CVD deposition. Now, overhang around the tops of ultra-small openings or bowing from the interconnect etch open preclude the conformal process from completely filling features without voids, while center seams are an inevitable result of conformal deposition, even in the absence of voids. These attributes render extremely small features vulnerable to breach during CMP, causing high resistance or complete failure of an inter- connect. High feature densities and lack of via redundancy in advanced chip designs mean that a single void can cause complete device failure and significant yield loss.

Fortunately, recent breakthroughs in materials engineering of low-resistance W barriers/liners and bulk fill are overcoming these limitations and making it possible to extend W use to next-generation devices. The former lower resistance by simplifying fill film requirements and enlarging the volume available for W fill; the latter eliminates undesirable seams to create more robust structures.

Low-resistance liners

To date, high-resistivity TiN has been predominantly used as an adhesion layer for CVD W and to block fluorine penetration during the bulk fill process. W does not grow directly on TiN; thus, it requires deposition of a nucleation layer before the fill step. As logic devices scale through the 10 nm node and beyond, the maximum critical dimension (CD) of the LIC willbe

Metal-organic deposition of thin W-based films offers an ideal solution, because it can eliminate high-resistance liners and nucle- ation layers while maintaining adhesion and fluorine-barrier properties equiv- alent to those of the current process flow. A new W liner has been developed that lowers line resistance for further device scaling: plasma-enhanced (PE) CVD W that nucleates on metal and oxides.

The PECVD W film is produced using a specialized chemical in the presence of reactive plasma that breaks down the ligands. The film composition is primarily W, and the atoms from the decomposed ligands are bonded to the W. The amorphous character of the film and the dopants in it from the ligand lead to good adhesion to dielec- trics and fluorine barrier properties in the 20-30Å range.

FIGURE 1 shows a simulation of a contact plug in the 4-30nm range. The model contains parallel and series resistors for the plug and through resistance. Features are assumed to be straight wall trenches. Resistance of 12 μΩ*cm is used for W at all thicknesses, which under-estimates the benefit of PECVD W. Scattering at film interfaces is not taken into account. The inflections in the curves (from right to left) occur when a film is removed due to volume constraints. It is clear that the benefit of PECVD W increases exponentially as CDs decrease, especially without the nucleation layer.

FIGURE 1. Plug resistance simulation demonstrates the significant benefit of PECVD W without a nucleation layer.

FIGURE 1. Plug resistance simulation demonstrates the significant benefit of PECVD W without a nucleation layer.

SiO2 trench structures with CDs ranging from 10nm to 150nm and a depth of 100nm were used to investigate W line resistance and evaluate gap-fill performance. As shown in FIGURE 2, line resistance in a ~10 nm CD dropped by nearly 90% compared with the conventional stack.

FIGURE 2. PECVD W plus gap fill reduces line resistance by nearly 90% over the conventional stack. The inset TEM shows conformal gap fill and CMP integration for PECVD W.

FIGURE 2. PECVD W plus gap fill reduces line resistance by nearly 90% over the conventional stack. The inset TEM shows conformal gap fill and CMP integration for PECVD W.

Seam-suppressed gap fill

Until now, feature dimensions have made W fill integration possible using nucleation followed by conformal CVD deposition – which always leaves a seam in features. At CDs

A new approach employs a unique, “selective” suppression mechanism that results in a bottom-up fill free of seams or voids. Pre-treating the nucleation layer creates preferred W growth from the bottom of the structure upwards and less on the field, minimizing the likelihood of void-creating pinch-off and seams (FIGURE 3). Experiments showed the process to be successful on structures with CDs ranging from 10nm to 150nm.

FIGURE 3. a.Cross-sectional TEM image of SSW partial fill of 30nm CD,100nm deep trench pattern with overhang created byAr sputter and PVD Ti. (b) TEM image of seamless SSW fill of the same structure. (c) TEM image of standard CVD W gap fill with seam.

FIGURE 3. a.Cross-sectional TEM image of SSW partial fill of 30nm CD,100nm deep trench pattern with overhang created byAr sputter and PVD Ti. (b) TEM image of seamless SSW fill of the same structure. (c) TEM image of standard CVD W gap fill with seam.

Electrical tests confirmed that SSW lowered line resistance compared to that of conventional CVD W (FIGURE 4). Post-CMP defect analysis by top-down view SEM revealed a narrow seam in conventional CVD W after W CMP (FIGURE 5a), while none is visible after SSW fill (FIGURE 5b).

FIGURE 4. Line resistance comparison of SSW and conventional CVD W on 10nm trench.

FIGURE 4. Line resistance comparison of SSW and conventional CVD W on 10nm trench.

Tungsten 5-1

FIGURE 5. Top-down SEM image of a) conventional CVD W process with visible seam in the center of the trench and b) SSW fill on the same structure.

FIGURE 5. Top-down SEM image of a) conventional CVD W process with visible seam in the center of the trench and b) SSW fill on the same structure.

Conclusion

For the next several nodes of logic and memory fabrication, W will remain an important material in interconnect and gate metallization. However, as scaling continues, transi- tions in process flows will be necessary to achieve low contact and line resistance while maintaining gap-fill integrity. A new W-based barrier/liner has been produced through precision materials engineering that improves device performance and integration while simplifying process flows. Similarly, a new SSW gap-fill process increases the volume of W (potentially lowering resistance), creates more robust features for post-fill integration, and relaxes requirements on CMP and dielectric etch steps, thus delivering performance, device design, and yield benefits.

For further detail on the processes presented in this article, see Bakke, J., et al., “Fluorine-Free Tungsten Films as Low Resistance liners for Tungsten Fill Applications” and Kai,W.,etal.,“ImprovingTungstenGap-FillforAdvance Contact Metallization,” presented at the 2016 IEEE Inter- national Interconnect Technology Conference.

BY DR. ZHIHONG LIU, Chairman and CEO, ProPlus Design Solutions

Semiconductor processes have long been a mystery for many circuit designers. They didn’t need to worry about how chips were fabricated most of the time, thanks to the many EDA innovations that make their jobs easier and complex designs possible.

The success of the foundry-fabless business model over the past 20 years has been one of the main drivers of the booming of semiconductor industry. The cooperation between foundries and IC designs in fabless companies for process development worked so well that process engineers and circuit designers only needed to focus on their area of expertise. EDA flows simplified the interaction by using process design kits (PDKs) as the information carrier for circuit designs and sent tapeout databases (GDSII) back to the foundry for chip fabrication. Most designers didn’t need to dig into the process.

That was then. The designer now is forced to understand process and devices when moving to smaller nodes in order to achieve more competitive designs. Because process is the least understood, the loose link between process and design should be enhanced to improve design and tapeout confidence.

Knowing processes and devices would help designers make better use of the process platform and improve designs. Device geometries are getting smaller and new structures such as FinFET and FD-SOI are becoming mainstream leading to complicated device characteristics and SPICE models, the most critical components in the PDK. They represent a process platform’s performance and device characteristics, fundamental to good circuit design. A solid understanding of SPICE models becomes necessary to make full use of the process. This is true not only for designs at advanced nodes at 28nm beyond, such as 16nm, 14nm and10nm, but critical for some refreshed older technologies for IoT/Wearable applications.

Running a full evaluation of process and device performance would provide guidance to better select device types, optimize device sizes and bias conditions, trade-off circuit speed and power. The same logic can be applied to generic circuit designs at any technology node, such as analog
designs at 180nm or above.

This practice is used mostly within IDMs where process and design teams have fairly direct channels to work cooperatively. Recently, fabless companies strengthened links with foundries to under- stand the process and devices to improve design output or for process-circuit co-design for high-end chip designs with more aggressive speed, power and performance specifications.

These efforts are significant. Most companies don’t have the resources and time to build a dedicated team and flow and there have been no available EDA tools dedicated to helping designers understand process and facilitate process development interactions. Increasing time-to-market pressures and tough competition drive the need to a higher priority.

Without an EDA tool, current practices can easily take weeks or months to build, maintain and run a flow by creating scripts or SPICE netlists for different evaluation items. It’s practically impossible to run through the cases to generate a full picture of process platform for designers within a short turnaround time.

As a result, it’s hard to come up with a set standard for process evaluation before using it in design, as efforts can vary for different projects. For a big corporation with many design projects, dealing with multiple foundries, using multiple technology nodes and different process platforms, this type of work is critical to its success however becomes overloaded.

Furthermore, the complexity of SPICE models is exploding. Thousands of parameters in each model and a huge model library file with more than 100K lines of code are quite common. Macro models with complicated layout- dependent effects and random variations add more dimensions of complexity.

Complexity and time pressures are huge. An EDA tool to manage both would be indispensable.

One tool could use the PDK library as the input to explore, compare and verify models. It could help designers under- stand and explore the process-design space to guide process platform selection and enable quick adoption of the process and assist designs. It would help designers dig into the process from different angles, including a high-level summary of the process and device performance, device characteristics, statistical behavior and circuit performance related to the application. This should enable designers quickly adopt and make full use of a process platform that suits their needs.

Pixelligent Technologies, a developer of high-index advanced materials for solid state lighting and display applications and producer of PixClear products, announced today that it closed $10.4 million in new funding. The round was led by The Abell Foundation, The Bunting Family Office, and David Testa, the former Chief Investment Officer of T. Rowe Price. Funds will be used to complete the installation of additional manufacturing capacity, open new offices in Asia, and continue to drive innovation in lighting, display and optical applications.

To date Pixelligent has raised over $36.0M in equity funding and has been awarded more than $12M in U.S. government grant programs to support the development of its proprietary PixClear products and PixClearProcess. The Pixelligent nanotechnology platform includes proprietary nanocrystal synthesis, capping technology, high volume manufacturing and application engineering that supports ink jet, slot die, UV curing, spray coating, and numerous other manufacturing processes.

“We have clearly established Pixelligent as the leading high-index materials manufacturer for demanding solid state lighting and OLED display applications throughout the world. Pixelligent is partnering with leading advanced materials suppliers to deliver breakthrough performance that currently spans applications in 12 discrete markets including: lighting, displays, printed and flexible electronics, AR/VR, optically clear adhesives, MEMS, gradient index lenses, and others with a combined total over $9B in market opportunities. We have numerous commercial applications currently in the market and expect additional product introductions before the end of 2016,” said Craig Bandes, President & CEO of Pixelligent Technologies.

“We started our partnership with Pixelligent in 2011 when the company relocated to Baltimore City and have seen the company achieve all of their critical technology and manufacturing milestones, while establishing a global brand and presence. Our investment objective is to support leading edge companies that deliver breakthrough technology and products and create jobs in our local community. Pixelligent is at the forefront in delivering on the promise of the nanotechnology revolution. We are proud of what the team at Pixelligent has accomplished to date and we look forward to their continued growth and success,” said Eileen O’Rourke, CFO of The Abell Foundation.

Mentor Graphics Corporation (NASDAQ:  MENT) today announced the first phase of the new Xpedition printed circuit design (PCB) flow to address the increasing complexity of today’s advanced systems designs. The increasing densities of electronics products are forcing companies to develop highly compact system designs with more functionality, and at lower costs. To efficiently manage the density and performance requirements for advanced PCB systems, the new Xpedition flow provides advanced technologies to enable design and verification of 3D rigid-flex structures, and to automate layout of high-speed topologies with advanced constraints.

“Our customers are industry leaders developing the world’s most advanced electronics systems. They require access to technologies that enable deployment of advanced technologies and techniques, from design for high performance, advanced packaging, growth of rigid-flex, and higher speeds and densities,” said AJ Incorvaia, vice president and general manager, Mentor Graphics Board Systems Division. “To deliver the latest Xpedition Enter­prise flow, we have partnered with our customers to address their strategic initiatives to manage increasing complexity, increase organizational collaboration, drive greater end-product quality, and facilitate enterprise IP management.”

Managing advanced rigid flex design complexity

Flex and rigid-flex PCBs are now found in all types of electronics products, from small consumer devices to aerospace, defense and automotive electronics where high reliability and safety are critical. The Xpedition rigid-flex technology enables a streamlined design process from initial stack-up creation through manufacturing.

Engineers can design complex rigid and flex PCBs in a fully supported 3D environment (3D design and verification—not just a 3D view), resulting in a correct-by-construction methodology for optimum reliability and product quality. 3D verification ensures that bends are in the right position, and elements on the board do not interfere with folding; this can be reviewed early in the design stage to prevent costly redesigns. Users can then export a 3D solid model to MCAD for efficient bi-directional PCB-enclosure co-design.

Integration with Mentor’s leading HyperLynx high-speed analysis technology enables optimization of signal and power integrity across complex rigid-flex stack-up structures. For fabrication preparation, the Xpedition flow provides all flex and rigid information using the ODB++ common data format. This methodology eliminates data ambiguities by clearly communicating the finished board intent to the fabricator. The new Xpedition flow is the optimum solution designed specifically for flex and rigid-flex design, from conception through fabrication output.

“Mentor’s new Xpedition flow provides multiple board outlines, stack-ups, and bend areas which allow us to define a rigid flex within the design environment, and export a folded 3D step model for efficient mechanical design integration,” stated Charles Ietswaard, PCB design engineer at NIKHEF, the national institute for sub-atomic physics in The Netherlands. “The automated rigid-flex capabilities in Xpedition help us manage the growing complexities of today’s advanced PCB systems with ease, higher productivity and overall product reliability.”

IC Insights will release its August Update to the 2016 McClean Report later this month. This Update includes an update of the semiconductor industry capital spending forecast, an analysis of the IC foundry industry, and a look at the top-25 semiconductor suppliers for 1H16, including a forecast for the full year ranking (the top 20 1H16 semiconductor suppliers are covered in this research bulletin).

The top-20 worldwide semiconductor (IC and O-S-D—optoelectronic, sensor, and discrete) sales ranking for 1H16 is shown in Figure 1. It includes eight suppliers headquartered in the U.S., three in Japan, three in Taiwan, three in Europe, two in South Korea, and one in Singapore, a relatively broad representation of geographic regions.

The top-20 ranking includes three pure-play foundries (TSMC, GlobalFoundries, and UMC) and six fabless companies. If the three pure-play foundries were excluded from the top-20 ranking, China-based fabless supplier HiSilicon ($1,710 million), U.S.-based IDM ON Semiconductor ($1,695 million), and U.S.-based IDM Analog Devices ($1,583 million) would have been ranked in the 18th, 19th, and 20th positions, respectively.

IC Insights includes foundries in the top-20 semiconductor supplier ranking since it has always viewed the ranking as a top supplier list, not a marketshare ranking, and realizes that in some cases the semiconductor sales are double counted. With many of our clients being vendors to the semiconductor industry (supplying equipment, chemicals, gases, etc.), excluding large IC manufacturers like the foundries would leave significant “holes” in the list of top semiconductor suppliers. As shown in the listing, the foundries and fabless companies are identified. In the April Update to The McClean Report, marketshare rankings of IC suppliers by product type were presented and foundries were excluded from these listings.

Overall, the top-20 list shown in Figure 1 is provided as a guideline to identify which companies are the leading semiconductor suppliers, whether they are IDMs, fabless companies, or foundries.

Figure 1

Figure 1

Thirteen of the top-20 companies had sales of at least $3.0 billion in 1H16.  As shown, it took $1.86 billion in sales just to make it into the 1H16 top-20 semiconductor supplier list.  There was one new entrant into the top-20 ranking in 1H16 as compared to the 2015 ranking—AMD, which replaced Japan-based Sharp.  In 2Q16, AMD registered a strong 23% increase in sales while Sharp was moving in the opposite direction logging a 13% decline in its 2Q16/1Q16 revenue.

Intel remained firmly in control of the number one spot in the top-20 ranking in 1H16.  In fact, it increased its lead over Samsung’s semiconductor sales from only 20% in 2015 to 33% in 1H16.  The biggest upward move in the ranking was made by Apple, which jumped up three positions in the 1H16 ranking as compared to 2015. Other companies that made noticeable moves up the ranking include MediaTek and the new Broadcom Ltd. (the merger of Avago and Broadcom), with each company moving up two positions.

Apple is an anomaly in the top-20 ranking with regards to major semiconductor suppliers. The company designs and uses its processors only in its own products—there are no sales of the company’s MPUs to other system makers.  IC Insights estimates that Apple’s custom ARM-based SoC processors had a “sales value” of $2.9 billion in 1H16, which placed them in the 14th position in the top-20 ranking.

In total, the top-20 semiconductor companies’ sales increased by 7% in 2Q16/1Q16.  Although, in total, the top-20 2Q16 semiconductor companies registered a 7% increase, there were seven companies that displayed a double-digit 2Q16/1Q16 jump in sales and only two that registered a decline (Intel and Renesas).

The fastest growing top-20 company in 2Q16 was Taiwan-based MediaTek, which posted a huge 32% increase in sales over 1Q16.  Although worldwide smartphone unit volume sales are forecast to increase by only 5% this year, MediaTek’s application processor shipments to the fast-growing China-based smartphone suppliers (e.g., Oppo and Vivo), helped drive its stellar 2Q16/1Q16 increase.  Overall, IC Insights expects MediaTek to register about $8.8 billion in sales in 2016, which would represent a 31% surge over the $6.7 billion in sales the company had last year.

As expected, given the possible acquisitions and mergers that could/will occur over the next few years, the top-20 ranking is likely to undergo a significant amount of upheaval as the semiconductor industry continues along its path to maturity.

A look at control of process uniformity across the wafer during plasma etch processes.

BY STEPHEN HWANG and KEREN KANARIK, Lam Research Corporation, Fremont, CA

Controlling process variability to achieve repeatable results has always been important for meeting yield and device performance requirements. With every advance in technology and change in design rule, tighter process controls are needed. In all of these cases, there are multiple sources of variability, often generalized as: within die, across wafer, wafer to wafer, and chamber to chamber. Typically, less than one third of the overall variation is allowed for variation across the wafer. For example, at the 14 nm node, the allowable variation for gate critical dimensions (CDs) is less than 2.4 nm, of which only about 0.84 nm is allowed for variation across the wafer [1]. At the 5 nm node, the allowable variation across the wafer may be less than 0.5 nm, or equivalent to two or three silicon atoms. In this article, we will discuss control of process uniformity across the wafer during plasma etch processes, its evolution in the industry, and some key focus areas.

A fundamental challenge in controlling uniformity in etch processes is the complexity of a plasma. Achieving the desired etch result (e.g., post-etch profile with selectivity to different film materials) requires managing the ratio of different ions and neutrals (e.g., Ar+, C4F8, C4F6+, O, O2+). Since the same plasma generates both types of species, the relative amount of ions to neutrals is strongly coupled. As a result, the impact of parameters typically used to control the plasma (e.g., source power and chamber pressure) are also interdependent.

Improving uniformity through design

Since the start of single-wafer processing in the early 1980s, etch chambers have been designed to produce similar plasma conditions on every location on the wafer to achieve uniform process results. This is especially challenging since there can be inherent electrical and chemical discontinuities at the edge (FIGURE 1) that affect uniformity across the wafer. Voltage gradients are created at the wafer edge due to the change from a biased surface to a grounded or floating surface. This bends the plasma sheath at the wafer edge, which changes the trajectory of ions relative to the wafer. The chemical potential discontinuity is analogous and produces concentration gradients for different species across the wafer. The gradients are caused by multiple phenomena, including variation in reactant consumption and by-products emissions rates at the center relative to the edge, as well as differences in temperature between the chamber and wafer that cause different absorption rates of chemical species.

Lam_Research_Figure_01

FIGURE 1. Discontinuities caused by the wafer edge create gradients that impact uniformity across the surface, with a significant impact at the edge.

 

Many chamber design changes have been implemented over the years to improve radial symmetry (FIGURE 2a). For example, a key hardware parameter for capacitively coupled plasma (CCP) chambers is the gap between the cathode and anode. Historically, the gap would be designed to provide the most uniform etch for a given power, pressure, and mixture of gas chemistries. On inductively coupled plasma (ICP) chambers, the gas injection location was a key design feature that would vary by process. In aluminum etch chambers, the reactant gas was delivered from a showerhead above the wafer. For silicon etch, the reactant gases were injected from around the perimeter of the wafer, but then evolved so that the gas was injected from above the center of the wafer.

FIGURE 2. Process non-uniformity has both radial and non- radial components (A). On a wafer map showing overall non- uniformity, removal of radial asymmetry allows isolating the more challenging non-radial component (B).

FIGURE 2. Process non-uniformity has both radial and non- radial components (A). On a wafer map showing overall non- uniformity, removal of radial asymmetry allows isolating the more challenging non-radial component (B).

With continuous optimization of chamber design, non-radial patterns became more apparent. On a uniformity map, the average of all the points within every radius can be taken and subtracted from the map, which leaves the more difficult asymmetric portion (FIGURE 2b). With this awareness, focus shifted toward elimi- nating asymmetries in the chamber design.

In retrospect, some of these improvements seem obvious. For instance, up to the late 1990s, it was not uncommon to have etch chambers with the turbomolecular pump located to the side of the wafer. This design created a side- to-side pattern due to the convective flow of reactants and by-products laterally across the wafer. By moving the pumps under the wafer, the flow became radially symmetric, thereby eliminating the process asymmetry.

In other cases, the source of asymmetry was more subtle. One interesting non-uniformity corrected with design was a problematic side-to-side pattern on the wafer that had a seemingly random orien- tation chamber-to-chamber. After extensive investigation to eliminate possible sources in the chamber hardware, the pattern was correlated with the Earth’s magnetic field (FIGURE 3). This example demon- strates the sensitivity of plasma processes, even to minor external influences. Although not specifically a chamber issue, the problem was corrected by applying special shielding with high magnetic-permeability materials around the chamber.

FIGURE 3. Non-uniformity induced by the Earth’s magnetic field was identified in an etch process (A). Applying magnetic shielding corrected the problem and provided uniform etch results (B).

FIGURE 3. Non-uniformity induced by the Earth’s magnetic field was identified in an etch process (A). Applying magnetic shielding corrected the problem and provided uniform etch results (B).

 

Development of process tuning capabilities

As etch processes became more varied and complex, fixed chamber designs were not sufficiently flexible to meet increasingly stringent requirements since it was not practical to provide a specific uniformity kit optimized for each etch process. Moreover, it was more challenging to achieve uniform results when etch technology transitioned from processing 200 mm to 300 mm wafers in the early 2000s. As a result, tuning capabilities were developed to deliver the uniformity control needed for a wide range of processes and larger wafer sizes.

By the early 2000s, the first uniformity tuning knobs focused on controlling the chemistry over the wafer. This was done in several ways, for example by splitting the main reactant gases into different locations or by adding tuning gases at separate locations from the main reactant gas. Since then, a number of tunable parameters have been identified for etch processes (Table 1). Ideally, orthogonal (independent) tuning knobs are used in order to match compensation as closely as possible to root causes. This provides the greatest impact on the process while limiting impact on other parameters. For example, in many dielectric etch processes, the etch rate is limited by the flux of ions from the plasma. Since gas injection doesn’t significantly impact plasma density uniformity, Lam Research developed tunable gap technology for CCP chambers to achieve uniform flux of ions across the wafer for a given set of process conditions.

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Over the years, continued development has focused on increasing the spatial resolution for better control across the wafer. For example, gas was at first only injected from the center location above the wafer. Then, additional capability was added that allowed controlling the ratio of gas directed to the center or edge of the wafer. Several years later, an additional gas injection location was added around the periphery of the wafer. To use wafer temperature as a control knob, different heating or cooling zones can be added to an electrostatic chuck (ESC), which holds the wafer. Historically, the number of temperature zones has increased from one to two (by 2002) to four radial zones (by 2006) to improve the radial uniformity of CDs. Since temperature directly affects CD uniformity (CDU), this is an effective way to tackle one of the most critical uniformity challenges.

Some of the most complex process flows today rely on these sophisticated tuning capabilities. Innovations that drive continuous scaling, such as 3D FinFET devices, advanced memory schemes, and double/quadruple patterning techniques, add to the challenge of reducing variability due to the increasing number of steps within the integration flows. Even if the uniformity for individual unit processes (including etch) are relatively good, their combined impact can be significant, and there is need to compensate somewhere in the flow.

When the uniformity profile of a step in the sequence, upstream or downstream, is known and difficult to correct, the profile of an etch step can be modified. For example, if one step is center fast, etch can compensate by being edge fast. This may sound simple, but it is actually quite difficult to achieve the level of process control that can essentially provide a mirror image of the non-uniformity in another process. Fortunately, plasma etch is one process that has matured to being capable of this level of control.

Uniformity control today

After many years of innovation, uniformity control capabilities now have the following characteristics:
• A high degree of granularity (numerous independent tuning locations across the wafer)
• Active tuning of both radial and non-radial patterns
• The ability to compensate for non-unifor- mities upstream and downstream of the etch process

One strategy being used at Lam to achieve the degree of control now needed is providing numerous independent heaters or micro-zones to control the wafer temperature, which is a critical parameter impacting CD uniformity. For example, using more than 100 localized heaters on one etch chamber delivers significantly higher spatial resolution than a system using only two or four heater zones for the entire wafer. Control of numerous individual heaters tunes both radial and non-radial patterns, whereas only center-middle-edge tuning was possible in previous generations (FIGURE 4).

FIGURE 4. Active uniformity control has evolved from limited radial tuning of large areas of the wafer to independent tuning of ever smaller regions across the wafer, enabling control of both radial and non-radial uniformity.

FIGURE 4. Active uniformity control has evolved from limited radial tuning of large areas of the wafer to independent tuning of ever smaller regions across the wafer, enabling control of both radial and non-radial uniformity.

With such high granularity, it is challenging for an individual engineer to manually determine the appropriate settings for so many heaters that will achieve a target thermal pattern across the wafer. To address this issue, advanced algorithms and controls with special temperature calibrations were developed so that the system automatically controls the heaters. Moreover, it can be difficult to determine the thermal map profile that will achieve the required process uniformity. Sophisticated software algorithms have also been developed to use process trends, chamber calibration data, and wafer metrology information to automatically create the appropriate thermal maps. With this capability, incoming non-uniformity can be reduced to less than 0.5 nm CDU after etch (FIGURE 5).

FIGURE 5. Proprietary hardware and software map incoming CDs and adjust etch process conditions in the numerous micro- zones across the wafer to compensate for variability from upstream processes.

FIGURE 5. Proprietary hardware and software map incoming CDs and adjust etch process conditions in the numerous micro- zones across the wafer to compensate for variability from upstream processes.

Future focus areas

Beyond the uniformity challenges discussed, performance at the edge of the wafer – the outer 10mm, where up to 10% of the die may be located – is an increasingly important area of future focus for improving yield. In this region, uniformity control is dominated by the electrical discontinuities at the edge of the wafer that can cause sheath bending. The impacted region of sheath bending is much smaller (~10-15 mm from the edge) compared to chemical or thermal effects (50-70 or 30-50 mm, respectively). While fixed edge hardware can be redesigned for optimal uniformity, new technologies are in development to provide in situ tunability of the sheath at the wafer edge.

Looking ahead, we can expect more types of control knobs and further granularity for finer tuning along with a greater focus on automation. Compensatory process control should continue to develop and be used as process modules become increasingly complex.

REFERENCES

1. ITRS 2013: Table FEP 12 Etch Process Technology Requirements

A major research institution has placed orders for two Advanced Vacuum plasma processing systems that will provide etch and deposition capabilities to be used in nanoelectronics research and development.

The order by imec, a Belgium-based, global nanoelectronics R&D center, is for two Advanced Vacuum Apex SLR systems. One will be configured with an inductively-coupled plasma (ICP) source, with the other configured for high-density plasma chemical vapor deposition (HDPCVD). Apex SLR® systems incorporate a field-proven, high-density plasma source that was developed by Plasma-Therm, parent company of Advanced Vacuum, for its widely used Shuttlelock® line of plasma tools.

Imec is an internationally renowned research institute that works with global partners on many types of nanoelectronics-based innovation. Imec is headquartered in Belgium and has offices in the Netherlands, Taiwan, USA, China, India, and Japan.

Dr. David Lishan, Director, Technical Marketing for Plasma-Therm, noted that “Plasma-Therm has a long history supporting R&D institutions, and this order continues that tradition. We are pleased that leading R&D organizations rely on Plasma-Therm technology for developing new processes and creating smaller, faster, and more efficient devices.”

“It’s gratifying that these Apex SLR systems were selected by imec’s scientists to help develop industry-relevant technology solutions,” Dr. Lishan said. Recent imec innovations include disposable photonics biosensors, flexible electronics, hyperspectral imaging devices, and 3D device integration (advanced packaging) processes.

Advanced Vacuum’s Apex SLR is a highly versatile, small-footprint plasma processing system. Apex SLR ICP is capable of etching a wide range of materials used in semiconductor devices and nanotechnology, while the Apex SLR HDPCVD enables relatively low-temperature plasma deposition of high-quality thin films. These films can include optical coatings, semiconductor device passivation layers, and other materials used in nanoelectronic fabrication and other applications with limited processing thermal budget.