Yearly Archives: 2016

Beyond its gloom, the MEMS industry is showing numerous emerging devices that hold promise for future growth. These innovative MEMS solutions were listed by the MEMS & Sensors team of Yole Développement (Yole) in the Status of the MEMS Industry 2016 report (Yole Développement, May 2016). Today, more than 100 businesses, startups and large companies are involved in exciting developments using MEMS technology. The MEMS approach can be defined as a transfer function: It lowers cost and improves integration and performance.

transfer function

“MEMS can be seen as a ‘transfer function’ using semiconductor and micromachining technologies to create devices replacing devices that are more complex, bulky or less sensitive,” explains Dr. Eric Mounier, Sr. Technology & Market Analyst at Yole. Yole has identified at least 5 criteria that determine the success of a MEMS device. They are: size reduction, potential cost reduction, “good enough” specifications, batch manufacturing compared to existing solutions, and reliability.
At least 10 to 15 years of development are required to achieve all the successful criteria.

“Based on this segmentation, and out of all the MEMS devices in development that could undergo significant growth in the future, we foresee ultrasonic and gas sensors as well as microspeaker as the next success for the MEMS industry,” details Dr. Mounier.

As Yole’s market forecast announces, the gas sensor market is showing a 7.3% CAGR for the 2014–2021 period. The market should reach US$920 million in 2021. Moreover Yole’s analysts highlight a potential upside market of almost US$65 million in 2021. This positive scenario might be possible if gas sensors are widely adopted in consumer products, analysts say (Source: Gas Sensor Technology & Market report, Yole Développement, February 2016).

Microspeakers could be part of the success story as well. Indeed a big transition is happening now: for the first time, silicon speakers are ready for volume production, enabling the creation of a brand-new multibillion-dollar market for MEMS manufacturers. Last month, Yole’s analysts had an interesting interview with USound, an Austrian company founded three years ago by several veterans of the MEMS industry.

“Prototypes of the first balanced-armature replacement and the first micro-tweeter are currently being sampled to selected customers,” USound asserted. “Pre-production will start at the end of the summer, along with internal qualification. The technology is ready for adoption and will revolutionize the personal-audio market, similar to what happened with the MEMS microphone.”

USound intends to evolve into an audio-system developer, offering complete solutions ranging from hardware to firmware, in order to simplify technology adoption and help our customers achieve optimum product performance. To read the full interview, click USound.

For the next few months, Yole will pursue its investigation into the MEMS world. Numerous technology and market reports will be released, and Yole’s MEMS & Sensors team will attend many key conferences to present its vision of the industry.

For example, in mid-September Yole will be part of two major events in Asia: MEMS & Sensors Conference Asia and Sensor Expo & Conference – China. At both conferences, Yole will present attendees with the status of the industry and its new virtuous cycle. Yole’s Speaker, Claire Troadec, MEMS & Semiconductor Manufacturing Analyst, will focus her presentation on the Chinese MEMS industry, which is steadily transforming from “Made in China” to “Created in China.” Claire will also review the Chinese MEMS players and the new virtuous cycle the MEMS industry.

It may be clammy and inconvenient, but human sweat has at least one positive characteristic – it can give insight to what’s happening inside your body. A new study published in the ECS Journal of Solid State Science and Technology aims to take advantage of sweat’s trove of medical information through the development of a sustainable, wearable sensor to detect lactate levels in your perspiration.

“When the human body undergoes strenuous exercise, there’s a point at which aerobic muscle function becomes anaerobic muscle function,” says Jenny Ulyanova, CFD Research Corporation (CFDRC) researcher and co-author of the paper. “At that point, lactate is produce at a faster rate than it is being consumed. When that happens, knowing what those levels are can be an indicator of potentially problematic conditions like muscle fatigue, stress, and dehydration.”

Utilizing green technology

Using sweat to track changes in the body is not a new concept. While there have been many developments in recent years to sense changes in the concentrations of the components of sweat, no purely biological green technology has been used for these devices. The team of CFDRC researchers, in collaboration with the University of New Mexico, developed an enzyme-based sensor powered by a biofuel cell – providing a safe, renewable power source.

Biofuel cells have become a promising technology in the field of energy storage, but still face many issues related to short active lifetimes, low power densities, and low efficiency levels. However, they have several attractive points, including their ability to use renewable fuels like glucose and implement affordable, renewable catalysts.

“The biofuel cell works in this particular case because the sensor is a low-power device,” Ulyanova says. “They’re very good at having high energy densities, but power densities are still a work in progress. But for low-power applications like this particular sensor, it works very well.”

In their research, entitled “Wearable Sensor System Powered by a Biofuel Cell for Detection of Lactate Levels in Sweat,” the team powered the biofuel cells with a fuel based on glucose. This same enzymatic technology, where the enzymes oxidize the fuel and generate energy, is used at the working electrode of the sensor which allows for the detection of lactate in your sweat.

Targeting lactate

While the use of the biofuel cell is a novel aspect of this work, what sets it apart from similar developments in the field is the use of electrochemical processes to very accurately detect a specific compound in a very complex medium like sweat.

“We’re doing it electrochemically, so we’re looking at applying a constant load to the sensor and generating a current response,” Ulyanova says, “which is directly proportional to the concentration of our target analyte.”

Practical applications

Originally, the sensor was developed to help detect and predict conditions related to lactate levels (i.e. fatigue and dehydration) for military personnel.

“The sensor was designed for a soldier in training at boot camp,” says Sergio Omar Garcia, CFDRC researcher and co-author of the paper, “but it could be applied to people that are active and anyone participating in strenuous activity.”

As for commercial applications, the researchers believe the device could be used as a training aid to monitor lactate changes in the same way that athletes use heart rate monitors to see how their heart rate changes during exercise.

On-body testing

The team is currently working to redesign the physical appearance of the patch to move from laboratory research to on-body tests. Once the scientists optimize how the sensor adheres to the skin, its sweat sample delivery/removal, and the systems electronic components, volunteers will test its capabilities while exercising.

“We had actually talked about this idea to some local high school football coaches,” Ulyanova says, “and they seem to really like it and are willing to put forth the use of their players to beta test the idea.”

After initial data is gathered, the team will be able to work with other groups to interpret the data and relate it to the physical condition of the person. With this, predictive models could be built to potentially help prevent conditions related to individual overexertion.

Future plans for the device include implementing wireless transmission of results and the development of a suite of sensors (a hybrid sensor) that can detect various other biomolecules, indicative of physical or physiological stressors.

SJ Semiconductor Corp. (SJSemi) and Qualcomm Technologies, Inc., a subsidiary of Qualcomm Incorporated (NASDAQ:  QCOM), jointly announced that SJSemi has begun mass production of 14nm wafer bumping for Qualcomm Technologies. In the wake of 28nm wafer bumping mass production, and with further improvement of its processing techniques and capabilities, SJSemi has become China’s first semiconductor company to enter the industrial chain with 14nm advanced process node mass production. Mass production of the 14nm wafer bumping in China is part of Qualcomm Technologies’ efforts to continuously drive the development of the Chinese integrated circuit industry, and it further reinforces Qualcomm Technologies’ commitment to China through industrial chain optimization, localized services, and superior offers to Chinese customers.

Founded in August 2014, SJSemi is a joint venture between Semiconductor Manufacturing International Corp. (SMIC) and Jiangsu Changjiang Electronics Technology Co., Ltd (JCET). In December 2015, Qualcomm Global Trading Pte Ltd., a subsidiary of Qualcomm Incorporated, participated in an additional investment in SJSemi. SJSemi realized mass production of the 28nm wafer bumping in early 2016, within two years of its inception, and it now ships 12-inch wafers in high volume every month. SJSemi has sharpened its unique competitive edge in 28nm bumping technology by achieving not only a first-class yield rate but also industry-leading key technical indicators such as contact resistance control over high-density copper pillar bumping. SJSemi will continue to expand the capacity of its 12-inch wafer bumping line, securing the supply chain for its customers. Currently, SJSemi has reached the production capacity of bumping 20,000 12-inch wafers per month.

“We are grateful to Qualcomm Technologies for its consistent support. With its assistance, we have managed to set up an advanced 12-inch bumping line with stable and efficient production to offer mass production services to our customers,” said Mr. Dong Cui, Chief Executive Officer of SJSemi. “The mass production of our 14nm wafer bumping technology is in recognition of our capabilities and strengths, and indicates our ability to offer comprehensive services to first-class global customers like Qualcomm Technologies. We expect to continuously keep pace with customer demand, further improve our technical capability, enrich our process methods, and boost our added value to the industrial chain.”

“The 14nm bumping production from SJSemi is very important to Qualcomm Technologies and has begun mass production, which demonstrates SJSemi’s world-class manufacturing capabilities in leading-edge bumping process technology,” said Dr. Roawen Chen, Senior Vice President, QCT global operations, Qualcomm Technologies, Inc. “We are pleased to work with SJSemi to expand our semiconductor supply chain footprint in China, which further shows our commitment to support China’s local IC manufacturing and better serve our Chinese customers.”

A team of scientists led by the Department of Energy’s Oak Ridge National Laboratory has developed a novel way to produce two-dimensional nanosheets by separating bulk materials with nontoxic liquid nitrogen. The environmentally friendly process generates a 20-fold increase in surface area per sheet, which could expand the nanomaterials’ commercial applications.

ORNL's Huiyuan Zhu places a sample of boron nitride, or "white graphene," into a furnace as part of a novel, nontoxic gas exfoliation process to separate 2-D nano materials. Credit: ORNL

ORNL’s Huiyuan Zhu places a sample of boron nitride, or “white graphene,” into a furnace as part of a novel, nontoxic gas exfoliation process to separate 2-D nano materials. Credit: ORNL

“It’s actually a very simple procedure,” said ORNL chemist Huiyuan Zhu, who co-authored a study published in Angewandte Chemie International Edition. “We heated commercially available boron nitride in a furnace to 800 degrees Celsius to expand the material’s 2D layers. Then, we immediately dipped the material into liquid nitrogen, which penetrates through the interlayers, gasifies into nitrogen, and exfoliates, or separates, the material into ultrathin layers.”

Nanosheets of boron nitride could be used in separation and catalysis, such as transforming carbon monoxide to carbon dioxide in gasoline-powered engines. They also may act as an absorbent to mop up hazardous waste. Zhu said the team’s controlled gas exfoliation process could be used to synthesize other 2D nanomaterials such as graphene, which has potential applications in semiconductors, photovoltaics, electrodes and water purification.

Because of the versatility and commercial potential of one-atom-thick 2D nanomaterials, scientists are seeking more efficient ways to produce larger sheets. Current exfoliation procedures use harsh chemicals that produce hazardous byproducts and reduce the amount of surface area per nanosheet, Zhu said.

“In this particular case, the surface area of the boron nitride nanosheets is 278 square meters per gram, and the commercially available boron nitride material has a surface area of only 10 square meters per gram,” Zhu said. “With 20 times more surface area, boron nitride can be used as a great support for catalysis.”

Further research is planned to expand the surface area of boron nitride nanosheets and also test their feasibility in cleaning up engine exhaust and improving the efficiency of hydrogen fuel cells.

Engineers from the University of Utah and the University of Minnesota have discovered that interfacing two particular oxide-based materials makes them highly conductive, a boon for future electronics that could result in much more power-efficient laptops, electric cars and home appliances that also don’t need cumbersome power supplies.

Their findings were published this month in the scientific journal, APL Materials, from the American Institute of Physics.

The team led by University of Utah electrical and computer engineering assistant professor Berardi Sensale-Rodriguez and University of Minnesota chemical engineering and materials science assistant professor Bharat Jalan revealed that when two oxide compounds — strontium titanate (STO) and neodymium titanate (NTO) — interact with each other, the bonds between the atoms are arranged in a way that produces many free electrons, the particles that can carry electrical current. STO and NTO are by themselves known as insulators — materials like glass — that are not conductive at all.

But when they interface, the amount of electrons produced is a hundred times larger than what is possible in semiconductors. “It is also about five times more conductive than silicon [the material most used in electronics],” Sensale-Rodriguez says.

This innovation could greatly improve power transistors — devices in electronics that regulate the electrical current –by making power supplies much more efficient for items ranging from televisions and refrigerators to handheld devices, Sensale-Rodriguez says. Today, electronics manufacturers use a material called gallium nitride for transistors in power supplies and other electronics that carry large electrical currents. But that material has been explored and optimized for many years and likely cannot be made more efficient. In this discovery made by the Utah and Minnesota team, the interface between STO and NTO can be at the very least as conductive as gallium nitride and likely will be much more in the future.

“When I look at the future, I see that we can perhaps improve conductivity by an order of magnitude through optimizing of the materials growth,” Jalan says. “We are bringing the possibility of high power, low energy oxide electronics closer to reality.”

Power transistors that use this combination of materials could lead to smaller devices and appliances because their power supplies would be more energy efficient. Laptop computers, for example, could ditch the bulky external power supplies — the big black boxes attached to the power cords — in favor of smaller supplies that are instead built inside the computer. Large appliances that consume a lot of electricity such as air conditioners could be more power efficient. And because there is less power wasted (wasted electricity usually dissipates into heat), these devices will not run as hot as before, says Sensale-Rodriguez. He also believes that if more electronics use these materials for transistors, collectively it could save significant amounts of electricity for the country.

“It’s fundamentally a different road toward power electronics, and the results are very exciting” he says. “But we still need to do more research.”

Over the past 20 years, China has become increasingly frustrated over the gap between its IC imports and indigenous IC production (Figure 1).  It has oftentimes been quoted over the last couple of years that China’s imports of semiconductors exceeds that of oil.

In its upcoming Mid-Year Update to The McClean Report 2016 (released at the end of this week), IC Insights examines the “Three-Phase” history of China’s attempt at strengthening its position in the IC industry that started in earnest in the late 1990s (Figure 2).

Figure 1

Figure 1

Figure 2

Figure 2

In the late 1990s, China began to contemplate ways to grow its indigenous IC industry and assisted in creating Hua Hong NEC, which was founded in 1997 as a joint venture between Shanghai Hua Hong and Japan-based NEC (it merged with Grace in 2011).  Then, as part of the country’s 10th Five Year Plan (2000-2005), establishing a strong China-based IC foundry industry became a priority.  As a result, pure play foundries SMIC and Grace (now Hua Hong Semiconductor) were both founded in 2000 and XMC was founded in 2006.  This effort is categorized by IC Insights as Phase 1 of China’s IC industry strategy.

In the early 2000s, to help boost the sales of its indigenous foundries, as well as ride the strong wave of fabless IC supplier growth, the Chinese government began attempts to foster a positive environment for the creation of Chinese fabless companies. It should be noted that eight of the current top 10 Chinese fabless IC suppliers were started between 2001 and 2004 and seven of them were in the top 50 worldwide ranking of fabless IC companies last year. This stage of China’s IC industry strategy is labeled by IC Insights as Phase 2.

IC Insights believes that Phase 3 of China’s attempt at creating a strong China-based IC industry began in 2014, just before the start of its 13th Five Year Plan which runs from 2015 through 2020.  As discussed in detail in the Mid-Year Update, this Phase is being supported by a huge “war chest” of cash that is intended to be used to purchase IC companies and their associated intellectual property, provide additional funding to China’s existing IC producers (e.g., SMIC, Grace, XMC, etc.), and to help establish new IC producers (e.g., Sino King Technology, Fujian Jin Hua, etc.).

In 1Q16, the U.S. Department of Commerce slapped an export ban on U.S. IC suppliers’ shipments of ICs to China-based telecom giant ZTE in response to the company allegedly shipping telecommunications equipment to Iran while it was under trade sanctions by the U.S. This ban, if fully enacted, would have a devastating effect on ZTE’s telecom equipment sales (including mobile phones). Thus far, the export ban has been postponed until August 30, 2016 pending further investigation by the U.S. Department of Commerce.

The situation regarding ZTE and the abrupt announcement earlier this year of export controls on the company by the U.S. government sent shock waves throughout the Chinese government as well as China’s electronic system manufacturers.  At this point in time, such potentially drastic measures taken by the U.S. government against such a large Chinese electronics company has bolstered the Chinese government’s resolve to make China more self-sufficient regarding IC component production, spurring increased emphasis on “Phase Three.”

Worldwide silicon wafer area shipments increased during the second quarter 2016 when compared to first quarter 2016 area shipments according to the SEMI Silicon Manufacturers Group (SMG) in its quarterly analysis of the silicon wafer industry.

Total silicon wafer area shipments were 2,706 million square inches during the most recent quarter, a 6.6 percent increase from the 2,538 million square inches shipped during the previous quarter. New quarterly total area shipments are 0.1 percent higher than second quarter 2015 shipments and are at their highest recorded quarterly level.

“Silicon shipment growth continues to gain momentum resulting in a quarterly volume shipment high,” said Dr. Volker Braetsch, chairman SEMI SMG and senior vice president of Siltronic AG. “Although year-to-date shipments are effectively flat relative to the same period as last year.”

Silicon* Area Shipment Trends

Millions of Square Inches

2Q2015

1Q2016

2Q2016

1H2015

1H2016
Total

2,702

2,538

2,706

5,339

5,243

*Shipments are for semiconductor applications only and do not include solar applications

Silicon wafers are the fundamental building material for semiconductors, which in turn, are vital components of virtually all electronics goods, including computers, telecommunications products, and consumer electronics. The highly engineered thin round disks are produced in various diameters (from one inch to 12 inches) and serve as the substrate material on which most semiconductor devices or “chips” are fabricated.

All data cited in this release is inclusive of polished silicon wafers, including virgin test wafers and epitaxial silicon wafers, as well as non-polished silicon wafers shipped by the wafer manufacturers to the end-users.

The Silicon Manufacturers Group acts as an independent special interest group within the SEMI structure and is open to SEMI members involved in manufacturing polycrystalline silicon, monocrystalline silicon or silicon wafers (e.g., as cut, polished, epi, etc.). The purpose of the group is to facilitate collective efforts on issues related to the silicon industry including the development of market information and statistics about the silicon industry and the semiconductor market.

Smaller and faster has been the trend for electronic devices since the inception of the computer chip, but flat transistors have gotten about as small as physically possible. For researchers pushing for even faster speeds and higher performance, the only way to go is up.

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

An array fin transistors made by the MacEtch method. The fins are tall and thin, with a higher aspect ratio and smoother sides than other methods can produce. Credit: Yi Song, University of Illinois

University of Illinois researchers have developed a way to etch very tall, narrow finFETs, a type of transistor that forms a tall semiconductor “fin” for the current to travel over. The etching technique addresses many problems in trying to create 3-D devices, typically done now by stacking layers or carving out structures from a thicker semiconductor wafer.

“We are exploring the electronic device roadmap beyond silicon,” said Xiuling Li, a U. of I. professor of electrical and computer engineering and the leader of the study. “With this technology, we are pushing the limit of the vertical space, so we can put more transistors on a chip and get faster speeds. We are making the structures very tall and smooth, with aspect ratios that are impossible for other existing methods to reach, and using a material with better performance than silicon.”

The team published the results in the journal Electron Device Letters.

Typically, finFETs are made by bombarding a semiconductor wafer with beams of high-energy ions. This technique has a number of challenges, Li said. For one, the sides of the fins are sloped instead of straight up and down, making them look more like tiny mountain ranges than fins. This shape means that only the tops of the fins can perform reliably. But an even bigger problem for high-performance applications is how the ion beam damages the surface of the semiconductor, which can lead to current leakage.

The Illinois technique, called metal-assisted chemical etching or MacEtch, is a liquid-based method, which is simpler and lower-cost than using ion beams, Li said. A metal template is applied to the surface, then a chemical bath etches away the areas around the template, leaving the sides of the fins vertical and smooth.

“We use a MacEtch technique that gives a much higher aspect ratio, and the sidewalls are nearly 90 degrees, so we can use the whole volume as the conducting channel,” said graduate student Yi Song, the first author of the paper. “One very tall fin channel can achieve the same conduction as several short fin channels, so we save a lot of area by improving the aspect ratio.”

The smoothness of the sides is important, since the semiconductor fins must be overlaid with insulators and metals that touch the tiny wires that interconnect the transistors on a chip. To have consistently high performance, the interface between the semiconductor and the insulator needs to be smooth and even, Song said.

Right now, the researchers use the compound semiconductor indium phosphide with gold as the metal template. However, they are working to develop a MacEtch method that does not use gold, which is incompatible with silicon.

“Compound semiconductors are the future beyond silicon, but silicon is still the industry standard. So it is important to make it compatible with silicon and existing manufacturing processes,” Li said.

The researchers said the MacEtch technique could apply to many types of devices or applications that use 3-D semiconductor structures, such as computing memory, batteries, solar cells and LEDs.

Peregrine Semiconductor Corp. today announced the promotion of Takaki Murata to vice president and general manager of the high performance analog (HPA) business unit.

“Peregrine Semiconductor was acquired by Murata in December of 2014, and they have proven to be a powerful and supportive parent company,” says Jim Cable, CEO of Peregrine Semiconductor. “Takaki has been preparing for this promotion for the last year and a half, as he served on the executive staff of our HPA business. The timing of this promotion reflects the success of our integration and the logical next step to further our assimilation into the Murata family of companies.”

A long-time veteran of Murata, Takaki has a Ph.D. in electrical engineering and 12 years of experience at Murata, in a range of different assignments including: LTCC material development, SAW filter development, antenna sales engineering, RF front-end sales engineering, corporate accounting and inductor business strategic planning. Most recently, Takaki served as the vice president of business development inside HPA. He has been in that role since early 2015.

“I am so impressed with the quality of engineering talent here at the HPA business unit of Peregrine,” says Takaki Murata, now vice president and general manager of the Peregrine HPA business unit. “When you add that talented pool of engineers to the uniqueness of the Peregrine UltraCMOS® platform and recent advances in the power management market to the wide support of an industry giant, like Murata, you have an unstoppable force. I look forward to facilitating many more successful collaborations in the very near future.”

“Murata is looking to Peregrine to provide semiconductor innovation to be applied to the Murata advantage in our growth markets of power, automotive, healthcare and 5G,” says Norio Nakajima, EVP communication and sensor business unit, and energy business group of Murata Manufacturing Co. “We have heavily invested in Peregrine because we see their technological advantage as critical to many of our new and growth initiatives. We believe that Takaki is ideally suited to his new position because of his technological expertise and his deep and long history with Murata Manufacturing.”

Since the purchase by Murata in December 2014, Peregrine Semiconductor has increased their employee base by 40 percent. Jim Cable adds, “The continued investment in Peregrine by Murata is an indicator of the significance that it places on our technology and innovation.”

The HPA business unit of Peregrine Semiconductor serves more than over 4,000 global customers in end markets ranging from wireless infrastructure and wired broadband to test & measurement (T&M), automotive and aerospace. Most recently, it launched its first product into the power/energy marketplace.  Products include RF switches, digital step attenuators (DSAs), digitally tunable capacitors (DTCs), tuning control switches, power limiters, phase-locked loops (PLLs), mixers, prescalers, DC-DC converters, monolithic phase and amplitude controllers (MPACs) and the fastest GaN FET driver available today.

A*STAR’s Institute of Microelectronics (IME) has launched two consortia on advanced packaging, the Silicon Photonics Packaging consortium (Phase II) and the MEMS Wafer Level Chip Scale Packaging (WLCSP) consortium. They will develop novel solutions in the heterogeneous integration of micro-electromechanical systems (MEMS) and silicon photonics devices, which will boost overall performance and drive down production costs. The new consortia will leverage on IME’s expertise in MEMS design, fabrication, wafer level packaging process, as well as silicon photonics packaging modules and processes.

The proliferation of the Internet of Things (IoT) is driving the rapid growth of diversified technologies which are key enablers in major application domains such as smart phones, tablets, wearable technology; and network infrastructures that support wireless communications.

However, this trend requires the complex integration of non-digital functions of “More-than-Moore” technologies such as MEMS with digital components into compact systems that have a smaller form factor, higher power efficiency and cost less. The onset of big data, cloud computing and high speed broadband wireless communications also calls for novel use of silicon photonics. Silicon photonics are a critical enabler of high density interconnects and high bandwidth, to meet high optical network requirements cost-effectively.

In the previous Silicon Photonics Packaging Consortium (Phase I), IME and its industry partners developed new capabilities in necessary device library and associated tool boxes to enable the integration of low profile lateral fiber assembly, laser diode and photonics devices. By employing a laser welding technique, the consortium demonstrated a fiber-chip-fiber loss of less than 8 decibel (dB) with less than 1.5dB excess packaging loss. These capabilities enabled integrated silicon photonic circuits to provide higher data rates at lower cost and power consumption. For details, please refer to Annex A.

Building on these achievements, the Silicon Photonics Packaging Consortium (Phase II) will develop a broad spectrum of silicon photonics packaging methodology. The consortium will further develop low loss silicon coupling modules, and provide a series of packaging solutions for laser diode integration. It will also focus on developing accurate thermal models, as well as improve overall module thermal management, reliability and radio-frequency (RF) performance to meet very high data bandwidth demand. All these new developments will lead to a more integrated packaging solution which promises better assembly margins and lower module costs.

IME’s MEMS WLCSP Consortium has also been established to develop a cost- effective integration packaging platform for capped MEMS and complementary metal-oxide semiconductor (CMOS) devices. This platform could be used for any MEMS devices with cavity-capping such as timing devices, inertial sensors, and RF MEMS packaging.

Conventional chip stacking that relies on a through-silicon via (TSV) and wire bonding on substrate method will usually result in high costs and large form factor. The consortium aims to lower production costs and achieve smaller footprint by developing a TSV-free over-mold wafer level packaging solution for MEMS-capped wafer using a novel metal deposited silicon pillar and wire bonding as a through mold interconnects.

The consortium aims to reduce form factor of integrated MEMS and CMOS devices by approximately 20 per cent, and lower manufacturing costs by approximately 15 per cent. These cost-effective packaging solutions are also expected to produce better electrical and reliability performance.

“These consortia partnerships play a critical role in developing innovative solutions to meet emerging market demands. Through these collaborations, we will elevate our capabilities from developing MEMS and silicon photonics devices to developing advanced solutions in heterogeneous integration. The capabilities developed will enable our industry partners to capture new growth opportunities in the IoT space and accelerate market adoption of cost-effective technologies,” said Prof. Dim-Lee Kwong, Executive Director of IME.

“Silicon photonics packaging is a crucial technology for the commercialisation of silicon photonic devices. The partnership generated remarkable results in the Silicon Photonics Packaging Consortium Phase I, and we are pleased to continue with the second phase, which will expand the application of silicon photonics with innovative approaches in terms of LD integration and RF performance. Through this consortium, Fujikura will accelerate the development of compact and cost-effective optical communications for diverse markets,” said Mr. Kenji Nishide, Executive Officer, General Manager, Advanced Technology Laboratory, Fujikura Ltd.

“Currently, it is anticipated that the demand for sensors will grow from billions to trillions by 2050. This demand is being driven by the emergence of sensor based smart systems fusing computing, connectivity and sensing in the context of the Internet of Things. IME’s packaging consortia partnership will allow us to identify and develop MEMS packaging innovative solutions in order to scale up for the Internet of Things,” said Mr. Mo Maghsoudnia, Vice President of Technology and Worldwide Manufacturing of InvenSense.

Mr. Shim Il Kwon, Chief Technology Officer, STATS ChipPAC said, “As the number of MEMS devices in emerging IoT applications continues to grow, semiconductor packaging will have a significant impact on the performance, size and cost targets that can be achieved. By collaborating with partners in the consortia, we will be able to help drive the cost effective integration of MEMS and ASICs in high performance, high yield WLCSP solutions for IoT products.”