Yearly Archives: 2016

Nano-electronics research center imec and Synopsys, Inc. (NASDAQ: SNPS) today announced an interconnect resistivity model to support the screening and selection of alternative interconnect metals and liner-barrier materials at the 7nm node and beyond. With the continued scaling of advanced process nodes, the impact of parasitic interconnect resistance on the switching delay of standard cells rises considerably. The new model developed through this collaboration enables the evaluation of interconnect material and process options through simulations in the early stages of technology development, when wafer data is not available, and in the process optimization and integration stages of technology development, where it reduces expensive and time-consuming wafer-based iterations.

“We have already released to our partners a number of sets of model parameters related to various liner/barrier systems for Cu metallization or to alternative metals, such as Ru and Co, which they will use to screen metallization options for next-generation interconnect technologies,” stated Dan Mocuta, director, Logic Device and Integration at imec.

To use the new resistivity model, customers simulate the fabrication of the interconnect structure in 3D using the Synopsys process emulation tool Process Explorer, and then simulate the wire and via resistance in Raphael, the Synopsys gold standard interconnect field solver. This simulation flow accounts for the impact of layout rules, multi-patterning flows, and process-induced 3D features on the resistance of any conductive net in a multilayer interconnect stack, thereby predicting the influence of material, process and patterning choices on the interconnect resistance at scaled dimensions.

Imec has calibrated the resistivity model to wafer data for Cu, W, Ru and Co interconnects.

“The new resistivity model developed through this collaboration with imec is an important component of our pre-wafer simulation solution to enable our mutual customers to perform early screening of interconnect technology options at advanced nodes,” said Dr. Howard Ko, senior vice president and general manager of the Silicon Engineering Group at Synopsys.

Imec’s research into advanced logic scaling is performed in cooperation with imec’s key partners in its core CMOS programs including GlobalFoundries, Intel, Micron, SK Hynix, Samsung, TSMC, Huawei, Qualcomm and Sony.

imec synopsys 1 imec synopsys 2

3D model of a multilayer interconnect stack (a) after process emulations using the Synopsys Sentaurus™ Process Explorer and 3D local resistivity profile (b) within wires and vias

Rudolph Technologies, Inc. (NYSE: RTEC) today unveiled its new patented Clearfind technology, which can detect organic defects that are difficult or impossible to see with conventional white-light imaging techniques. Organic contaminants are often the root cause of field failures, which occur after the material has been exposed to operating conditions for extended periods. Rudolph has been actively collaborating with several key customers to fully understand their inspection challenges and how the new technology addresses them, and plans to incorporate Clearfind technology in its upcoming defect inspection systems for advanced packaging applications.

“As advanced packaging processes become more complex, process windows are shrinking and manufacturers are seeking better methods for control and inspection that balance the need for high throughput against the ‘escape’ of true defects and the ‘false positive’ detection of nuisance defects,” said Mike Goodrich, vice president and general manager of Rudolph’s Process Control Group. “Organic defects, in particular, have become more troublesome as die interconnects shrink and there is less surface area for good adhesion. Clearfind technology will help our customers see these defects earlier in the process, permitting faster action to mitigate the root cause and reducing the amount of product in jeopardy.”

Goodrich continued, “Using laser illumination we are able to clearly identify residue defects that typical white-light optics would miss. In addition to optimizing the wavelength of the illumination to enhance detection, we have specifically designed the mechanics of the system to accommodate the high warpage found in advanced packaging applications.”

Clearfind technology highlights organic residues on bumps and bond pads or at the bottoms of vias so that they are easy to detect. On metals, it eliminates the high-contrast graininess seen under conventional illumination, resulting in an obvious defect signal against a featureless background. This same graininess in conventional imaging can also cause false positives, which are especially costly at this stage of the process where the sunk cost of unnecessarily rejected good product is high. Finally, Clearfind technology readily detects shorts and opens in metal lines when inspected with an underlying organic layer. Rudolph believes these capabilities will significantly increase its customer’s ability to detect process and manufacturing related issues earlier in the process resulting in significant yield, which equates to millions of dollars in savings, especially for processes utilizing known-good die. Rudolph’s customers see this as a critical technology to improve quality for their customers in order to avoid the high costs of replacement and penalties.

For more information about the new Clearfind technology, please visit Rudolph at SEMICON West, booth 6543, in the North Hall.

clearfind-images-final

Applied Micro Circuits Corporation (NASDAQ:AMCC) today announced that it has adopted 7nm process technology from TSMC, a world-leading foundry, to enable AppliedMicro’s silicon products for cloud computing and networking applications.

“We are excited to extend our relationship with TSMC to ultimately bring cutting-edge technology to the cloud computing market,” said Paramesh Gopi, President and CEO of AppliedMicro. “We will work closely with TSMC to ensure our flagship silicon products benefit from their manufacturing excellence that is renowned throughout the industry. Together we will introduce technology to revolutionize the rapidly growing data-center market to deliver an unprecedented bundle of compute and connectivity performance, energy efficiency and bandwidth utilization at a low total cost of ownership.”

“We are pleased to be a part of AppliedMicro’s success,” said Dr. B.J. Woo, TSMC Vice President of Business Development. “TSMC’s advanced 7nm technology will empower AppliedMicro to deliver the critical performance needed in computing and connectivity applications.”

Recently introduced innovations from AppliedMicro include X-Gene 3 at ARM TechCon in November 2015, and single lambda, mixed signal 100G X-Weave PAM4 at the Optical Fiber Communications Conference in March 2016.  Both product functions were validated  with TSMC 16FF+ shuttle and are expected to sample to customers by early 2017.

EV Group (EVG), a supplier of wafer bonding and lithography equipment for the MEMS, nanotechnology and semiconductor markets, today introduced the EVG50 automated metrology system. Designed to support the increasingly stringent manufacturing requirements for advanced packaging, MEMS and photonics applications, the EVG50 performs high-resolution non-destructive multi-layer thickness and topography measurement, as well as void detection, in bonded wafer stacks and in photoresists used in optical lithography. The system measures layers down to two microns in thickness, can inspect up to one million points, and achieves throughputs of up to 55 300-mm wafers per hour. This combination of extremely high resolution and high throughput provides cost-efficient full-wafer inspection that enables device manufacturers to improve their wafer bonding and lithography processes, as well as achieve higher yields.

The EVG 50 Automated Metrology System from EV Group performs high-throughput, high-resolution measurements of critical wafer bonding and lithography process parameters.

The EVG 50 Automated Metrology System from EV Group performs high-throughput, high-resolution measurements of critical wafer bonding and lithography process parameters.

Dr. Thomas Glinsner, corporate technology director at EV Group, noted, “The semiconductor industry is witnessing a trend toward total control and monitoring of all production processes. Mid-end-of-line and back-end packaging processes face tighter process constraints at levels previously seen only in front-end-of-line wafer processing. This is creating an urgent need for highly accurate in-line metrology that can provide critical process data quickly and cost-effectively. The EVG50 is an important addition to our suite of metrology solutions that achieves these goals at speeds and resolutions that far surpass those of competitive systems.”

Building on a legacy of widely adopted metrology solutions

The standalone EVG50 system was developed based on the company’s existing in-line metrology module (IMM), which is available as an option in EVG’s line of 300-mm process equipment and has been widely implemented in high-volume manufacturing. The EVG50 complements the company’s versatile EVG40NT measurement system, which is the industry standard for bond overlay inspection, to meet increased customer demand for full-area layer thickness and topography measurement in critical applications. The EVG50’s high throughput and unparalleled accuracy and repeatability, even at ultra-high resolutions, enables cost-effective, 100-percent inspection of production wafers, resulting in improved process control.

The EVG50’s versatility allows it to measure coating thickness for lithography as well as wafer bow and warpage, and make void inspections for a bonded wafer stack on the same system, while its low-contact edge handling enables particle-free, full-area wafer inspection. Another key benefit of the EVG50 is its flexibility. Leveraging a multi-sensor measurement mount, the system can be customized for different thickness ranges and substrates to address a wide variety of customer requirements. Its self-calibration capability also allows for better system reproducibility and productive uptime.

Media, analysts and potential customers interested in learning more about EVG’s suite of metrology solutions, including the EVG50, are invited to visit the company’s booth #1017 in the South Hall of the Moscone Convention Center in San Francisco, Calif., at the SEMICON West show on July 12-14.

Applied Materials, Inc. today announced its next-generation e-beam inspection system is delivering the highest resolution and image quality at the fastest throughput to leading foundry, logic, DRAM and 3D NAND customers as they move to advanced nodes.

The Applied PROVision– system is the industry’s most advanced e-beam inspection tool, incorporating innovations based on more than 20 years of leading expertise in e-beam technology for review and metrology. It is the only e-beam hotspot inspection tool offering down to 1nm resolution, allowing customers to detect the most challenging “killer” defects that other technologies cannot find, and to monitor process marginality to rapidly resolve ramp issues and achieve higher yields.

“The PROVision system is the latest addition to our e-beam portfolio, and is a key part of Applied’s growth strategy,” said Bob Perlmutter, vice president and general manager of Applied’s Imaging and Process Control Group. “Our differentiated e-beam column technology is the best in the industry and when coupled with our customers’ new inspection methodologies, enables the PROVision system to go beyond R&D use and into production environments.”

The PROVision system is gaining momentum with already more than a dozen shipments, including repeat orders from a leading foundry and a major memory manufacturer. Additional systems are scheduled for shipment to existing and new customers in the second half of 2016.

“The PROVision system’s unique combination of high resolution and massive sampling has helped accelerate time to solution and time to market for our advanced nodes,” said Dr. Oh-Jang Kwon, SK hynix R&D EBI Group.

Offering 3x faster throughput over existing e-beam hotspot inspection tools, the PROVision system ensures accurate process characterization, prediction and detection of performance- and yield-limiting defects throughout the fab product life cycle. The PROVision system complements Applied’s e-beam metrology and review products as well as the optical patterned wafer inspection product line.

071116 Applied PROVision system

3D-Micromac AG, a supplier of laser micromachining and roll-to-roll laser systems for the photovoltaic, medical device and electronics markets, announced that its microDICE laser micromachining system has been adopted by a major industrial manufacturer for volume production of high-power diodes. Leveraging 3D-Micromac’s proprietary TLS-Dicing technology, the microDICE system provides fast, clean and cost-effective dicing of wafers used for advanced semiconductors and power device applications. Its unique approach uses thermally induced mechanical stress to separate brittle semiconductor materials such as silicon, silicon carbide (SiC), germanium (Ge) and gallium arsenide (GaAs).

3d micromac

The microDICE laser micromachining system from 3D-Micromac supports volume production of high-power diodes.

TLS-Dicing is a contact- and residue-free process that provides significantly higher throughput, higher yields and greater functionality compared to traditional die-separation technologies. For example, throughput is up to 30X greater compared to saw dicing. The technology also provides lower cost of ownership than other approaches. A forceless and contactless machining process, TLS-Dicing eliminates tool wear and requires no expensive consumables for surface cleaning–resulting in cost savings of up to an order of magnitude or more.

“While significant time and resources are invested in the front-end of semiconductor manufacturing to produce a completed product wafer, back-end wafer processing has historically been viewed as a necessary evil,” stated Tino Petsch, CEO of 3D-Micromac. “That’s all changed with the adoption of new types of wafer substrates, thinner wafers and scaling to smaller dimensions, larger-size substrates, and new packaging technologies like 3D-stacking. Back-end process steps such as wafer dicing are evolving as critical value-add process steps that not only ensure, but also further enhance, device yields. Using our TLS-Dicing technology, the microDICE system provides superior wafer dicing performance over other approaches while considerably reducing the dicing cost per wafer. Our technology has been proven in the photovoltaic and other industrial markets, and we are pleased to bring the benefits of it to the semiconductor and power device manufacturing industry.”

3D-Micromac also announced today that it is expanding its global infrastructure with the opening of its new 3D-Micromac America headquarters in the heart of Silicon Valley, in San Jose, Calif. Serving as both an applications lab and sales and support facility, the office marks the company’s first major presence in North America and will enable 3D-Micromac to better meet rising customer demand for its laser micromachining products across all of its served markets, including solar, semiconductor, MEMS, display and smart glass.

According to Daniel Weber, sales and business development manager for 3D-Micromac America, “With our new regional headquarters and applications lab, 3D-Micromac can offer our North American-based customers a first-class network of sales and support services for our laser micromachining systems. Providing customer evaluations, applications development, and small-scale contract manufacturing is a unique offering among wafer dicing technology suppliers. We look forward to delivering all of these capabilities to our existing, new and potential customers.”

Photoresist manufacturers had reason to smile as fiscal 2015 closed, with sales growing nicely to $1.37B, a 6.2% increase over 2014. That bump has to sustain them through 2020, according to a new report from Techcet Group, “Critical Materials Report: Photoresists and Extensions and Ancillaries 2016.” Total volumes for photoresist and extension materials continue to grow with wafer starts, although revenues are expected to hover around $1.4B for the next 4 years. Growth from wafer starts in partially offset by reductions in photoresist thicknesses for critical layers in leading edge devices.

Virtually all of the growth in lithography materials can be attributed to volume growth in advanced nodes. While the 5 year CAGR outlook for silicon wafer starts is -2% for the 45nm node and larger, that same outlook is +10% for the 28nm node and smaller. ArF (193nm wavelength) resists already comprise over 40% of the total market. Extreme ultra-violent lithography (EUVL @ ~13nm wavelength) remains in the forecast for 2020, but it will be limited to mix-and-match implementation at the 10nm node due to its premium cost and low throughput. Nano-Imprint Lithography (NIL) is in limited use by one Asian memory fab. Multi-patterning with 193nm immersion will remain the workhorse for all leading edge IC fabs.

The category of resolution “extension” materials to enable finer feature patterning grows out of the segment for bottom anti-reflection coatings (BARC) and spin-on hard-masks (HM), which can be combined with a top layer of photoresist in a so-called “Tri-Layer Resist” (TLR) approach. Extensions also include specialty chemical formations to “trim” lines by removing photoresist material, or to “shrink” holes by adding material to sidewalls. The extension materials market is now the fastest growing segment, already at $650M in 2015 it is forecast to reach $790M by 2020, as detailed in TECHCET’s Report.

The photoresist ancillary segment that includes strippers/removers, developers, edge-bead removers (EBR) and specialty solvents is expected to suffer a slow decline from today’s $600M to $575M by 2020, primarily due to volume reductions associated with thinner photoresists. Also, ancillaries are generally sourced in large quantities from local suppliers, and regional pricing pressures further depress revenues in this sub-market.

There are six major suppliers controlling 90% of the global resist market, with a total of eleven key manufacturers offering standard and advanced photoresist products and critical ancillaries. JSR and TOK share 53% of the market, with others at 12% or less. In addition to market analysis, critical supply chain issues and technical trends, the report includes profiles and updates for major suppliers of photoresist and related materials to the global semiconductor industry.

Imec, a nanoelectronics research center, today announced the opening of imec Florida, a new entity focusing on photonics and high-speed electronics IC design based in Osceola, Florida. Imec Florida kicked off with the signing of a collaboration agreement with the University of Central Florida (UCF), Osceola County and the International Consortium for Advanced Manufacturing Research (ICAMR), that is setting up fab facilities for the development and production of highly innovative III-V-on-silicon solutions for a broad range of applications including sensors, high-speed electronics and photonics.

Imec Florida will be established as a design center facilitating the collaboration between imec’s headquarters, based in Leuven, Belgium, and U.S.-based semiconductor and system companies, universities, and research institutes. Imec Florida’s initial focus will be the R&D of high speed electronics and photonics solutions, starting with an offering of IC design research for a broad set of semiconductor-based solutions such as THz and LIDAR sensors, imagers, and a broad range of sensors.  It will also provide IC design needs that will be driving the ICAMR manufacturing research. Through imec Florida, imec’s design, prototyping and low-volume production service – also named imec IC-link – will provide the US market low-cost access to advanced foundry services, helping entrepreneurs to (industry and academia) design innovative products and get them to market.

Funding for imec Florida will come from Osceola County, and the University of Central Florida. The new center will attract top talent through future strategic partnerships, with the aim to employ about 10 scientists and engineers by the end of the year and increase to 100 researchers in the next five years. Heading up the facility as General Manager will be imec’s Vice President Bert Gyselinckx who previously served as general manager at imec in Eindhoven, the Netherlands and helped to co-invent many technologies deployed by innovative semiconductor and consumer electronics companies.

“As the U.S. semiconductor market continues to strengthen with semiconductor manufacturing, equipment, materials and system innovation, we are extremely pleased to collaborate with partner organizations in Florida and see Osceola County in the Orlando region as an interesting location to drive the next phase of imec’s growth and innovation,” stated Luc Van den hove, president and CEO of imec. “Together with industrial and academic partners, we want to develop sustainable solutions and technology to accelerate innovation and stimulate economic growth within Osceola County and the State of Florida.”

“Imec’s international prestige gives us the opportunity to leverage its standing in a field that is growing exponentially in order to recruit more partners and funding for our work at the new Design Center and the Florida Advanced Manufacturing Research Center,” said Osceola County Commission Chairwoman Viviana Janer. “The relationships and people that imec brings to our operation are tangible ways that Osceola County’s 5-year, $15 million investment will be more than re-paid. It’s important to realize that the new Design Center is going to capture the attention of everyone in this field, thereby ensuring maximum utilization and value of the FAMRC.”

“The imec Design Center is the funnel that will fill ICAMR with high-value manufacturing opportunities and we will work closely with them to make sure our capabilities tightly align with their technology direction, said ICAMR CEO Chester Kennedy.  “This partnership is poised to shine the global high-tech spotlight on Central Florida.”

On July 11, 2016, imec will introduce imec Florida to the semiconductor industry at its annual Imec Technology Forum (ITF) USA, a half-day conference in San Francisco Calif., at the Marriott Marquis. ITF USA is part of imec’s prestigious worldwide ITF events, organized in conjunction with SEMICON West and supported by SEMI. With the theme ‘Towards the Ultimate System’, imec’s highly acclaimed speakers and industrial keynote speakers will look at the co-optimization of design and new technology, and how technology innovation can deliver the right building blocks to build these systems.

The health of the semiconductor industry is increasingly tied to the health of the worldwide economy. Rarely can there be strong semiconductor market growth without at least “good” worldwide economic growth to support it. Consequently, IC Insights expects annual global semiconductor market growth rates to continue to closely track the performance of worldwide GDP growth (Figure 1).  In its upcoming Mid-Year Update to The McClean Report 2016 (to be released at the end of July), IC Insights forecasts 2016 global GDP growth of only 2.3%, which is below the 2.5% level that is considered to be the global recession threshold.

Figure 1

Figure 1

In many areas of the world, local economies have slowed.  China, which is the leading market for personal computers, digital TVs, smartphones, new commercial aircraft, and automobiles, is forecast to continue to lose economic momentum in 2016.  Its GDP is forecast to increase 6.6% this year, which continues a slide in that country’s annual GDP growth rate that started in 2010 when growth rates exceeded 10%.

IC Insights believes that the worldwide economy will be negatively impacted, at least over the next year or two, by the Brexit vote this past June.  At this point, since the U.K. is unlikely to officially be able to leave the European Union (EU) for a couple of years, the biggest negative effect on economic growth is the uncertainty of the entire situation.  Some of the uncertainty created by the vote includes:

•    Whether the U.K. will actually leave the EU.  Since the Brexit vote is not legally binding, and still needs to be approved by the U.K. government, there is uncertainty if its departure from the EU will actually happen.

•    Whether the U.K. will come apart itself.  There are rumblings about Scotland breaking away from being a part of the U.K. in order for it to remain as part of the EU.

•    What trade deals will be made by the U.K. if it does leave the EU?  As part of its exit from the EU, the U.K. will need to establish numerous new trade deals with the EU.  There is tremendous uncertainty regarding whether these deals would have a positive or negative effect on the U.K. economy.

•    Will other countries follow the U.K. and depart from the EU?  Anxiety persists over whether the EU will fall apart as other countries attempt their own exit.  Some countries mentioned as possibly following the U.K. out of the EU include the Netherlands (Nexit), France (Frexit), Italy, Austria, and Sweden (Swexit).

The other major “culprit” dragging down semiconductor industry growth this year is the very weak DRAM market.  At $45.0 billion, the DRAM market was the largest single product category in the semiconductor industry in 2015.  IC Insights forecasts that the DRAM market will register a 19% drop of $8.5 billion this year to $36.5 billion.  The DRAM market alone is forecast to shave three percentage points off of total semiconductor market growth this year. Semiconductor market growth excluding DRAM is forecast to be +2%.

Most of the DRAM market decline expected for this year is due to a rapid decline in DRAM pricing over the past 18 months.  For 2016, the average price for a DRAM device is forecast to drop to $2.55, a steep 16% decline as compared to 2015’s DRAM ASP of $3.03. Further trends and analysis relating to semiconductor market forecasts through 2020 will be covered in the 250-plus-page Mid-Year Update to the 2016 edition of The McClean Report.

Gigaphoton Inc., a manufacturer of light sources used in lithography, has announced success in achieving 250W light output at 4.0% conversion efficiency with a Laser-Produced Plasma (LPP) light source prototype for EUV scanners, which the company is currently engaged in developing. At this output level, the light sources can be used in high-volume manufacturing of state-of-the-art semiconductors. The company also announced its success in achieving 119 hours of continuous operation at over 130W in testing.

This result was achieved via the culmination of a number of efforts that the company has continued to develop, including the sub 20 μm micro droplet supply technology, the combination of solid state pre-pulse and CO2 main pulse lasers, improvements in energy control technology, and magnetic field enabled debris mitigation technology.

Gigaphoton has also launched operation of a high-power EUV light source verifier designed for use in a semiconductor high-volume manufacturing environment, and is committed to continuing the development of EUV light sources with high operational rates and reliability in an aim to facilitate their implementation in the high-volume manufacturing of semiconductors.

Hakaru Mizoguchi, Vice President and CTO of Gigaphoton says, “Our success in achieving 250W output at 4.0% conversion efficiency serves to demonstrate how very close we are to perfecting an EUV light source that will achieve the high output rates, while delivering stable operation at low running costs, which the semiconductor manufacturers have long waited for. We are confident that Gigaphoton’s advanced technological capabilities and development efforts aimed at high-volume manufacturing will ultimately produce ground breaking results by accelerating the development of EUV scanners for mass production, expediting the implementation of EUV scanners as the next generation of technology in lithography, contributing to overall development of the semiconductor industry, and accelerating the realization of an IoT based society.

*This project utilizes results from the New Energy and Industrial Technology Development Organization (NEDO) grant program.