Yearly Archives: 2017

The global mask alignment systems market is expected to grow at a CAGR of more than 9% during the forecast period, according to Technavio’s latest market research.

In this market research report, Technavio covers the market outlook and growth prospects of the global mask alignment systems market for 2017-2021. The market is further categorized based on application (microelectromechanical system (MEMS) devices, compound semiconductors, and LED devices) and end-user (foundry, memory, and integrated device manufacturer (IDM)).

APAC: largest mask alignment systems market

APAC has the presence of several prominent semiconductor foundries such as Taiwan Semiconductor Manufacturing Company (TSMC), Samsung, and SMIC. This has created demand for mask alignment systems in the region. The major revenue contributors to the mask alignment systems market in APAC are Taiwan, South Korea, and Japan. These countries contribute significantly to the market revenue as they are home to many leading semiconductor device manufacturers.

“In the APAC region, the presence of dominant players in the global consumer electronics and mobile devices markets such as Samsung, Sony, LG Electronics, Toshiba, and Panasonic is supporting the demand for semiconductor devices that include lithography equipment such as mask alignment systems. Furthermore, the major chip vendors in the region are investing in infrastructure development such as the construction of new fabs to increase the throughput,” says Rohan Joy Thomas, a lead semiconductor equipment research expert from Technavio.

Mask alignment systems market in EMEA

In EMEA, the demand for mask alignment systems comes mainly from companies such as Infineon Technologies, NXP Semiconductors, and STMicroelectronics. Germany and the UK are the major revenue contributors to the mask alignment systems market in EMEA due to the presence of several prominent automobile manufacturers such as AUDI, BMW, Daimler (Mercedes-Benz), and Volkswagen.

“The increased focus on safety, passenger comfort, and engine efficiency require more number of ICs and the fabrication of these ICs will need more semiconductor equipment, including mask alignment systems. This will fuel the growth of the mask alignment systems market in EMEA during the forecast period,” says Rohan.

Mask alignment systems market in the Americas

The Americas has a comparatively lower share than the other two regions. But, the Americas can expect some changes in its market share during the forecast period. Several prominent semiconductor vendors are headquartered in this region, even though their manufacturing facilities are in APAC (due to the cost-effectiveness of production in APAC). The governing authorities of the Americas are promising special packages in the form of subsidies and incentives to encourage manufacturers to bring back their production facilities to the Americas. The American Recovery and Reinvestment Act is an example of such initiatives.

The presence of prominent semiconductor manufacturers such as Global Foundries and Intel will create demand for lithography systems such as mask alignment systems during the forecast period. In addition, the region boasts of a few major car manufacturers that are looking to integrate semiconductor devices and components into their products. This will also create demand for semiconductor production equipment such as mask alignment systems from the region during the forecast period

The top vendors in the global mask alignment systems market as highlighted in this market research analysis are:

  • EV Group
  • Neutronix
  • SUSS Microtek

 

Qualcomm Incorporated (NASDAQ: QCOM) (“Qualcomm” or the “Company”) today announced that the Qualcomm Board of Directors, following the recommendation of the Board’s Governance Committee, has unanimously determined not to nominate any of the 11 candidates assembled by Broadcom Limited (NASDAQ: AVGO) and Silver Lake Partners to replace Qualcomm’s current directors at Qualcomm’s 2018 Annual Meeting of Stockholders.  Qualcomm today also filed its preliminary proxy statement with the U.S. Securities and Exchange Commission in connection with Qualcomm’s upcoming 2018 Annual Meeting.

After a thorough review of the Broadcom-Silver Lake nominees, the Governance Committee concluded that these nominees are inherently conflicted and would not bring incremental skills or expertise to the Qualcomm Board. Qualcomm’s Board is nominating its 11 incumbent directors for re-election at the 2018 Annual Meeting: Barbara T. Alexander, Jeffrey W. Henderson, Thomas W. Horton, Dr. Paul E. Jacobs, Ann M. Livermore, Harish Manwani, Mark D. McLaughlin, Steve Mollenkopf, Clark T. Randt, Jr., Dr. Francisco Ros and Anthony J. “Tony” Vinciquerra.

Qualcomm’s existing Board has a deep understanding of the global IP/licensing and semiconductor business and relevant adjacent industries, and has overseen the design and execution of Qualcomm’s strategy, including driving its leadership in mobile, IoT, automotive, edge computing and networking, as well as the coming transition to 5G. Qualcomm’s Board remains focused on driving profitable growth and maximizing value for all stockholders.

Broadcom and Silver Lake are asking Qualcomm stockholders to turn over control of their Company now to the hand-picked Broadcom-Silver Lake nominees based on a proposal that dramatically undervalues Qualcomm and is not actionable due to its significant regulatory uncertainty, which may not be resolved for 18 months, if ever, and lack of committed financing.  Broadcom has made no commitments to resolve the serious regulatory issues inherent in its proposal.

Qualcomm’s Board is committed to maintaining best-in-class corporate governance. Qualcomm directors are elected annually and 9 of the 11 directors are independent, including 4 directors added in the last 3 years.  The incumbent directors have a mix of industry perspectives, operating and financial expertise, corporate restructuring experience and IP/licensing expertise, as well as a long history of collaborative stockholder engagement, all of which collectively drive performance and stockholder value.

Detailed information about Qualcomm’s director nominees is included in the Company’s preliminary proxy statement. Also included is a “Background to the Solicitation” section, which details all interactions between Qualcomm and Broadcom relating to Broadcom’s unsolicited acquisition proposal.

The use of LEDs to illuminate buildings and outdoor spaces reduced the total carbon dioxide (CO2) emissions of lighting by an estimated 570 million tons in 2017. This reduction is roughly equivalent to shutting down 162 coal-fired power plants, according to IHS Markit (Nasdaq: INFO), a world leader in critical information, analytics and solutions. LED lighting uses an average of 40 percent less power than fluorescents, and 80 percent less than incandescents, to produce the same amount of light.

“The efficiency of LEDs is essentially what makes them environmentally friendly,” said Jamie Fox, principal analyst, lighting and LEDs group, IHS Markit. “Therefore, LED conversion is unlike other measures, which require people to reduce consumption or make lifestyle changes.”

LED component and lighting companies were responsible for reducing the global carbon (CO2e) footprint by an estimated 1.5 percent in 2017, and that number is likely to continue to grow as more LEDs are installed around the world.

LEDs have other positive environmental benefits, too. For example, LEDs have a longer life span than traditional bulbs and fewer are produced, so the emissions and pollution associated with the production, shipping, sale and disposal of the products is lowered. Secondly, unlike fluorescents, LEDs do not contain mercury. LEDs also decrease air pollution, since most electrical energy is still generated by burning fossil fuels. “While other activities affect climate change more than lighting does, it is still a very strong contribution from a single industry sector,” Fox said.

IHS Markit has tracked the market share for top LED component suppliers for many years. Based on an analysis of this data, Nichia can claim credit for having saved the most carbon overall — accounting for 10 percent of all LED lighting reduction achieved in 2017, which translates into 57 million tons of CO2 — about the same as 16 coal plants. Cree followed Nichia with 8 percent, while Lumileds, Seoul Semiconductor, MLS, Samsung and LG Innotek each have a share in the range of 4 percent to 7 percent.

Savings achieved by each company relate to the energy saved by the use of that company’s components while installed in lighting applications. It does not include a whole lifecycle analysis, which would likely lead to a small additional positive benefit, due to the longer life of LEDs.

“LED component companies and lighting companies have transformed their industry,” Fox said. “They are fighting climate change much more effectively than other industries, and they should be given credit for it. Unlike in other industry sectors, workers at LED companies can honestly say that by selling more of their products, they are helping to reduce global warming.”

IHS Markit figures are only based on the lighting market. They do not include energy saved by LEDs that replaced other technologies in other sectors, such as automotive and consumer technology.

The SEMI European 3D Summit will make its Dresden, Germany, debut  22-24 January, 2018, featuring a broader scope of 3D topics driving innovation and business opportunities in the 3D market. The event will highlight the latest 3D technologies including 3DIC Through-Silicon-Via (TSV), 2.5D, 3D FO-WLP/ e-WLB, glass interposers, thermal management and 3D alternative technologies for heterogeneous integration and high-density systems.

A market briefing on the latest business challenges and opportunities in the 3D sector will kick off the summit, with 3D and packaging industry experts presenting their exclusive business and market insights and analysis confirming the huge forecast growth of advanced packaging. Keynotes and presentations on the current adoption of 3D applications such as high-end memory, performance, mobile, imaging and automotive will highlight this 6th edition of SEMI European 3D Summit.

Sold-out for five years straight, the European 3D Summit will showcase the leading names in 3D integration microelectronics manufacturing and offer numerous networking opportunities including a gala dinner and cocktail hour, along with frequent coffee and lunch break mixers. In addition, attendees will meet emerging new talent engaged in the future of 3D integration including Sabrina Fadloun, PhD student and senior field process engineer, SPTS Technologies, and September 2017 winner of the international competition “My Thesis in 180 Seconds.”

The European 3D Summit will showcase speakers from companies such as Third Millennium Test Solutions (3MTS), Amkor Technology, CEA-Leti, Chipworks, Epcos, Fraunhofer, GLOBALFOUNDRIES, Hewlett Packard, Huawei, IBM, IMEC, Intel, ProPrincipia, Qualcomm, Silex, ST Microelectronics, SMIC, TechSearch, Tessera Xperi, Université de Sherbrooke, Western Digital, X-Fab and Yole Développement.

Featuring a huge supplier base, Dresden is home to some of Europe’s largest fabs, from GLOBALFOUNDRIES, Infineon, and X-FAB to a new 300mm BOSCH fab.

Premium Sponsors of the European 3D Summit are SPTS Technologies (platinum sponsor), ASE Group (gold sponsor), Suss MicroTec Group (silver sponsor), EV Group and Trymax (event sponsor)

Please find more registration information at www.semi.org/eu/European-3D-Summit-2018-Register. For more information on the show, please visit www.semi.org/eu/european-3d-summit-2018 or contact Mr. Michael Kaiser, Senior Manager Business Development, SEMI Europe (email: [email protected] or tel. +49 30 3030 8077 10).

United Microelectronics Corporation (NYSE:UMC;TWSE:2303) (“UMC”), a global semiconductor foundry, today announced the availability of the company’s 40nm process platform that incorporates Silicon Storage Technology’s (SST) embedded SuperFlash non-volatile memory. The newly available 40nm SST process features a >20% reduction in eFlash cell size and 20-30% macro area over UMC’s mass production 55nm SST technology. Toshiba Electronic Devices & Storage Corporation has started studying technical feasibility of UMC’s 40nm SST for their microcontroller (MCU) ICs.

“We expect that UMC’s 40nm SST will improve the performance of our MCU products,” said Toshiya Matsui, Vice President, Mixed Signal IC Division of Toshiba Electronic Devices & Storage Corporation “Working with UMC will also allow us to maintain a robust business continuity plan (BCP) through stable manufacturing supply and flexible capacity support based on our production requirements.”

More than 20 customers and products are in various stages of 55nm SST eFlash production at UMC, including those for SIM card, banking, automotive, IOT, MCU and other applications.

Wenchi Ting, Associate VP of Specialty Technology division at UMC said, “Since qualifying SST’s embedded flash technology on our popular 55nm process in 2015, we have received tremendous interest from customers looking to further utilize the low power, high reliability, superior data retention and high endurance characteristics of this process platform for their automotive, industrial, consumer and IoT applications. We are pleased to introduce this eNVM solution on our 40nm platform, and look forward to bringing the high speed and high reliability benefits of SST to Toshiba and our other foundry customers.”

UMC’s robust SST process performs according to JEDEC standards, with 100k endurance and more than 10 years of data retention at 85C and an operating-temperature range of -40C to 125C. In addition to the 40nm SST process, UMC has over 20 customers in production using the foundry’s 55nm SST for a broad range of product applications.

Researchers at the Center for Integrated Nanostructure Physics, within the Institute for Basic Science (IBS), have shown that defects in monolayer molybdenum disulfide (MoS2) exhibit electrical switching, providing new insights into the electrical properties of this material. As MoS2 is one of the most promising 2D semiconductors, it is expected that these results will contribute to its future use in opto-electronics.

The study on 2-D molybdenum disulfide (MoS2) defects employed low frequency noise measurements and conductive atomic force microscopy (C-AFM). The enlarged image shows an AFM cantilever tip pointing to an area with one sulfur monovacancy (area shaded red). As current flows through the AFM tip and the sample, switching events between different ionization states (neutral and charged -1) are measured. With a radius of around 25 nanometers, the AFM tip covers an area that contains around 1-8 sulfur monovacancies. Credit: IBS, published on Nature Communications

The study on 2-D molybdenum disulfide (MoS2) defects employed low frequency noise measurements and conductive atomic force microscopy (C-AFM). The enlarged image shows an AFM cantilever tip pointing to an area with one sulfur monovacancy (area shaded red). As current flows through the AFM tip and the sample, switching events between different ionization states (neutral and charged -1) are measured. With a radius of around 25 nanometers, the AFM tip covers an area that contains around 1-8 sulfur monovacancies. Credit: IBS, published on Nature Communications

Defects can cause major changes in the properties of a material, leading to either desirable or unwanted effects. For example, petrochemical industry has long taken advantage of the catalytic activity of MoS2edges, characterized by the presence of a high concentration of defects, to produce petroleum products with reduced sulfur dioxide (SO2) emissions. On the other hand, having a pristine material is a must in electronics. Currently, silicon rules the industry, because it can be prepared in a virtually defect-free manner. In the case of MoS2, its suitability for electronic applications is currently limited by the presence of naturally occurring defects. So far, the precise link between these defects and the degraded properties of MoS2 has been an open question.

In IBS, a team of physicists, material scientists, and electrical engineers worked closely together to explore the electronic properties of sulfur vacancies in MoS2 monolayers, using a combination of atomic force microscopy (AFM) and noise analysis. The scientists used a metallic AFM tip to measure the noise signal, i.e., the variation of electrical current passing through a single layer of MoS2 placed on a metal substrate.

The most common defects in MoS2 are instances of missing single sulfur atoms, also known as sulfur monovacancies. In a perfect sample, each sulfur atom has two valence electrons that bind to two molybdenum electrons. However, where a sulfur atom is missing, these two molybdenum electrons are left unsaturated, defining the neutral state (0 state) of the defect. However, the team observed rapid switching events in their noise measurements, indicating the state of the vacancy switched between neutral (0 state) and charged (-1 state).

“The switching between 0 and -1 is happening continuously. While an electron resides at the vacancy for a while, it is missing from the current, such that we observe a current drop,” explains Michael Neumann, one of the co-first authors of the study. “This goes a long way towards understanding the known anomalies of MoS2, and it is very interesting that sulfur vacancies alone are enough to explain these anomalies, without requiring more complex defects.” According to the experiments and earlier calculations, two electrons can be also trapped at the vacancy (-2 state), but this does not seem to be energetically favored.

The new observation that sulfur vacancies can be charged (-1 and -2 states) sheds light on several MoS2 anomalies, including its reduced electron mobility observed in MoS2 monolayer samples: electrons move following the direction of an applied voltage, but get scattered by charged defects. “The -1 state is occupied around 50% of the time, which would lead to scattering of electrons, and thus explain why MoS2 has such poor mobility,” clarifies Neumann. Other MoS2 characteristics which can be explained by this study are the n-type doping of MoS2, and the unexpectedly large resistance at the MoS2-metal junction.

“This research opens up the possibility of developing a new noise nanospectroscopy device capable of mapping one or more defects on a nanoscale scale over a wide area of a 2D material,” concludes the corresponding author Young Hee Lee.

The full study is available on Nature Communications.

By Natalie Shim, SEMI Korea

As dynamic back-end related technologies such as TSV (Through-Silicon Vias), InFO (Integrated Fan Out), etc., enable electronic devices to downsize with higher performance, the importance of back-end processing is greater than ever. Due to this, more and more customers are requesting “quality control” by tracing raw materials to assembly and packaging companies and the need for a standard is clear.

The Korea Advanced Back-end Factory Integration Task Force, in response to the industry’s demand, has decided to revise SEMI E142-0211 (Reapproved 1016), Specification for Substrate Mapping by adding an assembly and packaging raw materials traceability method.

Standards Chart

The first ballot is open for voting in Cycle 9-2017 (Nov 29 to Dec 29, 2017), and the TF will review the feedback at the next Information and Control Korea Technical Committee Chapter meeting scheduled for February 1, 2018, in conjunction with SEMICON Korea in Seoul, Korea.

Get Involved

SEMI Standards development activities take place throughout the year in all major manufacturing regions. To get involved, join the SEMI International Standards Program at: www.semi.org/standardsmembership.

For more information regarding Korea Advanced Back-end Factory Integration Task Force activities, please contact Natalie Shim at [email protected].

JEDEC Solid State Technology Association, a leader in standards development for the microelectronics industry, announces the successful launch of its newest committee: JC-70 Wide Bandgap Power Electronic Conversion Semiconductors. JC-70 held its first meeting in late October with twenty-three member companies, led by committee and subcommittee chairs from Infineon Technologies, Texas Instruments, Transphorm, and Wolfspeed, a Cree Company. Committee members include industry leaders in power GaN and SiC semiconductors as well as prospective users of WBG power semiconductors and T&M equipment manufacturers. Global multinational corporations and technology startups from the US, Europe, and Asia are working together to bring to the industry a set of standards for reliability, testing, and parametrics of WBG power semiconductors.

JC-70 has two subcommittees, which are focusing on Silicon Carbide (SiC) and Gallium Nitride (GaN) as the most mature wide bandgap (WBG) power semiconductor materials. Both SiC and GaN offer immense potential for enabling higher performance, more compact, and energy efficient power systems. Industry interest in JC-70 has been high with several new members joining the committee after the first meeting, underscoring the importance of creating universal standards to help advance the adoption of WBG power technologies.

“I am delighted by the initial response to the JC-70 committee, and look forward to welcoming additional companies to participate in developing standards for wide bandgap power technology,” said John Kelly, JEDEC President. “Broad industry participation will help ensure the resulting documents meet the needs of product designers as they create systems to enable a more energy efficient future.”

Four committee meetings are planned for 2018, including a webconference on January 25 and a meeting co-located with the APEC Conference on March 5. Interested companies worldwide are welcome to join JEDEC to participate in this important standardization effort.Contact Emily Desjardins ([email protected]) for more information or visit www.jedec.org.

Samsung Electronics Co., Ltd. announced today that it has begun mass producing the industry’s first 2nd-generation of 10-nanometer class (1y-nm), 8-gigabit (Gb) DDR4. For use in a wide range of next-generation computing systems, the new 8Gb DDR4 features the highest performance and energy efficiency for an 8Gb DRAM chip, as well as the smallest dimensions.

Samsung_1y-nm_8Gb_DDR4_Chp+Mod

“By developing innovative technologies in DRAM circuit design and process, we have broken through what has been a major barrier for DRAM scalability,” said Gyoyoung Jin, president of Memory Business at Samsung Electronics. “Through a rapid ramp-up of the 2nd-generation 10nm-class DRAM, we will expand our overall 10nm-class DRAM production more aggressively, in order to accommodate strong market demand and continue to strengthen our business competitiveness.”

Samsung’s 2nd-generation 10nm-class 8Gb DDR4 features an approximate 30 percent productivity gain over the company’s 1st-generation 10nm-class 8Gb DDR4. In addition, the new 8Gb DDR4’s performance levels and energy efficiency have been improved about 10 and 15 percent respectively, thanks to the use of an advanced, proprietary circuit design technology. The new 8Gb DDR4 can operate at 3,600 megabits per second (Mbps) per pin, compared to 3,200 Mbps of the company’s 1x-nm 8Gb DDR4.

To enable these achievements, Samsung has applied new technologies, without the use of an EUV process. The innovation here includes use of a high-sensitivity cell data sensing system and a progressive “air spacer” scheme.

In the cells of Samsung’s 2nd-generation 10nm-class DRAM, a newly devised data sensing system enables a more accurate determination of the data stored in each cell, which leads to a significant increase in the level of circuit integration and manufacturing productivity.

The new 10nm-class DRAM also makes use of a unique air spacer that has been placed around its bit lines to dramatically decrease parasitic capacitance**. Use of the air spacer enables not only a higher level of scaling, but also rapid cell operation.

With these advancements, Samsung is now accelerating its plans for much faster introductions of next-generation DRAM chips and systems, including DDR5, HBM3, LPDDR5 and GDDR6, for use in enterprise servers, mobile devices, supercomputers, HPC systems and high-speed graphics cards.

Samsung has finished validating its 2nd-generation 10nm-class DDR4 modules with CPU manufacturers, and next plans to work closely with its global IT customers in the development of more efficient next-generation computing systems.

In addition, the world’s leading DRAM producer expects to not only rapidly increase the production volume of the 2nd-generation 10nm-class DRAM lineups, but also to manufacture more of its mainstream 1st-generation 10nm-class DRAM, which together will meet the growing demands for DRAM in premium electronic systems worldwide.

Electronics manufacturing executives will sharpen their competitive edge in Dublin, Ireland, on 4-6 March at Europe’s SEMI Industry Strategy Symposium (ISS Europe). The three-day flagship business event brings together analysts, researchers, economists, technologists and industry leaders for critical insights into the forces shaping the electronics manufacturing supply chain. With Europe a key engine of global innovation and the supply chain, ISS Europe 2018 takes aim at helping European organisations find new ways to maximise competitive advantage.

“Organisations operating in Europe need to find the most effective way to innovate, manufacture and profit by leveraging their strengths in the global supply chain,” said Laith Altimime, president, SEMI Europe. “During ISS Europe 2018, hosted by SEMI Europe, top European companies, research institutes and public institutions will convene to discuss how to compete and win globally in the context of Europe’s strategic, economic and social needs.”

ISS Europe 2018 discussions will focus on successful manufacturing in Europe and mechanisms to support innovation. The speaker lineup includes:

  • David Bloss, VP, Technology Manufacturing Group, Intel
  • Holger Blume, professor, University of Hanover
  • Jean-Frederic Clerc, deputy CEO and CTO, CEA Tech
  • Kevin Cooney, senior VP and managing director, Global CIO, Xilinx EMEA
  • Jean-Christophe Eloy, CEO, Yole Développement
  • Ann-Charlotte Johannesson, CEO, CEI-Europe AB
  • Cheryl Miller, founder/executive director, Digital Leadership Institute
  • Michael Morris, director AMBER Research Centre, professor, Trinity College Dublin
  • Alain Mutricy, senior VP product management, GLOBALFOUNDRIES
  • James O’Riordan, CTO, S3 Group
  • David Sneddon, director of large customer sales for Central Europe, Google
  • Florien van der Windt, Cluster Manager Smart Mobility, Dutch Ministry of Infrastructure & Environment
  • Hanns Windele, vice president, Europe and India, Mentor Graphics, a Siemens Business

The Panel Discussion “Critical Strategies to Grow Europe in the Global Supply Chain” will highlight ISS Europe 2018 as participants take advantage of great networking opportunities such as an opening reception and a gala dinner announcing the 2017 European Award winner.

Join Europe’s strategic thinkers and business drivers at ISS Europe 2018 in Dublin, Ireland from March 4-6, 2018.