Greater collaboration for 2017 and beyond
Colin Cameron, Global Pads Business Director, CMP Technologies, Dow Electronic Materials
The global semiconductor industry is on the upswing right now, and we expect to see this extend into 2017. With respect to end-use markets driving the most growth, smartphones continue to be a major contributor. After a few years of declining growth, the PC market is leveling off and still comprises a significant share. Among the other notable segments are tablets, servers, and automotive.
Advanced storage applications such as servers and solid state drives are fueling growth in advanced chips and are creating new uses for 3D NAND flash memory, which is being increasingly used to store higher quantities of data in as small a footprint as possible. Going vertical increases density and generally reduces cost. The manufacturing process brings additional challenges compared to 2D, especially when considering the increased planarization needed for the increase in layers and their respective thicknesses. This puts more demand on the chemical mechanical polishing (CMP) step, which is being used to a greater extent.
This year, we’re seeing the emergence of production at the 10nm node, supporting trends in consumer devices such as advanced smartphone design and high-end graphic processors to support streaming video. Implementation for 10nm has shown the tremendous value in deeper collaboration between semiconductor manufacturers and materials suppliers. Manufacturers are increasingly in need of customized solutions, and suppliers are working more directly with their customers to ensure that advanced technologies can be manufactured reliably.
China’s semiconductor market has been growing rapidly, and its local IC industry continues to develop, with manufacturers bringing new production on line and more new construction starting in 2017. This scaling is creating demand throughout the semiconductor supply chain.
As a consumables supplier, we’ve been developing new CMP solutions that offer both performance improvements for future technology nodes as well as cost of ownership benefits for mature nodes. When planning for 7nm and beyond, the smaller geometry will significantly tighten specifications for defect levels and planarization. Narrower process margins may require new materials tailored for each application, making collaboration more critical than ever in the new year.