BY PHIL GARROU, Contributing Editor

At the recent IEEE 3DIC Conference, Koyanagi and co-workers at Tohoku Univ reported on their studies of Ti as a 3D TSV barrier layer.

Cu was substituted in the early 2000s for Al inter- connect wiring which no longer meet the resistivity requirements in the aggressively scaled technology nodes. Cu, which has low electrical resistivity has proved itself as a potential interconnect material, only if necessary barrier layers are in place.

The most serious concern with Cu as interconnect material is the formation of midgap defects in active Si, since it diffuses fast into the Si. Owing to this, the minority carrier life time is reduced several orders even at 200 °C. Moreover, during this diffusion process since Cu travels through SiO2, the insulation nature of SiO2 is degraded which can result in premature dielectric breakdown leading to device failure. The well-known method to prevent Cu diffusing into SiO2 and then in Si is to sandwich an amorphous metal layer between the Cu and SiO2. Required properties of a good barrier layer are low internal film stress, high thermal stability and low resistivity. Metals with high melting points are known to have larger activation energy for the diffusion to take place.

Although Ta is best suited as a barrier material based on melting point, Ta has more integrated film stress than Ti film, i.e. a 200nm-thick sputtered Ta film possesses internal stress of 1.4 GPa, whereas the stress in a similar thickness Ti film is 0.8 GPa . Internal stress is the main cause for the delamination of sputtered Ta films. Thus Ti is a better barrier layer based on internal stress.
One way to improve the barrier performance of Ti, is to use a Ti/TiN structure as barrier layer, but TiN has a large resistivity (p~270 μ.cm) .

The Tohoku group has found a simple method to improve the barrier ability of Ti layer is to anneal the TSV structures in vacuum at temperatures up to 400°C. This results in a significant improvement in leakage current characteristics for SiO2 dielectric. TiSix has been identified at the interface between Cu and SiO2 during the sputter deposition.

Another presentation by Tohoku University examined the reduction of the keep-out-zone in 3DIC by local stress suppression with negative-CTE filler.

The thinning of the IC chips leads to low flexural rigidity of IC chips. In addition, the CTE of the underfill material is larger than that of metal microbumps. In other words, the underfill material shrinks more compared to metal microbumps. IC chips are bent by this shrinkage after the 3D integration process. This CTE mismatch induces local bending stress in thinned Si chips, and in turn effects the MOSFET electrical performance in thinned Si chips.

In general, SiO2 or Al2O3 filler have been introduced into the underfill to reduce the CTE of underfill. High density filler is required to realize a CTE close to the value of the microbumps.

However, it is difficult to use the conventional density underfill for 3D IC with fine pitch microbumps due to its high viscosity. What’s required is a low viscosity low CTE underfill.
The Tohoku group suggests a negative CTE material as the filler to suppress the local bending stress. They used manganese nitride-based negative-CTE material as filler. The CTE of this material is -45 ppm/K at the temperature from 65 °C to 100 °C.